Claims: A loadable programmable Shift Register (pSR), said pSR being configured to receive a programmable input Load Location (LL) that defines where data D is to be loaded from the Load Register when L (Load Control Signal) = 1. The pSR of claim 1, wherein the pSR with programmable load location (pSRL) comprises a bit-remapper function d that receives L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and based on n (n+1):1 multiplexers and pi’, outputs a load vector, wherein pi’ = (LL-1) when ((L = 1, S = 0) and (LL = i)), else if (S = 1), pi’ = p + i, else pi’ = i. The pSR of claim 2, wherein the pSRL receives the L (Load Control Signal), the S (Shift Control Signal), the LL (Load Location Control Signal), and the p (programmable shift value) from any or combination of a control Finite State Machine (FSM), a programmable logic device (PLD), or a software application. The pSR of claim 2, wherein if L=1 and S =0, di = Di-LL if LL = i = min (n, (LL+m)), else di = di. The pSR of claim 2, wherein if L=0 and S =1, di = di+p if i < (n-p), else di = 0. The pSR of claim 2, wherein if L=1 and S =1, di = di+p if i 1, then loading happens to the left of bit 1 and d1 stays uninvolved. This is a total of (n + 1) values. Similarly, bit 2 could get its own value, one of (n – 2) bits to its left or only bits 1 and 2 of the load register (D1 or D2). It would get D1 if LL = 2, and it would get D2 if LL = 1. This is a total of (n + 1) values. Continuing, bit 3 could get its own value, one of (n – 3) bits to its left or bits 1, 2 or 3 of the load register (D1, D2 or D3). It would get D1 if LL = 3, D2 if LL = 2 and D3 if LL = 1. Once again, this is a total of (n + 1) values. Generically, bit r gets its own value, one of (n – r) bits to its left or one of r bits {1, 2, 3 … r} of the load register – D1, D2, D3 … Dr. It gets D1 if (LL = r), D2 if LL = (r – 1), D3 if LL = (r – 2) and so on. This is a total of (n + 1) values. Thus, in general bit r gets the value of bit D(r – LL + 1) if LL = r. If LL > r, then bit r either may either get a shifted value or hold its previous value. From above results it may be noted that, at most n (n + 1):1 multiplexers are needed for the implementation. The multiplexer size starts reducing from the (n – m + 1)th bit onwards because there are fewer bits on the left to choose from while shifting. The nth bit can only get its own value or one of m values from the load register, since it does not have bits on its left. FIG. 5B illustrates an exemplary implementation of the proposed loadable programmable shift register with programmable load location (pSRL), in accordance with an embodiment of the present disclosure. In an embodiment, FIG. 5B illustrates the proposed loadable programmable shift register with an additional input that defines where data is loaded (pSRL). It is to be appreciated that for the exemplary implementation purpose, D1, D2, D3 … etc. are connected in the reverse order of d2, d3, d4… etc, which enables a simple way of realizing the expression (r – LL + 1), since bit r will get the value of bit D(r – LL + 1) from the load register while loading. In an exemplary embodiment, in an implementation, the proposed pSRL focuses on the way pi’ is computed, wherein using the implementation as illustrated in FIG. 5C, for pi’ generation for the pSRL: p1’ is realized by: if ((L = 1, S = 0) and (LL = 1)) p1’ = (LL – 1) else if (S = 1) p1’ = p + 1 else p1’ = 1 if (L = 1, S = 0) and (LL = 3): LL p1’ selects 1 0 D3 2 1 D2 3 2 D1 else if (S = 1) p p1’ selects 1 4 d4 2 5 d5 3 6 d6 … … … else X 3 d3 p2’ is realized by if ((L = 1, S = 0) and (LL = 2)) p2’ = (LL – 1) else if (S = 1) p2’ = p + 2 else p2’ = 2 if (L = 1, S = 0) and (LL = 2): LL p2’ selects 1 0 D2 2 1 D1 else if (S = 1) p p2’ selects 1 3 d3 2 4 d4 3 5 d5 … … … else X 2 d2 p3’ is realized by: if ((L = 1, S = 0) and (LL = 3)) p3’ = (LL – 1) else if (S = 1) p3’ = p + 3 else p3’ = 3 if (L = 1, S = 0) and (LL = 3): LL p3’ selects 1 0 D3 2 1 D2 3 2 D1 else if (S = 1) p p3’ selects 1 4 d4 2 5 d5 3 6 d6 … … … else X 3 d3 pi’ is realized by: if ((L = 1, S = 0) and (LL = i)) pi’ = (LL – 1) else if (S = 1) pi’ = p + i else pi’ = i if (L = 1, S = 0) and (LL = p): LL pi’ selects 1 0 Dp 2 1 Dp-1 3 2 Dp-2 … … … p p–1 D1 else if (S = 1) p pi selects 1 1+p dp+1 2 2+p dp+2 3 3+p dp+3 … … … else X p dp Thus, it may be noted form the above that, the n (n + 1):1 multiplexers and pi’ together defines the bit re-mapper function d, which is a complete solution for a pSRL. FIG. 5C illustrates an exemplary conceptual block diagram of the proposed loadable programmable shift register with programmable load location (pSRL) as illustrated in FIGs. 5A-B with a bit-remapper function (d) 594, in accordance with an embodiment of the present disclosure. The proposed loadable programmable shift register includes with an additional input that defines where data is loaded (pSRL). Considering the above analysis representations and analysis, FIG. 5C illustrates the block diagram of pSRL. As shown in FIG. 5C, the bit-mapper function d (also interchangeably referred to as bit-mapper d 594) receives a data (Din) from a load register having a data width (M) 592 along with at least one of control inputs 582 that control at least one of load location (LL) of data 584, loading (L) of data 584, shifting (S) of data 588, and a programmable shift value (p) 590. It may be noted from the above that, FIG. 5C provides a generalized programmable shift register with programmable load location which serves as a storage. In an exemplary embodiment, the proposed loadable programmable shift register with programmable load location (pSRL) 580 is provided. The pSRL being configured to receive a programmable input LL 584 that defines where data D is to be loaded from the Load Register when L (Load Control Signal) = 1. In an exemplary embodiment, the pSR with programmable load location (pSRL) includes a bit-remapper d 594 function that receives L (Load Control Signal) 586, S (Shift Control Signal) 588, LL (Load Location Control Signal) 584, and p (programmable shift value 590, and based on n (n+1):1 multiplexers and pi’, outputs a load vector, wherein pi’ = (LL-1) when ((L = 1, S = 0) and (LL = i)), else if (S = 1), pi’ = p + i, else pi’ = i. In an exemplary embodiment, the pSRL receives the L (Load Control Signal), the S (Shift Control Signal), the LL (Load Location Control Signal), and the p (programmable shift value) from a control Finite State Machine (FSM) (not shown). In an exemplary embodiment, if L=1 and S =0, di = Di-LL if LL = i = min (n, (LL+m)), else di = di. In another aspect, if L=0 and S =1, di = di+p if i < (n-p), else di = 0. In yet another aspect, if L=1 and S=1, di = di+p if i