FIELD OF INVENTION

The present invention relates to a design of Linear Variable Differential Transformer (LVDT) signal conditioner Integrated Circuit containing modules of signal generator, driver, signal conditioner, demodulator and filter amplifiers all integrated on a monolithic silicon substrate to give out proportional or ratio metric outputs from the differential inputs from a LVDT. The IC can be configured to function in the Ratio metric mode or in the proportional mode of operation.

BACKGROUND AND PRIOR ART

Linear variable differential transformers (LVDTs) are theoretically infinitesimal-resolution displacement measurement devices. LVDTs operate on the principle of transformer, having stationary, primary and secondary coil assembly and a moving core. The transformer's internal structure consists of a primary winding centered between a pair of identically wound secondary windings, symmetrically spaced about the primary coil. The coil assembly is typically mounted to a stationary form, while the core is secured to the object whose position is being measured. A core of permeable material can slide freely through the center of the form. The primary coil is excited by an AC source. Magnetic flux produced by the primary coil is coupled to the two secondary coils, inducing an AC voltage in each coil.

When the core is centered perfectly between both secondary and the primary coils, the voltage induced in each secondary is equal in amplitude. If the core is displaced a small amount from the null position, the flux coupling to one secondary winding increases while to the other winding decreases. The result is a differential voltage output signal which is a sinusoidal waveform of the same frequency as the input excitation signal and has amplitude proportional to the displacement of the core from the null position. The differential output signal is either fully in phase or fully in anti- phase with the signal applied to the primary coil, depending on the direction of the core displacement. In order to obtain useful information from LVDT a suitable signal conditioner is required to process the LVDT secondary signals to derive a DC output voltage from which the position and direction of LVDT core can be deduced.

The LVDT signal conditioner circuit can be designed in the following modes of operation

1. Differential
2. Ratio metric
3. Proportional

Differential operation

When operating in Differential mode, the center tap of the output windings is often not used and me secondary windings are connected in series opposition. The output Voltage is measured across the transformer secondary winding. When we displace the core from the center (null position), the output will increase in phase with the excitation when moved in one direction, and out of phase with the excitation when moved to the other direction. The output AC signal is de-modulated and translated to a linear DC signal which is proportional to the displacement. The output equation is: Vo = A K (T) (vla-v2a) Vpri (T) Where Vo : output voltage

A : Amplifier Gain
K (T) : Transfer function of LVDT
via, v2a : Secondary induced voltages
Vpri (T): Primary excitation From the above equation it is evident that, the output DC voltage will be directly affected by the parameters like Operating Temperature, core temperature, Excitation level and drift, phase shift between the primary and secondary, noise in the LVDT.

Ratio metric Operation

In the ratio metric mode, the difference of the secondary voltages is divided by the sum of the secondary voltages.

Vo α A [{K(T)(vla-v2a)Vpri(T)} / { K(T)(vla+v2a) Vpri(T) }]
Vo α A [ (vla-v2a)/ (vla+v2a)]

Any change due to temperature or excitation variation therefore no longer affects the output.

Proportional Operation

In the proportional mode, the difference of the secondary voltages is divided by the excitation Voltage.

Vo α [A K(T)(vla-v2a)Vpri(T)]/ Vpri(T) VoαAK(T)(vla-v2a)

Here the output is no longer dependent on the stability of the excitation voltage. The core direction information can be obtained by employing one of the techniques

1. Synchronous Demodulation

2. Direct Conversion method

In the Synchronous Demodulation method the Phase derived from the output signal is compared with the excitation signal to obtain the direction information. The synchronous demodulation method depends on the accuracy of the phase error, in addition, there are losses associated with the demodulation, which usually involve switches and the charge injection and timing jitter also the synchronous demodulation method increases the circuit complexity and power requirement. In this present disclosure, the inventors have presented the Direct Conversion concept and explained how the phase error is addressed in a better way and thus improving the accuracy of the positional information and noise performance. The methodology of demodulation and subsequent realization of ratio metric and proportional outputs are also explained.

US2012036396 (Al) titled "Built in self test using embedded memory and processor in an application specific integrated circuit" describes a printer comprising of an application specific integrated circuit (ASIC) which has a processing core and a memory that contains the test routines for execution from an embedded memory or an external memory. It has an interface coupled to the processing core which permits the activation of the first output signal indicating a test result. Therefore during ASIC production the test routines can test the blocks of the ASIC without a complicated test pattern from the test equipment.

US7893687 titled "LVDT acquisition device with dual demodulation subsystem" describes a device for decoding signals at the output of a Linear Variable Differential Transformer (LVDT) which has a primary coil, two secondary coils and a slidable ferromagnetic part. The device includes an analog to the digital converter which is connected to the output of both the secondary coils and produces the digitized outputs. These outputs are multiplied by a multiplier module and the position error of the ferromagnetic part is calculated by error calculation module. Thus the error signals have lower dependence on phase shift and the accuracy is enhanced.

The present invention LVDT signal conditioner ASIC, BE5061 performs the below mentioned operations:

1. Primary excitation signal generation and drive
2. Processing of the secondary signals of the LVDT to obtain the Sum and Difference signals
3. Unique divide operation to obtain the ratio metric or proportional outputs

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS

Figure 1 shows the block diagram of the LVDT Signal Conditioner ASIC

Figure 2 shows the packaged LVDT Signal Conditioner ASIC.

Figure 3 shows the Pin diagram of LVDT Signal Conditioner ASIC.

Figure 4 shows the physical design view of the Application Specific Integrated Circuit (ASIC).

Figure 5 shows the operation of ASIC in ratio metric mode for a ratio of -0.9.

Figure 6 shows the operation of ASIC in ratio metric mode for a ratio of 0.9.

Figure 7 shows the Linearity graph of LVDT ASIC output in ratio metric mode of operation, the graph is plotted for Vo (output of ASIC) versus Displacement of the core (normalized).

DETAILED DESCRD7TION OF THE PREFERRED EMBODIMENTS

Figure 1 describes the primary embodiment of the present disclosure which is a LVDT signal conditioner ASIC 100 consists of an internal oscillator 117, primarydriver 104, differential amplifier 111; precision rectifiers 105,106, 112; filters 107,108,113; adder 110; subtractor 109; divider (PWM generator) 114; demodulator filter 115; demodulator amplifier 116, an uncommitted Op amp 138.

In an embodiment of the present disclosure, the internal oscillator 117 comprises of square wave generator 101, integrator 102, sine shaper 103, and a provision to program the frequency from 500 Hz to 10 KHz.

Further another embodiment of the present disclosure comprises the primary driver 104, which has programmable voltage from 2.1Vrms to 15Vrms.

One more embodiment of the present disclosure comprises the precision rectifiers 105,106 and filters 107,108 to convert the Secondary AC Signals 121,122 to DC Voltages.

Further another embodiment of the present disclosure comprises the adder 110 to get the sum 129 and the subtractor 109 to get the difference value of the secondary DC voltages.

Further another embodiment of the present disclosure comprises the differential amplifier 111 precision rectifiers 112 and filter 113 to convert the Primary Excitation

Signal 123,124 to obtain primary excitation DC Voltage 128.

Further another embodiment of the present disclosure comprises the divider (PWM operation) 114 which takes the denominator input. The denominator can be the sum 129 or primary DC signal 128 to operate in ratio metric or proportional mode respectively.

Further another embodiment of the present disclosure comprises the demodulator filter 115 and demodulator amplifier 116 to provide DC output 133 from which the positional and directional information of the LVDT core from the null position can be deduced.

Further another embodiment of the present disclosure comprises an uncommitted amplifier 138 which can be used as an independent operational amplifier.

Features

• Monolithic LVDT signal conditioner IC
• Insensitive to LVDT Primary to Secondary phase shifts
• Dual Supply operation (±15 V)
• Temperature compensated
• Programmable sine wave frequency (500 Hz to 10 kHz)
• Programmable sine wave amplitude (2.1 Vrms to 15 Vrms)
• Bipolar Demodulated output (±11 V )
• Configurable option to select proportional or ratio metric mode of operation.
• Can interface different type of LVDTs where the sum of secondary signals may or may not be constant with stroke length.
• Can also interface LVDTs having independent primary excitation.

The oscillator section 117 comprises a Square wave generator 101 whose frequency can be programmed from 500 Hz to 10 kHz by means of an external capacitor 125. The integrator 102 feeds a Sine wave shaper 103 that produces a sine wave whose magnitude can be programmable from 2.1 to 15 Vrms using external resistor 126. The driver amplifier 104 has an offset null adjustment provision 127. The driver amplifier 104 output 119,120 drives the primary of the LVDT 134.

The demodulator 118 process the AC output of the LVDT 134 secondaries 121,122 to derive the DC voltage. This DC output represents the core position (magnitude as well as direction).The demodulator 118 comprises of precision full wave rectifiers 105 106 112, Butterworth low pass filtersl07,108,113 and divider 114 modules. The signals from the secondary 121, 122 of LVDT are fed to the Precision Full wave rectifiers 105,106 and passed through a filter 107,108 to get DC signals, say VIA and V2A. Provision has been given to opt for the filters to function either in the Ist order or IInd order. The signals VIA and V2A are insensitive to the phase shift that mayoccur between the LVDT Primary and the Secondary as the peak of the signal is derived. The DC signals are added 110 and subtracted 109 to get (V1A+V2A) and (V1A-V2A) respectively. The primary excitation signal is also rectified and filtered to get 128 say Vpri. The divider module works on a unique Ratio metric / Proportional architecture. This architecture does not require a highly stable magnitude excitation.

Ratio metric Operation

The Ratio metric operation for [(V1A-V2A)/ (V1A+V2A)] setup is implemented by dividing the subtracted signal, (V1A-V2A) (Numerator), by the sum signal, (V1A+V2A). The division is achieved by means of PWM architecture by varying the duty cycle proportional to the core position. As an example for

1. via = v2a (null position) i.e. core is at the center, the PWM duty cycle D = 0.5
2. via > v2a i.e. core towards via direction D > 0.5
3. via < v2a i.e. core towards v2a D < 0.5. where D = Ton / T; T = Ton + Toff
via, v2a are instantaneous voltages of LVDT secondaries 121,122

VIA, V2A are the DC voltages from 107,108 The [(V1A-V2A)/ (V1A+V2A)] output is independent of primary and secondary temperature variations, i.e. any change in the VIA and V2A will result in the same change in the numerator and denominator resulting constant ratio and hence insensitive to temperature variations of primary and secondary, phase differences between primary and secondary, the output is also independent of transformer variations .

Proportional Operation

The ASIC can be configured to operate in Proportional mode [(VIA-V2A)/ Vpri].The Proportional operation for [(V1A-V2A)/ Vpri] setup is effected through dividing the subtracted signal, (V1A-V2A) (Numerator), by the primary excitation reference signal, Vpri 128. In case of LVDTs that do not guarantee (V1A+ V2A) constant over stroke length, (V1A-V2A)/Vpri operation can be used. This, however, cannot work well with the temperature uncompensated LVDTs. The divider generates a PWM, the duty cycle of which is proportional to [(VIA-V2A)/ Vpri]

The PWM duty cycle is filtered to get an equivalent DC voltage, the magnitude of which represents the core position and sign provides the direction of core movement about the transformer null. This DC value is further scaled in the final demodulator amplifier 116 to the required level. The final amplifier has an offset null 131 and gain adjustment provision 132. The final DC output 133 from which the position and direction information can be deduced is in accordance to the equation

Vout =K*[(vla-v2a)/ (vla+v2a)] for Ratio metric operation Vout =K*[(vla-v2a)/ (Vpri)] for proportional operation

Where K is a constant value comprising of reference voltage and gain

Therefore the demodulator processes the secondary output of the LVDT to give out a temperature compensated and offset neutralized DC output voltage from which the positional information and direction can be deduced. The Ratio metric scheme, employed in this ASIC, is quite advantageous in that LVDT primary to secondary phase shifts have negligible effect on overall demodulator circuit performance. Figure 2 shows the photograph of the packaged LVDT Signal Conditioner ASIC, assembled in a 44pin CQFP package.

Figure 3 shows the Pin diagram of the 44 pin LVDT Signal Conditioner ASIC with the named signals.

Figure 4 depicts the physical design topography of the ASIC which exhibits a specialty and innovation in the layout art.

Chip Size : 5.4*4.43 mm2
Process : Bipolar 45V process
Number of Pads : 44
Package : CQFP

Figure 5 shows the graphical representation of the output of the ASIC for the ratio i metric operation.

Ratio = [(vla-v2a)/ (vla+v2a)] = - 0.9; for vla=0.2Vp, v2a=3.8Vp where via, v2a are secondary voltages 121,122 of LVDT

The VOUT graph shows the output of LVDT ASIC for the above mentioned inputs

Figure 6 shows the graphical representation of the output of the ASIC for the ratio metric operation.
Ratio = [(vla-v2a)/ (vla+v2a)] = + 0.9; for vla=3.8Vp, v2a=0.2Vp

where via, v2a are secondary voltages 121,122 of LVDT The VOUT graph shows the output of LVDT ASIC for the above mentioned inputs

Figure 7 shows the Linearity of the LVDT ASIC for ratio metric operation where x axis represents the Ratio = [(vla-v2a)/ (vla+v2a)] and y axis represents the output of the ASIC. The graph is plotted for 3 temperatures at -55°C, 27°C and 125°C.

The output of ASIC variation over temperature is about 20ppm/°C

WE CLAIM

1. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit for fine-grained resolution displacement measurement having a signal generator module, an integrated oscillator and driver 117 module for driving the primary of LVDT 134, an integrated demodulator 118 for the demodulating secondary signal of the LVDT 134 having a Differential amplifier, one or more Precision Rectifiers, one or more filter amplifiers, subtracter, adder, divider, Amplifiers wherein the output of the device is configured to select for a ratio metric or proportional operation.

2. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1 wherein the integrated oscillator 117 module has a frequency which can be programmed externally from 500 Hz to 10 kHz by an external capacitor 125.

3. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1 wherein the drive Amplifier 104 modules provides the excitation required for the LVDT 134 primary coil, wherein the excitation voltage 119,120 can be programmed externally from 2.1 Vrms to 15 Vrms by external resistors 126,120 and the offset can be adjusted 127.

4. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1, wherein Demodulator 118 rectifies and processes the signals from the secondary 121,122 of the LVDT 134.

5. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1, wherein the Demodulator 118 processes the signals from the primary 123, 124 of the LVDT 134 to obtain the DC Voltage 128.

6. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1, wherein the Filter 107, 108,113 can be configured as first order or second order.

7. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1, wherein the Divider 114 can take inputs to operate in the Ratio metric 129 mode.

8. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1, wherein the Divider 114 can take inputs to operate in the Proportional 128 mode.

9. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1, wherein the signal conditioner has the division 114 that is performed through a unique PWM operation where the duty cycle is varied in accordance to the position of the core.

10. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1, wherein the signal conditioner module has the PWM wave filtered in the Demodulator Filter 115 which is a Second order Butterworth Filter such that this DC voltage can be scaled by programming the gain of the demodulator amplifier 116 through programmable resistors 132,133 with offset adjustment 131.

11. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1, wherein the signal conditioner has a DC Voltage proportional to the displacement of the core from the null position, the magnitude gives the distance and polarity gives the direction of the core from the null position

12. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1, wherein the signal conditioner has the advantage that the output is insensitive for phase shifts between the primary and secondary and also independent of temperature variation.

13. An improved monolithic Linear Variable Differential Transformer (LDVT) signal conditioner Integrated circuit of Claim 1, wherein the signal conditioner, wherein all the modules in Claiml, is embodied in an ASIC, is fabricated on silicon using 45V Bipolar Process and assembled in a 44pin CQFP package such that the ASIC is designed to operate for a wide operating temperature, -55 °C to 125°C.