PROTECTION DEVICE FOR POWER CONVERTER AND PROTECTION
METHOD
FIELD OF THE INVENTION
The present invention relates to a protection device for a power converter formed of plural power switching elements and a protection method, and more specifically to a protection device for a power converter in a configuration suited to the detection of device destruction and restriction after the detection of the device destruction and a protection method.
BACKGROUND OF THE INVENTION
A power converter has a function of generating alternating-current power in which plural switching elements are operated to convert direct current power into a voltage equivalent to an alternating voltage command at a given amplitude and frequency.
There are some configurations of the power switching elements of this power converter. In these configurations, in a three-level power converter adopting a circuit configuration including four types of switching elements, for example, a command signal for a switching pattern is given to a gate driver in response to the reception of an alternating voltage command, the switching elements switch on or off, and a voltage equivalent to the alternating

voltage command Is outputted at an alternating current output end.
Moreover, in a power converter that aims to increase a power capacitance in which switching elements are formed in multiple stages as two or more of switching elements are serially connected and applicable voltages are increased, the same switching command is given to the switching elements serially connected in multiple stages to switch on or off, and a voltage equivalent to an alternating voltage command is outputted.
The configurations of switching elements and control methods for the switching elements of these power converters are described in detail in Japanese Unexamined Patent Application Publication No. 2009-165348 and Japanese Unexamined Patent Application Publication No. 2008-86096, for example.
SUMMARY OF THE INVENTION In the power converters configured of plural switching elements, in the case where one of the switching elements operates differently from an on command or off command because of a failure or malfunction, for example, a direct current short circuit is induced, and secondary damage occurs such as a failure of a main circuit. Moreover, there is a problem in that short circuit energy

is increased because of the provision of higher voltages and damage in a fault is great.
On the other hand, there are previously existing methods for detecting a short circuit using a fuse and for preventing the expansion of damage, and there is a method as Japanese Unexamined Patent Application Publication No. 2009-165348 in which a time period during which a command pulse signal for a voltage control element is not matched with a gate feedback signal expressing the On-state or Off-state of the voltage control element is counted, it is observed that the signals are not matched with each other for a predetermined time period or longer, and an abnormality in the voltage control element is detected.
However, in the protection method using a fuse, although it is possible to suppress the range of damage better than the case where no fuse is provided, a time period until a fuse blows is longer than a time period until the switching element fails. Thus, there is a problem in that some kind of damage is given to all switching elements located on an electric current short circuit path.
Moreover, in the method in which a command pulse signal for a faulty element is compared with a feedback signal for detection, there is a problem in that in the case where the influence of an element failure or the

influence of secondary damage such as a direct current short circuit caused by an element failure is extended to a detection circuit and in the case where such an event occurs that a failure of the faulty element cannot be detected, a direct current short circuit occurs and secondary damage cannot be prevented.
From the description above, it is an object of the present invention to provide a power converter and a protection method that can more reliably detect an element failure, can aim to prevent the expansion of secondary damage, and can suppress increases in restoration time and restoration costs.
In order to achieve the object, the present invention is a protection device for a power converter in which an upper arm and a lower arm are formed of a series circuit of plural switching elements, a ground is connected from a midway point of the upper arm and the lower arm through a diode, a ground is connected from a connecting point of the upper arm and the lower arm through a load, and DC power supplies are connected to both ends of the upper arm and the lower arm. The plurality of the switching elements forming the arms individually include an overvoltage suppression circuit including a clamping element connected between a collector and a gate, a signal generator circuit that applies a gate signal to the gate, and an overvoltage

detection circuit disposed in parallel with the signal generator circuit. When an overvoltage occurs on the switching element, the overvoltage detection circuit monitors duration of the overvoltage from a clamp current obtained from the overvoltage suppression circuit and detects a failure of the switching element.
As described above, according to the present invention, it is possible to provide a power converter that can decrease secondary damage when a switching element fails, and can suppress restoration time and restoration costs.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of a first embodiment of the present invention for stopping the development of a failure;
FIG. 2 is a diagram of the electric current waveforms and voltage waveforms of elements when a failure is developed in a previously existing circuit;
FIG. 3 is a diagram of the electric current waveforms and voltage waveforms of elements when a failure is developed in the first embodiment.
FIG. 4 is a diagram of the configurations of a main body and a control device in one phase in three phases of a power converter;

FIG. 5 is a diagram of exemplary signal waveforms of the elements of the power converter in FIG. 4;
FIG. 6 is a diagram of the situations of the development of a failure mode in the case where an element
QNC2 in FIG. 4 fails;
FIG. 7 is a diagram of another exemplary
configuration of the main body and another exemplary configuration of the controller in one phase in three phases of the power converter;
FIG. 8 is a diagram of the situations of the development of a failure mode in the case where an element QNC in FIG. 7 fails;
FIG. 9 is a diagram of a second embodiment of the present invention for stopping the development of a failure;
FIG. 10 is a diagram of the electric current waveforms and voltage waveforms of elements when a failure is developed in a previously existing circuit; and
FIG. II is a diagram of the electric current waveforms and voltage waveforms of elements when a failure is developed in the second embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, embodiments of the present invention will be described with reference to the drawings,

It is noted that in the description of the drawings and the embodiments below, the description will be made as an IGBT and a Zener diode are taken as examples for switching elements. However, the similar effect can be obtained by a configuration in which the IGBT for a switching element is replaced by a MOS gate semiconductor other than the IGBT and the Zener diode is replaced by a clamping element that carries an electric current when a voltage at a certain threshold or greater is applied.
First Embodiment
First, the basic configuration and operation of a power converter to which the present invention is applicable will be described. FIG. 4 is the extraction of the configurations of a main body (a power converter 100a) and a controller (a pulse duration modulation circuit 200) in one phase (a U phase) in three phases of the power converter (the U phase, a V phase, and a W phase). Since the configurations of the main body and the controller are the same in the U phase, the V phase, and the W phase, only the configurations in the U phase will be described below.
In FIG. 4, the power converter 100a that is the main body is configured of plural switching elements connected in series. In the embodiment of the present invention, the

switching elements are configured of IGBTs, and form a series circuit using IGBTs QPl, QP2, QPCl, QPC2, QNCl, QNC2, QNl, and QN2. In the IGBT series circuit, an upper arm is formed of four upper elements QPl, QP2, QPCl, and QPC2, a lower arm is formed of four lower elements QNCl, QNC2, QNl, and QN2, and a load 3 is connected between a midway point P12 of the upper arm and the lower arm and a ground. Moreover, a diode series circuit formed of clamp diodes DCPl, DCP2, DCNl, and DCN2 is provided between a midway point P13 of the four upper elements QPl, QP2, QPCl, and QPC2 and a midway point P14 of the four lower elements QNCl, QNC2, QNl, and QN2.
A voltage E is taken from direct current voltage sources Ipa and Ina at both ends of the series circuit formed of the IGBTs. A midway point P15 of the diode series circuit and a midway point P16 of the direct current voltage sources are then grounded in common.
The power converter side that is the main body is configured as described above, and the pulse duration modulation circuit 200 on the control side is configured as follows. First, four gate amplifiers GAlu, GA2u, GA3u, and GA4u are included in the last stage of the pulse duration modulation circuit 200 that is a control circuit. In these gate amplifiers, a switching pulse Glu from the gate amplifier GAlu is given to gate drivers 110 of the

upper elements QPl and QP2 of the IGBT series circuit, a switching pulse G2u from the gate amplifier GA2u is given to gate drivers 110 of the lower elements QNCl and QNC2 of the IGBT series circuit, a switching pulse G3u from the 5 gate amplifier GA3u is given to gate drivers 110 of the upper elements QPCl and QPC2 of the IGBT series circuit,
and a switching pulse G4u from the gate amplifier GA4u is given to gate drivers 110 of the lower elements QNl and QN2 of the IGBT series circuit. According to this turning-
10 on method, the upper elements QPl and QP2, the lower
elements QNCl and QNC2, the upper elements QPCl and QPC2, and the lower elements QNl and QN2 of the IGBT series circuit are configured as an integrated device driven by the same switching pulse for use.
15 Moreover, the gate amplifiers GAlu and GA2u and the gate amplifiers GA3u and GA4u receive switching pulses from comparators Cmpl and Cmp2, respectively. One of the gate amplifiers GAlu and GA2u and one of the gate amplifiers GA3u and GA4u receive inverted switching pulse
20 signals from inverting circuits Notl and Not2. As a result, when switching pulses are given to the upper elements QPl and QP2, the inverted switching pulses of the switching pulses are given to the lower elements QNCl and QNC2, and when switching pulses are given to the lower elements QNl
25 and QN2, the inverted switching pulses of the switching

10
pulses are given to the upper elements QPCl and QPC2.
FIG. 5 is a diagram of exemplary signal waveforms of the elements of the power converter in FIG. 4. According to the drawing, the relationship among the inverted 5 signals of the switching pulse signals Glu, G2u, G3u, and G4u are clearly illustrated. The switching pulse signals Glu, G2u, G3u, and G4u are depicted by two values, on and off.
Moreover, in the control device configuration in FIG.
10 4, the comparators Cmpl and Cmp2 define the turning on and off of the switching pulse signals Glu, G2u, G3u, and G4u by the comparison of the size of a triangular wave CrSl with the sizes of alternating voltage commands Vu*p and Vu*N in the U phase. It is noted that in FIG. 4, G31
15 denotes a carrier wave generator for the triangular wave Cr31, Bl denotes a bias circuit, 2f denotes an adder, and Ml denotes a multiplication circuit that provides a desired direct current voltage Er. As illustrated in FIG. 5, the triangular wave Cr31 is a triangular waveform
20 changed between a potential zero and a potential of +Er/2. The alternating voltage command Vu*p is a sinusoidal waveform whose center value is a potential of zero, and the alternating voltage command Vu*N that a potential of +Er/2 is added to the alternating voltage command Vu*p is
25 a sinusoidal waveform whose center value is a potential of

11
+Er/2.
According to these exemplary signal waveforms of the elements of the power converter in FIG. 5, the alternating voltage waveforms Vu*, Vv*, and Vw* desired to be 5 outputted are given to the pulse duration modulation
circuit 200, the turning on and off of the switching pulse signals Glu, G2u, G3u, and G4u is determined by the comparison of the size of the triangular wave Cr31 with the sizes of the alternating voltage commands Vu*p and
10 Vu*N in the U phase, and finally, a voltage Vu at the output end of the inverter is determined.
The output pattern of the voltage Vu at the output end of the inverter has three patterns as illustrated in the lower side in FIG. 5, pattern A in which the switching
15 pulses Glu and G3u are on and the output voltage is a
voltage of +E, pattern B in which the switching pulses G2u are G3u are on and the output voltage is a voltage of zero, and pattern C in which the switching pulses G2u and G4u are on and the output voltage is a voltage of -E. It is
20 noted that a time period for which the potential is a
voltage of +E or -E is controlled, so that a sinusoidal waveform can be obtained for an alternating waveform after filtered.
FIG. 6 is a diagram of the situations of the
25 development of a failure mode in the case where the

12
element QNC2 fails, which is one of the IGBTs of the circuit illustrated in FIG. 4. Here, suppose that an exemplary switching pattern is pattern A in FIG. 5. It is noted that since this development of a failure can be 5 similarly occur when switching patterns are patterns in B and C in FIG. 5, pattern A will be specifically described in the following description.
In exemplary switching pattern A, the switching pulses Glu and G3u are on and the output voltage is a
10 voltage of +E, the upper elements QPl, QP2, QPCl, and QPC2 are in the On-state, and an electric current is carried at this time as a route AAl in the upper part in FIG. 6. An electric current is carried along the route from the ground through the terminal P16, the direct current
15 voltage source Ipa, the upper elements QPl, QP2, QPCl, and QPC2, the terminal P12, and the load 3, to the ground.
Suppose that the conduction of the lower element QNC2 fails in this conduction state as in the upper part in FIG. 6. In other words, suppose that the conduction of the
20 element QNC2 fails in two elements, the element QNCl and the element QNC2, which are integrally turned on and operated. In this case, it is possible that voltages for two elements, the elements QNCl and QNC2, are applied to the element QNCl, which is one of the elements connected
25 in series, the voltage applied to the element QNCl is

13
increased, and the element QNCl eventually goes to fail because of an overvoltage. When both of the elements QNCl and QNC2 fail, an electric current is carried as a route AA2 as in the lower part in FIG. 6. The electric current 5 is carried along the route from the terminal P16 through the direct current voltage source Ipa, the upper elements QPl, QP2, QPCl, and QPC2, the terminal P12, the lower elements QNCl and QNC2, and the clamp diodes DCNl and DCN2 to the terminal P16. It is possible that a direct current
10 short circuit in this state causes the development of the failures of the elements QPl, QP2, QPCl, QPC2, QNCl, QNC2, DCN2, and DCNl on the route.
In an embodiment of the present invention in order to stop the development of a failure, an overvoltage
15 suppression circuit 112, an overvoltage detection circuit 111, and a signal generator circuit 110 are mounted on the individual gate drivers 110 of the switching elements as illustrated in FIG. 1. Although two series elements QNCl and QNC2 integrally operated are illustrated in FIG. 1,
20 the similar overvoltage suppression circuit 112, the overvoltage detection circuit 111, and the signal generator circuit 110 are also provided on the other elements.
According to the circuit configuration in FIG. 1, the
25 switching pulse signal G3u is given in common to two

14
series elements QNCl and QNC2 integrally operated, and the signal generator circuits 110 of the series elements QNCl and QNC2 give gate currents Igl and Ig2 to gates g of the IGBT elements QNCl and QNC2 in response to the reception 5 of the switching pulse signal G3u.
On the other hand, the IGBT elements QNCl and QNC2 are turned off in response to the application of negative gate currents Igl and Ig2, collector currents Ic carried through collectors c of the IGBT elements QNCl and QNC2
10 are decreased, and a collector voltage is increased. A Zener diode 112a of the overvoltage suppression circuit 112 configured of a series circuit formed of the Zener diode 112a and a resistor 112b regulates a collector voltage when the collector voltage is reached at a
15 predetermined voltage or greater, and clamp currents Igcl and Igc2 are carried. Thus, the clamp currents Igcl and Igc2 are branched to the gate currents Igl' and Ig2' and the gate currents Igl and Ig2, and the gate currents are carried. In the overvoltage detection circuit 111, the
20 potentials of the gate currents Igl and Ig2 are monitored, and an abnormality is detected from overvoltages of the IGBT elements QNCl and QNC2. It is noted that here, the directions of arrows in FIG. 1 are positive for the clamp currents Igcl and Igc2, the gate currents Igl and Ig2, and
25 the gate currents Igl' and Ig2' .

15
It is noted that in the conditions in which an overvoltage is applied across a collector c and an emitter e of the IGBT of the switching element, the voltage across the collector c and the emitter e is sufficiently higher 5 than the voltage across a gate g and the emitter e, it is considered that the voltage across the collector c and the emitter e is nearly equal to the voltage across the collector c and the gate g, and both of the voltages are called a collector voltage.
10 Moreover, it is fine that the Zener diode 112a of the overvoltage suppression circuit 112 in FIG. 1 is a clamping element in a broad sense. In short, it is fine that the Zener diode 112a is one having a function that an electric current is carried when a voltage at a certain
15 threshold or greater is applied. The Zener diode 112a is an example of a clamping element.
FIG. 2 is the electric current waveforms and voltage waveforms of elements when a failure is developed as described above in a previously existing circuit that does
20 not include the overvoltage suppression circuit 112. In FIG. 2, (a) is the collector current Ic, (b) is a collector voltage Vcel, (c) is a collector voltage Vce2, (d) is the clamp current Igcl, (e) is the gate current Igl, (f) is the gate current Igl', (g) is the clamp current
25 Igc2, (h) is the gate current Ig2, (i) is the gate current

16
Ig2', and (j) is a failure detection signal in the order from above.
Moreover, in the time base on the horizontal axis in FIG. 2, time tl is the time at which the conduction of the 5 element QNC2 fails, and time t2 is the time at which the conduction of the element QNCl fails because of the development of a failure. Therefore, in the normal operation state in which no failure occurs in FIG. 2, the waveforms of the elements before time tl are repeatedly
10 generated. In other words, the negative gate currents in (f) and (i) by the switching pulse Glu3 are carried in the state in which the collector current Ic in (a) is carried through the series elements QNCl and QNC2, so that the IGBT elements QNCl and QNC2 are turned off, and the
15 collector current Ic is decreased. It is noted that in this state, Igl (e) = Igl' (f) and Igc2' (h) = Ig2' (i). Moreover, such repeating waveforms are generated in which in association with the turning off of the IGBT elements QNCl and QNC2, the collector voltages in (b) and (c) of
20 the series elements QNCl and QNC2 are raised, the negative gate currents in (f) and (i) are gone, and the collector voltages in (b) and (c) of the series elements QNCl and QNC2 are decreased.
On the other hand, since the conduction of the
25 element QNC2 fails at time tl, the collector voltage Vcel

17
in (b) of the element QNCl is applied to together with a voltage supposed to be applied to the element QNC2 after time tl. The state in which this high voltage is applied is continued, the failure is further developed, the 5 conduction of the element QNCl fails at time t2, and a large electric current is continuously carried as the collector current Ic in (a). It is noted that in the element QNCl after time t2, the collector voltage Vcel in (b) is rapidly decreased. Since this example of the
10 previously existing circuit does not include the
overvoltage detection circuit, failure detection in (j) is not performed.
As illustrated in this example, when the collector current Ic carried through the element QNCl is cut from
15 the conduction state and goes to zero, the collector
voltages Vcel and Vce2 applied to the IGBTs are jumped because of the interconnection inductance of the main circuit as (b) and (c) in FIG. 2. Moreover, when the conduction of the element QNC2 fails at time tl, a voltage
20 supposed to be applied to the element QNC2 is a voltage of zero as (c) in FIG. 2, the voltage applied to the faulty element QNC2 is applied to the element QNCl, and the collector voltage Vcel of the element QNCl is increased as (b) in FIG. 2. As a result, the element QN goes to fail
25 because of an overvoltage at time t2, a direct current

short circuit occurs from the power supply Ipa on the route of the elements QPl, QP2, QPCl, QPC2, QNCl, QNC2, DCN2, and DCNl as (b) in FIG. 2, and secondary damage is extended. 5 FIG. 3 is the operation of a circuit to which the present invention is applied. Items on the vertical axis and the horizontal axis in the case of these waveforms are the same as the items in FIG. 2, and the detailed description of the items (a) to (j) is omitted.
10 In the case of the present invention including the overvoltage suppression circuit 112, when the collector voltages Vcel and Vce2 are reached at high voltages determined at the Zener diode 112a, the clamp currents Igcl and Igc2 are generated, and the collector voltages
15 Vcel and Vce2 are kept and regulated at high voltages determined at the Zener diode 112a. The clamp currents Igcl and Igc2 generated from this result are branched to the gate currents Igl and Ig2 and the gate currents Igl' and Ig2'.
20 In FIG. 3, the gate currents Igl and Ig2 and the gate currents Igl' and Ig2' are illustrated in association with the branching of the clamp currents Igcl and Igc2. In (e) , (f), (h), and (i) in FIG. 3, the waveforms of the gate currents in a period from time tlO to time til are the
25 same as the previously existing waveforms. However, in a

19
period from time til to time tl2 in which the clamp current is branched, the waveforms are the gate current waveforms that the clamp current is added. According to the waveforms, the gate currents Igl and Ig2 are increased 5 on the negative side, and the gate currents Igl' and Ig2' are moved to the zero potential side.
When the circuit in FIG. 1 is in the normal operation state in which no failure occurs, the waveforms of the elements before time tl in FIG. 3 are repeatedly generated
10 as described above. In other words, the negative gate
currents in (f) and (i) caused by the switching pulse Glu3 are carried in the state in which the collector current Ic in (a) is carried through the series elements QNCl and QNC2, so that the collector current Ic is decreased.
15 Moreover, although the collector voltages in (b) and (c) of the series elements QNCl and QNC2 are raised, the values are regulated by the clamp voltage, and the gate currents Igl and Ig2 and the gate currents Igl' and Ig2' are determined by branching the clamp current at this time.
20 After that, such repeating waveforms are generated in which after the gate currents are gone, the collector voltages in (b) and (c) of the series elements QNCl and QNC2 are decreased.
On the other hand, a series of operations of the
25 circuit in FIG. 1 in the case where the conduction of the

20
element QNC2 falls from the normal operation state Is as follows. In FIG. 3, first. In the normal state, the elements QNCl and QNC2 perform normal switching operations, and the collector current Ic carried through the elements
5 QNCl and QNC2 is turned to zero when the collector current Ic Is cut from the conduction state ((a) in FIG. 3). This phenomenon is a phenomenon in the normal switching operation. At this time, the collector voltages Vcel and Vce2 applied to the elements QNCl and QNC2 are jumped
10 because of the interconnection inductance of the main
circuit as in (b) and (c) in FIG. 3. In this case, when the collector voltages Vcel and Vce2 applied to the Zener diode 112a of the overvoltage suppression circuit 112 of the gate driver 110 are reached at a set clamp voltage
15 value Vm or greater, the clamp currents Igcl and Igc2 are carried through the resistors 112b. The clamp currents Igcl and Igc2 are branched, the electric currents Igl' and Ig2' are carried through the gates g of the elements QNCl and QNC2, and the electric currents Igl and Ig2 are
20 carried through the overvoltage detection circuit 111.
As described above, according to the circuit in FIG. 1, the gate currents Igl', Ig2' are supplied as gate charge currents from the overvoltage suppression circuit 112 to the gates g of the elements QNCl and QNC2 to
25 increase the gate voltages, so that the impedances of the

21
elements QNCl and QNC2 are decreased and protected from an overvoltage, and the collector voltages of the element QNCl and QNC2 are balanced.
At this time, the overvoltage detection circuit 111 5 observes the gate currents Igl and Ig2 carried into the overvoltage detection circuit 111, and checks whether an electric current at the clamp detection threshold In or greater is carried for a period of abnormality detection time tf or longer. In the state before time tl, a period
10 tfl, in which the electric current is at the clamp detection threshold In or greater, is generated in a period from time til to time tl2. However, since this phenomenon is an event that periodically occurs in a correct switching operation, it is confirmed whether the
15 value is the reference value tf or less, and it is
determined that an abnormality is not detected in the operation.
On the other hand, continuously, when the conduction of the element QNC2 fails, the voltage supposed to be
20 applied to the element QNC2 is a voltage of zero at time tl as (c) in FIG. 3, a voltage for the element QNC2 is applied to the element QNCl, and the collector voltage Vcel of the element QNCl is increased as (d) in FIG. 3. In this event, similarly to voltage clamping in normal
25 switching, when the value is the set clamp voltage value

22
Vm or greater, the clamp current Igcl is carried through the resistor 112b and then branched, the electric current Igl' is carried through the gate g of the element QNCl, and the electric current Igl is carried through the 5 overvoltage detection circuit 111.
Thus, the current Igl is supplied as a gate charge current to the gate g, so that the impedance of the element QNCl is decreased, and the element QNCl is protected from an overvoltage. Moreover, simultaneously
10 with the protection, the overvoltage detection circuit 111 observes the gate current Igl carried into the overvoltage detection circuit 111, and checks whether the electric current at the clamp detection threshold In or greater is carried for a period of abnormality detection time tf or
15 longer.
In a period tf2 in which the value is the clamp detection threshold In or greater at this time, it is detected that the value is the reference value tf or greater, and a failure is determined. In this connection,
20 since the period tfl is about 5 ]iS, whereas the period tf2 is 15 IJS or greater, these periods can be easily distinguished. Thus, when the gate current is carried for the abnormality detection time tf or longer, the failure detection signal is turned on as (j) in FIG. 3, it is
25 determined that a neighboring element fails, the operation

23
of the power converter is stopped before the occurrence of a direct current short circuit, and the expansion of secondary damage can be suppressed.
It is noted that in order to balance voltage sharing 5 between MOS gate semiconductor devices serially connected in multiple stages in the same switching operation, the number of stages of the clamping elements that carry an electric current when a voltage at a certain threshold or greater is applied is adjusted to the number that a
10 voltage jump is positively suppressed, so that series
voltages of the MOS gate semiconductors can be balanced in the normal switching operation.
Moreover, in FIG. 3, after time tl, a positive gate current igl in (e) is carried caused by the clamp current
15 branched to the gate g. Although this is an electric
current in the conducting direction of the semiconductor device, the constants and the like of the elements of the switching elements are defined as low values in such a manner that the elements are not actually operated at an
20 electric current at this time.
As described above, according to the first embodiment, the collector voltage is individually monitored for plural the series switching elements forming the arms, a period in which the collector voltage is a predetermined value or
25 greater is a predetermined period or greater, so that an

24
abnormality in the switching element is determined.
Second Embodiment
Next, a second embodiment of the present invention 5 will be described. In the first embodiment, the IGBT elements are in a two series configuration for the switching pulses G. In the second embodiment, the IGBT elements are in one series configuration. The basic configuration of a power converter 100b according to the
10 second embodiment will be described with reference to FIG. 7.
In FIG. 7, the power converter 100b is a power converter in one phase extracted from three phases of the power converter (the U phase, the V phase, and the W
15 phase). Since the configurations are the same in the U phase, the V phase, and the W phase, only the configuration in the U phase will be described below. The power converter 100b is configured of plural switching elements connected in series. In the second embodiment of
20 the present invention, the switching elements are
configured of IGBTs, and form a series circuit using IGBTs QP, QPC, QNC, and QN. In the IGBT series circuit, an upper arm is formed of two upper elements QP and QPC, a lower arm is formed two lower elements QNC and QN, and a load 3
25 is connected between a midway point P12 of the upper arm

25
and the lower arm and a ground. Moreover, a diode series circuit formed of clamp diodes DCP and DON is provided between a midway point P13 of these two upper elements QP and QPC and a midway point P14 of these two lower elements 5 QNC and QN.
A voltage E is taken from direct current voltage
sources Ipa and Ina at both ends of the series circuit formed of the IGBTs. A midway point P15 of the diode series circuit and a midway point P16 of the direct
10 current voltage sources are then grounded in common.
The power converter side that is the main body is configured as described above, and a pulse duration modulation circuit 200 on the control side is configured as below. First, four gate amplifiers GAlu, GA2u, GA3u,
15 and GA4u are included in the last stage of the pulse
duration modulation circuit 200 that is a control circuit. In these gate amplifiers, a switching pulse Glu from the gate amplifier GAlu is given to gate drivers 110 of the upper elements QPl and QP2 of the IGBT series circuit, a
20 switching pulse G2u from the gate amplifier GA2u is given to gate drivers 110 of the lower elements QNCl and QNC2 of the IGBT series circuit, a switching pulse G3u from the gate amplifier GA3u is given to gate drivers 110 of the upper elements QPCl and QPC2 of the IGBT series circuit,
25 and a switching pulse G4u from the gate amplifier GA4u is

26
given to gate drivers 110 of the lower elements QNl and QN2 of the IGBT series circuit.
Moreover, the gate amplifiers GAlu and GA2u and the gate amplifiers GA3u and GA4u receive switching pulses 5 from comparators Cmpl and Cmp2, respectively. One of the gate amplifiers GAlu and GA2u and one of the gate amplifiers GA3u and GA4u receive inverted switching pulse signals from inverting circuits Notl and Not2. As a result, when switching pulses are given to the upper elements QPl
10 and QP2, the inverted switching pulses of the switching
pulses are given to the lower elements QNCl and QNC2, and when switching pulses are given to the lower elements QNl and QN2, the inverted switching pulses of the switching pulses are given to the upper elements QPCl and QPC2.
15 It is noted that although the relationship between the switching pulses Glu, G2u, G3u, and G4u and the voltage at the output end of the power converter in the case of the second embodiment is FIG. 5, the description is omitted because the relationship is the same as the
20 first embodiment.
FIG. 8 is a failure mode in the case where the element QNC fails, which is one of the IGBTs of the circuit illustrated in FIG. 7. For an example of a failure mode, when the switching pattern is pattern A in FIG. 5,
25 an electric current is carried as a route BBl in (a) in

27
FIG. 8. When the conduction of the switching element QNC fails in this state, it is likely that a direct current short circuit as a route BB2 in (b) in FIG. 8 occurs, and the elements QP, QPC, QNC, and DON on the route fail. It 5 is noted that since this development of a failure can be similarly occur when switching patterns are patterns B and C in FIG. 5, pattern A will be specifically described in the following description.
Moreover, voltages for four elements QP, QPC, QNC,
10 and QN are applied to the element QN, which is one of the elements connected in series, the voltage is increased, and the element QN soon goes to fail because of an overvoltage. When the element QN fails, the electric current is carried as a route BB3 in (c) in FIG. 8 because
15 of a direct current short circuit, the voltage on the
short circuit route is a voltage twice the voltage in (b) in FIG. 8, and short circuit energy is increased to escalate damage.
In order to stop the development of the failure, in
20 the second embodiment of the present invention, an overvoltage suppression circuit 112, an overvoltage detection circuit 111, and a signal generator circuit 110 are mounted on the gate drivers 110 of the switching elements individually as illustrated in FIG. 8. The
25 circuit configuration in FIG. 8 is basically the same as

2i
the circuit configuration in FIG. 1. The second embodiment is only different from the first embodiment in that the signal generator circuit 110 is individually disposed, and the other configurations and the operations are the same 5 as in FIG. 1.
It is noted that in the conditions in which an overvoltage is applied across the collector and the emitter of the IGBT, the voltage across the collector and the emitter is sufficiently higher than the voltage across
10 the gate and the emitter, and it is considered that the voltage across the collector and the emitter is nearly equal to the voltage across the collector and the gate, so that both of the voltages are called the collector voltage below.
15 FIG. 10 is the electric current waveforms and voltage waveforms of elements when a failure is developed as described above in the case where a previously existing circuit that does not include the overvoltage suppression circuit 112. In FIG. 2, (a) and (b) are the collector
20 currents Ic, (c) is the collector voltage Vcel, (d) is the collector voltage Vce2, (e) is the clamp current Igcl, (f) is the gate current Igl, (g) is the gate current Igl', (h) is the clamp current Igc2, (i) is the gate current Ig2, (j) is the gate current Ig2', and (k) is the failure
25 detection signal in the order from above.

29
Moreover, in the time base on the horizontal axis in FIG. 10, time tl is the time at which the conduction of the element QNC fails, and time t2 is the time at which the conduction of the element QN fails because of the 5 development of a failure. Therefore, in the normal
operation state in which no failure occurs in FIG. 10, the waveforms of the elements before time tl are repeatedly generated. In other words, the negative gate currents in (f) and (g) by the switching pulse Glu3 is carried in the
10 state in which the collector currents Ic in (a) and (b) are carried through the series elements QNC and QN, so that the IGBT element QNC is turned off, and the collector current Ic is decreased. It is noted that in this state, Igl (f) = Igl (g), and Igc2' (i) = Ig2' (j). Furthermore,
15 such a repeating waveform is generated in which in
association with the turning off of the IGBT element QNC, the collector voltage in (c) of the series element QNC is raised, the negative gate currents (f) and (g) are gone, and the collector voltage in (c) of the element QNC is
20 decreased.
On the other hand, since the conduction of the element QNC fails at time tl, the collector voltage Vce2 in (d) of the element QN is applied together with the voltage supposed to be applied to the element QNC after
25 time tl. The state in which this high voltage is applied

30
is continued, the failure is further developed, the conduction of the element QN fails at t2, and a large electric current is continuously carried as the collector current Ic in (a). It is noted that in the element QNC
5 after time t2, the collector voltage Vce2 in (d) is
rapidly decreased. Since this example of the previously
existing circuit does not include the overvoltage detection circuit, failure detection in (k) is not performed.
10 As illustrated in this example, when the collector
current Ic carried through the element QNC is cut from the conduction state and goes to zero, the collector voltage Vcel applied to the IGBT is jumped as (c) in FIG. 10 because of the interconnection inductance of the main
15 circuit. Moreover, when the conduction of the element QNC fails at time tl, the voltage supposed to be applied to the element QNC is a voltage of zero as (c) in FIG. 10, the voltage applied to the faulty element QNC is applied to the element QN, and the collector voltage Vce2 of the
20 element QN is increased as (d) in FIG. 10. As a result, the element QN goes to fail because of an overvoltage at time t2, a direct current short circuit occurs from the power supply Ipa on the route of the elements QP, QPC, QNC, and DCN as (c) in FIG. 10, and secondary damage is
25 extended.

31
Next, FIG. 11 is the operation of a circuit to which the present invention is applied. In FIG. 11, as apparent from the description in FIG. 3, when the electric current Icl carried through the element QNC is cut from the 5 conduction state and goes to zero ((a) in FIG. 11 in the normal switching operation), the collector voltage Vcel applied to the element QNC is jumped as (c) in FIG. 11 because of the interconnection inductance of the main circuit. However, when the collector voltage Vcel applied
10 to the Zener diode 112a of the overvoltage suppression circuit 112 of the gate driver 110 is reached at the set clamp voltage value Vc or greater, the clamp current Igcl is carried through the resistor 112b and then branched, the gate current Igl' ((g) in FIG. 11) is carried through
15 the gate g of the element QNC, and the gate current Igl ((f) in FIG. 11) is carried through the overvoltage detection circuit 111.
As described above, the electric current Igl' is supplied as a gate charge current to the gate g of the
20 element QNC to increase the gate voltage, so that the
impedance is decreased, and the element QNC is protected from an overvoltage. Moreover, the overvoltage detection circuit 111 observes the gate current Igl carried into the overvoltage detection circuit 111, and checks whether the
25 electric current at the clamp detection threshold In or

32
greater is carried for a period of abnormality detection time tf or longer.
When the conduction of the element QNC fails at time tl, the voltage supposed to be applied to the element QNC 5 is a voltage of zero as (c) in FIG. 11, the voltage
applied to the other element is applied to the element QN as described in FIG. 8, and the collector voltage Vce2 of the element QN is increased as (d) in FIG. 11. At this time, when the value is reached at the set clamp voltage
10 value Vc or greater as similar to the voltage clamp in normal switching before conduction failure, the clamp current Igc2 is carried through the resistor 112b, the current is branched, and then the electric current Ig2' is carried into the gate g of the element QN, and the
15 electric current Ig2 is carried into the overvoltage detection circuit 111.
The electric current Ig2' is supplied as a gate charge current to the gate g, so that the impedance of the element QN is decreased, and the element QN is protected
20 from an overvoltage. Moreover, simultaneously with the
protection, the overvoltage detection circuit 111 observes the gate current Ig2 carried into the overvoltage detection circuit 111, and checks whether an electric current of the clamp detection threshold I or greater is
25 carried for a period of abnormality detection time tf or

33
longer. When the gate current is carried for the abnormality detection time tf or longer as (i) in FIG. 11, the failure detection signal is turned on as (k) in FIG. 11, it is determined that a neighboring element fails, the 5 operation of the power converter is stopped, and the expansion of secondary damage can be suppressed.
As described above, according to the second embodiment, the collector voltage is individually monitored for plural the series switching elements forming
10 the arms, it is determined that a period in which the
collector voltage is a predetermined value or greater is a predetermined period or greater, so that an abnormality in the switching element is determined.
As described above, according to the present
15 invention, when a voltage is biased on a neighboring
element after the switching element of the power converter fails and the voltage is increased, the overvoltage is suppressed by the overvoltage suppression circuit, the overvoltage detection circuit detects that the overvoltage
20 is occurring for a predetermined time period or longer, it is determined that the neighboring element fails, the operation of the device is stopped before the occurrence of a direct current short circuit, and the escalation of the secondary damage of the device is suppressed.
25 Here, the overvoltage suppression circuit is

34
configured of a circuit in which clamping elements like a Zener diode, for example, are serially connected, and an electric current is carried when a voltage is applied. The overvoltage suppression circuit is a circuit as described 5 in Japanese Unexamined Patent Application Publication No. 2008-86096 in which the circuit is connected between the collector and the gate of the switching element in parallel with each other, when an overvoltage is applied across the collector and the gate, an electric current is
10 carried through the Zener diode, and the charge current is supplied to the gate of the switching element, so that the impedance of the switching element is decreased, and the switching element is protected from an overvoltage.
Moreover, the overvoltage detection circuit is a
15 circuit that recognizes an electric current carried from the overvoltage suppression circuit to the gate driver when an overvoltage occurs as a signal which is not matched with a command signal carried from the gate driver to the switching element and determines that an
20 overvoltage occurs as described in Japanese Unexamined Patent Application Publication No. 2009-165348.
As described above, according to the present invention, the overvoltage suppression circuit using the method described in Japanese Unexamined Patent Application
25 Publication No. 2008-86096 is combined with the

35
overvoltage detection circuit using the method described in Japanese Unexamined Patent Application Publication No. 2009-165348, and the number of the stages of the clamping elements serially connected of the overvoltage suppression 5 circuit is adjusted, so that an overvoltage can be
suppressed in the normal operation. Moreover, a setting is provided to carry an electric current from the clamping element of the overvoltage suppression circuit for a predetermined time period or longer when a neighboring
10 element fails. After the overvoltage detection circuit detects that the electric current is carried for a predetermined time period or longer, it is determined that the neighboring element fails, and the power converter is stopped. Thus, even though it is not enabled to detect a
15 failure at a faulty element itself, the failure of the element is reliably and quickly detected, and the expansion of secondary damage can be suppressed.
List of Reference Signs
20 Ipa, Ina, Ipb, and Inb Direct current voltage source
P12 Alternating current output end
2f Adder
3 Load
100a U phase of a power converter in two serial
25 connections

36
100b U phase of a power converter in a single serial connection
110 Gate driver
111 Overvoltage detection circuit
5 112 Overvoltage suppression circuit
112a Zener diode
112b Resistor
200 Pulse duration modulation circuit
AAl, AA2, BBl, BB2, and BB3 current conduction route 10 Bl Bias circuit
c Collector of an IGBT
Cmpl and Cmp2 Comparator
CrSl Carrier wave
e Emitter of the IGBT 15 DCPl, DCP2, DCNl, DCN2, DCP, and DCN Clamp diode
E Direct current voltage value
Er Desired direct current voltage value
g Gate of an IGBT
G31 Carrier wave generator 20 Glu to G4u Switching pulse in a U phase
GAlu to GA4u Gate amplifier in the U phase
Ic Collector current
Igl and Ig2 Gate current carried through the
overvoltage detection circuit

Igl' and Ig2' Gate current carried through the gate of the IGBT
Igcl and Igc2 Electric current carried through the overvoltage suppression circuit
In Clamp detection threshold electric current Ml Multiplication circuit
Notl and Not2 NOT circuit
tl Clamping time
t2 Switching element failure time
tf Abnormality detection time threshold in clamping
Vcel and Vce2 Collector voltage
Vc Clamp voltage
Vu U phase inverter output voltage
Vu* U phase alternating voltage command
Vv* V phase alternating voltage command
Vw* W phase alternating voltage command
Vu*P and Vu*N Branched U phase alternating voltage
command
Vv*P and Vv*N Branched V phase alternating voltage
command
Vw*P and Vw*N Branched W phase alternating voltage
command
QPl, QP2, QPCl, QPC2, QNCl, QNC2, QNl, and QN2 IGBT
element
QP, QPC, QNC, and QN IGBT element

WHAT IS CLAIMED IS:
1. A protection device for a power converter in which
an upper arm and a lower arm are formed of a series
circuit of a plurality of switching elements, a ground is
connected from a midway point of the upper arm and the
lower arm through a diode, a ground is connected from a
connecting point of the upper arm and the lower arm
through a load, and DC power supplies are connected to
both ends of the upper arm and the lower arm,
wherein the plurality of the switching elements forming the arms individually include an overvoltage suppression circuit including a clamping element connected between a collector and a gate, a signal generator circuit that applies a gate signal to the gate, and an overvoltage detection circuit disposed in parallel with the signal generator circuit; and
when an overvoltage occurs on the switching element, the overvoltage detection circuit monitors duration of the overvoltage from a clamp current obtained from the overvoltage suppression circuit and detects a failure of the switching element.
2. The protection device for a power converter
according to claim 1,

wherein in the power converter, a plurality of switching elements are individually disposed between the midway point of the upper arm and the lower arm and a terminal on the power supply side or the connecting point of the upper arm and the lower arm, and the plurality of the switching elements are driven by the same switching pulse.
3. The protection device for a power converter
according to claim 1,
wherein the power converter includes a single switching element disposed between the midway point of the upper arm and the lower arm and a terminal on the power supply side or the connecting point of the upper arm and the lower arm.
4. The protection device for a power converter
according to any one of claims 1 to 3,
wherein duration of the overvoltage is set longer than duration of an overvoltage of a collector voltage of the switching element, the overvoltage being produced when a gate signal is applied to the gate.
5. The protection device for a power converter
according to claim 2,

wherein a MOS gate semiconductor device is adopted for switching elements serially connected in multiple stages in the same switching operation; and
in order to balance voltage sharing between the MOS gate semiconductor devices, a number of stages of clamping elements that carry an electric current when a voltage at
a certain threshold or greater is applied is adjusted to a number that a voltage jump is positively suppressed, and series voltages of the MOS gate semiconductors are balanced in normal switching operation.
6. A protection method for a power converter in which an upper arm and a lower arm are formed of a series circuit of MOS gate semiconductors for a plurality of switching elements, a ground is connected from a midway point of the upper arm and the lower arm through a diode, a ground is connected from a connecting point of the upper arm and the lower arm through a load, and DC power supplies are connected to both ends of the upper arm and the lower arm,
the method comprising:
providing a clamping element that carries an electric current when a voltage at a threshold or greater is applied to a first switching element in a failure of a second switching element serially connected to the first

switching element in the same arm,
suppressing an overvoltage of a MOS gate
semiconductor by supplying an electric current carried
from the clamping element to a gate of the MOS gate
semiconductor to decrease impedance; and
detecting a failure of the second switching element
by detecting that the electric current from the clamping
element is carried for a predetermined time period or
longer.
7. The protection method for a power converter
according to claim 6,
wherein when the second switching element fails, an abnormality is detected by counting a time period for a gate current carried from the clamping element caused by an overvoltage applied to the second switching element; and
in normal switching, a number of stages of the clamping elements is determined in a manner that a time period for the gate current carried from the clamping element is decreased and an abnormality is not wrongly detected.
8. A protection method for a power converter
comprising:

forming an upper arm and a lower arm using a series circuit of a plurality of switching elements;
connecting a ground from a midway point of the upper arm and the lower arm through a diode;
connecting a ground from a connecting point of the upper arm and the lower arm through a load; and
connecting DC power supplies to both ends of the upper arm and the lower arm,
wherein when a first switching element fails in the switching elements and a voltage of a second switching element connected in series is increased, an overvoltage of the second switching element is suppressed by an overvoltage suppression circuit; and
a failure of the first switching element is detected at an overvoltage detection circuit by detecting an occurrence of an overvoltage of the second switching element for a predetermined time period or longer.