WE CLAIM:
1. A processor (400) comprising:
a multi-core processor (400) having a single semiconductor die including a plurality of cores (410a-410n), a plurality of integrated voltage regulators (412a-412n) each associated with one of the plurality of cores (410a-410n) and to each provide an independent voltage to at least one of the plurality of cores, and a control logic to receive a performance state change request from an operating system (OS) for dynamic update during OS operation of a voltage/frequency of one or more cores of the plurality of cores, the control logic to determine whether to update a voltage/frequency of a first core (410a) of the plurality of cores (410a-410n) based at least in part on a workload, a thermal design power (TDP) margin and a temperature of a portion of the single semiconductor die in which the first core (410a) is located, and control provision of the voltage/frequency to the first core independently of provision of a voltage/frequency to at least a second core (410b) of the plurality of cores, wherein the control logic is to provide a control signal to each of the plurality of integrated voltage regulators (412a-412n) to enable the corresponding integrated voltage regulator to provide an independent voltage to the corresponding core, and wherein a first voltage is to be coupled to the multi-core processor to provide a first regulated voltage to the plurality of integrated voltage regulators.
2. The processor of claim 1, wherein the control logic includes a power control unit (455) of an uncore (420) portion of the processor.
3. The processor of claim 2, wherein the OS is aware of independent control of voltage/frequency provision to the plurality of cores.
4. The processor of claim 2, wherein the power control unit includes an activity monitor to monitor micro-architectural operation of the plurality of cores and to dynamically select at least one of the plurality of cores for provision of an updated voltage/frequency thereto based on the micro-architectural monitoring, and

independent of an operating system (OS) that provides the performance state change request.
5. A method comprising:
receiving (210) a performance state change request to dynamically adjust a voltage/frequency provided to at least one core of a processor during operation in a power control unit (455) of a processor (400);
selecting at least one core of the processor to adjust the voltage/frequency provided thereto independently of at least one other core of the processor;
sending (250, 280) a control signal for the adjusted voltage to an integrated voltage regulator associated with the selected core to enable the core to operate at the adjusted voltage; and
dynamically controlling an independent voltage/frequency for a first set of cores of the processor including the at least one core, and statically controlling a second set of cores of the processor including the at least one other core to receive a fixed voltage/frequency, wherein the first set of cores are associated with a first operating system and the second set of cores are associated with a second operating system.
6. The method of claim 5, comprising selecting the at least one core to adjust the voltage/frequency provided thereto deterministically and not opportunistically.
7. The method of claim 5, comprising adjusting a first plurality of cores to execute at an increased voltage/frequency independently of a second plurality of cores, so that a thermal design power (TDP) budget for the processor is maintained.
8. The method of claim 5, comprising receiving the performance state
change request from the first operating system, wherein the first operating system
is unaware of an independent voltage control ability of the processor.

9. The method of claim 5, wherein the first operating system is to execute
non-deterministic operations and the second operating system is to execute
deterministic operations.
10. The method of claim 9, wherein the non-deterministic operations
comprise user-level applications and the deterministic operations comprise
management operations.
11. A system (100) comprising:
a processor (110) including a plurality of cores (120a-120n), a plurality of integrated voltage regulators (125a-125n) each to independently provide a voltage to at least one of the plurality of cores, and a power control unit (455) to control the plurality of integrated voltage regulators to dynamically adjust during operating system operation one or more independent voltages provided to at least some of the plurality of cores, based at least in part on a workload, a thermal design power (TDP) of the processor, and a temperature of a portion of a die of the processor in which the at least some cores are located, the processor formed on a single semiconductor die;
an external voltage (160) coupled to the processor (110) to provide a first voltage to the plurality of integrated voltage regulators; and
a dynamic random access memory (DRAM) coupled to the processor.
12. The system of claim 11, wherein the power control unit includes an activity monitor to monitor micro-architectural operation of the plurality of cores and to dynamically select at least one of the plurality of cores for provision of an updated voltage/frequency thereto based on the monitoring.
13. The system of claim 11, wherein the power control unit is to cause dynamic adjustment to a voltage/frequency provided to an uncore logic of the processor to enable power savings, the uncore logic including the power control unit and wherein the voltage and frequency at which the uncore logic operates is not visible to the operating system, and to apply the power savings to cause

dynamic adjustment to a voltage/frequency provided to at least one of the plurality of cores.
14. The system of claim 11, wherein the power control unit includes an activity monitor to monitor micro-architectural operation of the plurality of cores and to dynamically select at least one of the plurality of cores for provision of an updated voltage/frequency thereto, and wherein at least one other core is to be provided a fixed voltage/frequency.
15. The system of claim 14, wherein the power control unit is to predict a usage of the at least one core in a future time period based on information from the activity monitor.
16. A processor (500) comprising:
a plurality of cores formed on a single semiconductor die, each of the plurality of cores including an instruction decoder (505) to decode instructions and at least one execution unit (520) to execute the decoded instructions;
a plurality of voltage regulators (412a-412n) formed on the single semiconductor die and each associated with one of the plurality of cores (410a-410n); and
a power control unit (PCU) (455) to control provision of a voltage/frequency to a first core (410a) of the plurality of cores (410a-410n) independently of provision of a voltage/frequency to at least a second core (410b) of the plurality of cores (410a-410n), wherein the PCU is to receive a performance state change request from an operating system (OS) during OS operation for dynamic update of a voltage/frequency of the first core, determine whether to update the voltage/frequency of the first core based at least in part on a workload, a thermal design power (TDP) margin and a temperature associated with the first core, and responsive to the determination update the voltage/frequency provided to the first core.

17. A non-transitory machine-readable medium having stored thereon
instructions, which if performed by a machine cause the machine to perform a
method comprising:
receiving (210) a performance state change request for a first core of a multicore processor, selecting at least one core of the multicore processor to adjust a voltage/frequency provided thereto independently of at least one other core of the multicore processor, sending (250, 280) a control signal for the adjusted voltage to an integrated voltage regulator associated with the selected core to enable the core to operate at the adjusted voltage; and
dynamically controlling (330) an independent voltage/frequency for a first set of cores of the multicore processor based at least in part on a workload, a thermal design power (TDP) and a temperature of the multicore processor, and controlling a second set of cores of the multicore processor to receive a fixed voltage/frequency, wherein the first set of cores are associated with a first operating system and the second set of cores are associated with a second operating system.
18. A system comprising:
a processor (400) including a plurality of cores (410a-410n), a plurality of voltage regulators (412a-412n) each to independently provide a voltage to at least one of the plurality of cores, and a power control unit (455) to control the plurality of voltage regulators to dynamically adjust during system operation one or more independent voltages to be provided to at least some of the plurality of cores, based at least in part on a workload, a thermal design power (TDP) of the processor, and a temperature of a portion of a die of the processor associated with the at least some cores;
an external voltage regulator (160) coupled to the processor to provide a first voltage to the plurality of voltage regulators; and
a dynamic random access memory (DRAM) (460) coupled to the processor.
19. A processor (400) comprising:

a plurality of cores (410a-410n) formed on a single semiconductor die, each of the plurality of cores including an instruction decoder (505) to decode instructions and at least one execution unit to execute the decoded instructions;
a plurality of voltage regulators (412a-412n) formed on the single semi-conductor die, at least one of the plurality of voltage regulators to provide a voltage to one or more of the plurality of cores (410a-410n); and
a power control unit (PCU) (455) to control provision of a voltage/frequency to a first core of the plurality of cores (410a-410n) independently of provision of a voltage/frequency to at least a second core of the plurality of cores, determine whether to update the voltage/frequency of the first core based at least in part on a workload, a thermal design power (TDP) margin and a temperature associated with the first core, and responsive to the determination update the voltage/frequency provided to the first core.
20. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
receiving (210) a performance state change request for a first core of a multicore processor;
adjusting (330) a voltage/frequency provided to the first core independently of at least one other core of the multicore processor,
sending (350) a control signal for the adjusted voltage to the first core to enable the first core to adjust a received voltage to the adjusted voltage; and
dynamically controlling an independent voltage/frequency for a first set of cores of the multicore processor based at least in part on a workload, a thermal design power (TDP) and a temperature of the multicore processor, controlling a second set of cores of the multicore processor to receive a first fixed voltage/frequency, wherein the first set of cores are associated with a first domain having a first operating system and the second set of cores are associated with a second domain having a second operating system, and controlling an uncore (420) circuit of the multicore processor to receive a second fixed voltage/frequency.

21. A system comprising:
a processor (400) including a plurality of cores (410a-410n), a plurality of integrated voltage regulators (412a-412n) each to independently provide a voltage to at least one of the plurality of cores, and a power control unit (455) to control the plurality of integrated voltage regulators to dynamically adjust during system operation one or more independent voltages to be provided to at least some of the plurality of cores, based at least in part on a workload, a thermal design power (TDP) of the processor, and a temperature of a portion of a die of the processor associated with the at least some cores;
an external voltage regulator (160) coupled to the processor to provide a first voltage to the plurality of integrated voltage regulators; and
a dynamic random access memory (DRAM) (460) coupled to the processor.
22. A processor (500) comprising:
a plurality of cores formed on a semiconductor die, at least one of the plurality of cores including an instruction cache (503), a decoder (505) to decode instructions, at least one execution unit (520) to execute the decoded instructions, one or more register files (530), and at least one core-included cache memory, wherein the at least one of the plurality of cores comprises an out-of-order pipeline (515);
a shared cache memory (550);
an integrated memory controller (136);
at least one fully integrated voltage regulator (125a) formed on the semiconductor die; and
a power controller to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores, wherein the first core and the second core are to execute asymmetric workloads, the power controller to determine whether to update the voltage/frequency of the first core based at least in part on a workload, a thermal design power (TDP) budget and a temperature of the processor, and responsive to the determination to update the voltage/frequency provided to the first core, wherein the power controller is to send a control signal to

the at least one fully integrated voltage regulator (125a) to cause the at least one fully integrated voltage regulator (125a) to provide the updated voltage to the first core.
23. A system comprising:
a processor (500);
a dynamic random access memory (DRAM) coupled to the processor;
a data storage, wherein the processor comprises:
a plurality of cores formed on a semiconductor die, at least one of the plurality of cores including a decoder (505) to decode instructions, at least one execution unit (520) to execute the decoded instructions, and at least one core-included cache memory (550), wherein the at least one of the plurality of cores comprises an out-of-order pipeline (515);
a shared cache memory (550);
an integrated memory controller (136);
at least one fully integrated voltage regulator (125a) formed on the semiconductor die; and
a power controller to control provision of a voltage to a first core of the plurality of cores independently of provision of a voltage to at least a second core of the plurality of cores, wherein the first core and the second core are to execute asymmetric workloads, the power controller to determine whether to update the voltage of the first core based at least in part on a workload, a thermal design power (TDP) budget and a temperature of the processor, and responsive to the determination to update the voltage provided to the first core, wherein the power controller is to send a control signal to the at least one fully integrated voltage regulator (125a) to cause the at least one fully integrated voltage regulator (125a) to provide the updated voltage to the first core.
24. A non-transitory machine-readable medium having stored thereon
instructions, which if performed by a machine cause the machine to perform a
method comprising:

receiving (210), in a power controller of a processor, a request for a performance state change to at least one core of the processor, the processor comprising a plurality of cores formed on a semiconductor die, a shared cache memory, the power controller, a fully integrated voltage regulator (125x) formed on the semiconductor die and an integrated memory controller (136);
determining, in the power controller, whether to update a voltage provided to the at least one core based at least in part on a workload, a thermal design power (TDP) budget and a temperature of the processor; and
responsive to the determining, causing the voltage provided to the at least one core to be updated, including sending from the power controller a control signal to the fully integrated voltage regulator (125x) to cause the fully integrated voltage regulator (125x) to provide the updated voltage to the at least one core while at least one other core of the plurality of cores (120a-120n) is provided with a second voltage, the second voltage different than the voltage provided to the at least one core and the updated voltage provided to the at least one core, the processor configured to enable independent performance states for at least some of the plurality of cores.