Description:RELATED APPLICATION
This patent application is related to India Patent Application No. 9263/DELNP/2011, filed on 25 November 2011, entitled “PROVIDING STATE STORAGE IN A PROCESSOR FOR SYSTEM MANAGEMENT MODE”.
Background
Most computer system processors support a special mode of operation called system management mode (SMM). SMM provides a distinct operating environment that is transparent to operating system (OS) software. This mode is often used by original equipment manufacturers (OEMs) to perform special tasks such as system management, device, power and thermal management. Server-related reliability, availability and serviceability (RAS) functions are usually implemented using SMM. SMM is typically entered by sending a system management interrupt (SMI) message to the processor. Upon acknowledging the SMI, the processor saves the current processor context, also called the Processor Save State, to a portion of system memory that is specifically allocated to SMM, referred to as system management random access memory (SMRAM), and executes SMI handler code contained in SMRAM. When the SMI handler has completed its operations, it executes a special (valid in SMM only) resume instruction, which causes the processor to reload the saved processor context from the SMRAM and resume executing the interrupted task.
In a multiprocessor system, generally a SMI message is broadcasted to all processors. The SMI handler selects one processor, referred to as the SMM monarch, to handle the event. This processor waits until all other processors rendezvous inside SMM before handling the SMI event. Non-monarch processors stay in SMM until the monarch completes the event handling. When the SMM event has been handled, the monarch will signal the other processors to exit SMM. This synchronized entry and exit behavior is implemented to prevent any resource conflicts between the two parallel environments (OS and SMM). That is, if some processors are active in the OS environment and the rest are active in the SMM environment at the same time, it is possible that they may modify a shared resource and thereby interfere with each other’s operations, causing the system to crash. In addition, certain SMM events can only be handled by a specific logical processor or a set of logical processors. A broadcast ensures that this condition is always met, since all logical processors will enter SMI.
Thus, SMI handling in a multiprocessor system is complex and can consume all system resources, preventing the handling of other useful work as while a processor is in SMM, it is not available to the operating system.
Brief Description of the Drawings
FIG. 1 is a block diagram of a processor in accordance with one embodiment of the present invention.
FIG. 2 is a block diagram of a multiprocessor system in accordance with one embodiment of the present invention.
FIG. 3 is a flow diagram of a method in accordance with one embodiment of the present invention.
FIG. 4 is a flow diagram of a method in accordance with another embodiment of the present invention.
Detailed Description
In various embodiments, on-die storage can be used as an alternative to using external physical memory to store the save state of individual threads on SMM entry/exit. In contrast, current systems are dependent on external physical memory for entering and exiting SMM. This SMM dependency on system RAM results in scaling, performance and reliability related limitations in mission critical applications, and can be avoided using an embodiment of the present invention. Note that as used herein, the term “thread” may refer to a hardware thread that includes storage in a processor for the architectural state associated with a process (e.g., a register file and associated configuration and status registers). As used herein, the term “hardware thread” is used synonymously with the term “logical processor.” Each processor core may include multiple logical processors each having a dedicated architectural state storage but which shares other core resources such as front end units, execution units and so forth.
, Claims:1) An apparatus for system management mode comprising:
a processor core to execute instructions and to enter a system management mode (SMM), wherein upon entry to the SMM the processor core is to store an active state present in a state storage of the processor core into a storage unit of the processor core and to set up a SMM execution environment by insertion of values associated with the SMM into the state storage.