Moore's law has continued to be the guiding force for the semiconductor Industry. With Scaling being done in line with this law, the size of the MOS transistor has continuously been decreasing to get better performance. However, short channel effects (SCEs) limit the scaling of the MOSFET device, particularly below the 32 nm technology node. To overcome these short channel effects, the conventional planar MOSFET is being replaced with novel device structures such as DG, Tri-Gate (Fin-FET), and cylindrical gate all around (CGAA) [1, 2, 3]. FinFETs were used for 22 nm technology nodes in 2011 [3]. For scaling below the 10 nm node, CGAA is considered a very promising structure because of its good electrostatic control over channel charge, higher immunity to SCEs, and a larger number of the equivalent number of gates as compared to other structures [4].
A small dimensioned MOSFET requires the use of ultra-steep (abrupt) and ultra-shallow junctions, the fabrication of which poses yet another problem. The Junction less Transistor (JLT) provides a solution to these issues as it has no p-n junction between source-channel and drain-channel region which is in contrast to the conventional inversion mode (JJVI) MOSFET. In a JL MOSFET, source-channel-drain regions are uniformly, heavily doped with the same type of doping. For n-channel MOSFET, doping is N+ - N+ - N+ and for that of p-channel MOSFET it is P+ - P+ - P+. A JL MOSFET has a near-ideal sub-threshold slope (SS) -60 mV/decade. Further, a simplified fabrication process, no requirement of an abrupt junction, steeper sub-threshold slope, and reduced SCEs are the added advantages of a JL device. Similarly, a JL CGAA silicon nanowire (SiNW) MOSFET is considered to be a much better device as compared to bulk MOSFET [5-14].
In a JL MOSFET, the doping type and concentration are uniform in the source, channel, and drain regions and are of the order of 1 x 1019 cm~3, that leads to a high source and drain series resistance. For a good device performance, it is required to reduce this series resistance. A device - junctionless accumulation-mode (JAM) FET was proposed that has a higher doping concentration ~ 1 X 1020 cm~3 in source and drain regions. However, JAMFET requires additional fabrication steps as compared to JLFET, making fabrication more complicated [15-17]. A more advanced structure in form of Si nanotube (SiNT) Field Effect Transistor (FET) with a double surrounding gate (DSG) was suggested by Tekleab et. al [18]. In this DSG structure, a gate is inside the channel region and another gate is outside the channel region. This positioning of gates results in good control of SCEs as compared to CGAA structure [18].

In the present report, the inventors have designed a new device structure by using channel and gate oxide engineering, in which Si channel is replaced with Ino.53Gao.47As - a high electron mobility material and SiC>2 gate oxide with AI2O3 - a material of higher dielectric constant [5-7]. Al203 is selected as the gate dielectric material as it has a good and atomic-level smooth interface with Ino.53Gao.47As and because of its higher dielectric constant as compared to Si02 [19, 20].
In the novel device design the inventors have used Quadruple Metal (QM) gate, in which gate of the Ino.53Gao.47As NT MOSFET is formed by using a combination of four different metals each having a different work function as shown in Figs, la & lb. In this QM gate based approach, metal gates of Nickel (Ni), Molybdenum (Mo), Tungsten (W), and Tantalum (Ta) are used as gates each having length of 1.25 nm These are given codes QM1, QM2, QM3, and QM3 respectively. This sequence also indicates the order of placement of metals from source to drain.
A step potential profile is obtained at the interface of dissimilar metals in the gate, as described by researchers in the case of a dual material gate engineering. In Triple material gate structure there are two step changes in surface potential [21-24].
Since, in the present structure, quadruple metal gate is used, hence there is a three-step change in surface potential, the first change is at the interface of metals QM4 and QM3, the second change is at the interface of QM3 and QM2, and the third change is at the interface of QM2 and QM1. This additional step change provides improved screening of channel region under QM1 from drain potential variation.
Hence QM architecture will result in further reduction of the SCEs and thereby enhancing the gate control over channel charge. This leads to three higher values of electric field being produced across the channel in a QM DSG NT MOSFET. The larger number of peaks in the electric field across the channel means higher acceleration of the carriers (electrons in NMOSFET) at the interface of metals. This in turn leads to improved carrier transport efficiency and causes a higher number of electrons to reach the drain. The gate material with a lower work function near the drain end reduces the peak electric field at the drain end. This

decrease in peak electric field at the drain region can result in an increased average lifetime of the device due to reduced hot-carrier effects (HCEs).
This also reduces drain induced barrier lowering (DIBL) as well as the temperature at the drain end. It leads to a reduction in short channel effects (SCEs) and results in high ON current (I0N)- Any increase in drain voltage is completely absorbed by screen gates QM2, QM3, and QM4. In QM type of gate engineered devices, the junctionless (JL) device has smaller DIBL as compared to the inversion mode (EVI) device.
Studies have been made on the behavior of drain current (/o)of the devices based on this structure and the results are presented for inversion mode (IM), junctionless (JL) devices with various optimizations.
For a reasonable comparison between the inversion mode (EVI) and junctionless (JL) type of Ino.53Gao.47As nanotube (NT) MOSFET devices, n-type doping is optimized in the JL device for two goals (i) doping is done to get the same ION as EVI device and (ii) doping is done to get the same VTH as in IM device. Further, along with these optimizations, we have also used Quadruple Metal (QM) Gate Engineering in the studies.
For this case, two devices - JLION and JL_VTH are investigated with channel region doping of 4.875 x 1019 cm~3 and 4.075 x 1019cm-3 respectively. For EVI types of device - small doping (1 x 1015 cm~3) is used in the channel region.
It is known that the various important performance parameters for a device, such as SS, DIBL, and ION/IOFF ratio depend upon the device structure, channel length, and gate material work function [25-27]. The results obtained in the studies show that for the devices reported in this patent, the inventors have observed a better performance as compared to those reported in the literature.
For all the JL devices of both cases, a near-ideal sub-threshold slope of nearly 60 mV/V is seen as compared to those reported in the literature [28-33]. Hence we can conclude that the JL devices based on the structure reported in figs, la & lb have almost an ideal SS, smaller DIBL, smaller IQFF, and hence higher ION/IOFF ratio as compared to EVI devices.

Channel region in DSG structure reported in this work is not limited to Ino.53Gao.47As, it can be any semiconducting material like Si, Ge, SiGe, InAs, GaAs or any combination thereof. Also gate length can be varied from 2 nm to 10 nm. Similarly AI2O3 gate oxide thickness vary from 0.8 nm to 5 nm and channel radius can also be varied upto 10 nm. Based on the dimensions of the device, there will be change in performance parameters like SS, DIBL, ION/IOFF ratio.
2. Drawing
2.1 Brief description of drawing
Fig. 1 shows DSG NT MOSFET (a) inner and outer gate of quadraple metal based gate structure with edges of Ino.53Gao.47As channel, AI2O3 is used as inner & outer gate oxide (b) complete structure of QM Ino.53Gao.47As NTs device.
Fig. 2 shows channel length cross section view of QM DSG Ino.53Gao.47As NT (a) Inversion Mode and (b) Junctionless device structures.

WE CLAIM:

1. Quadruple Metal gate based double surrounding gate Ino.53Gao.47As nanotube MOSFET device structure.
4. REFERENCESS
[1] U. K. Das, Geert Eneman, Ravi Shankar R. Velampati, Yogesh Singh Chauhan, K. B. Jinesh, and Tarun K. Bhattacharyya," Consideration of UFET Architecture for the 5 nm Node and Beyond Logic Transistor," Journal of the 'Electron Devices Society, 6, pp. 1129-1135, September 2018.
[2] Achinta Baidya, Srimanta Baishya and Trupti Ranjan Lenk, "Impact of thin high-k dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor," Material Science in Semiconductor Processing, vol. 71, pp. 413-420, 2017. [3] Fikru Adamu-Lema, Xingsheng Wang, Salvatore Maria Amoroso, Craig Riddet, Binjie Cheng, Lucian Shifren, Robert Aitken, Saurahb Sinha, Greg Yeric, and Asen Asenov, "Performance and Variability of Doped Multithreshold FinFETs for 10-nm CMOS," IEEE Transactions On Electron Devices, vol. 61, pp. 3372-3378, 2014. [4.] Uttam Kumar Das, M. Garcia Bardon, D. Jang, G. Eneman, P. Schuddinck, D. Yakimets, P. Raghavan, Guido Groeseneken, "Limitations on Lateral Nanowire Scaling Beyond 7 nm Node," IEEE Electron Device Letters, vol. 38, pp. 9-11, 2017. [5] Suchismita Tewari, Abhijit Biswas, and Abhijit Mallik, "Study of InGaAs-Channel MOSFETs for Analog/Mixed-Signal System-on-Chip Applications," IEEE Electron Device Letters, vol. 33, pp. 372-374, March 2012.
[6] Zhengping Jiang, Behtash Behin-Aein, Zoran Krivokapic, Michael Povolotskyi, and Gerhard Klimeck, "Tunneling and Short Channel Effects in Ultrascaled InGaAs Double-Gate MOSFETs," IEEE Transactions On Electron Devices, vol. 62, pp. 525-531, February 2015.
[7] Sanghyeon Kim, Seong Kwang Kim, SangHoon Shin, Jae-Hoon Han, Dae-Myeong Geum, Jae-Phil Shim, Subin Lee, Han Sung Kim, Gunwu Ju, Jin Dong Song, Muhammad A. Alam, and Hyung-jun Kim, "Highly-stable self-aligned Ni-InGaAs and non-self-aligned Mo contact for Monolithic 3D Integration of InGaAs MOSFETs," IEEE Journal of the Electron Devices Society, vol. 7, pp 869 - 877, March 2019. [8] S. Tayal, and A. Nandi, "Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications," Materials Science in Semiconductor Processing, 80, pp. 63-67, 2018.

[9] Oana Moldovan, Francois Lime and Benjamin Iniguez, "A Compact Explicit Model
for Long-Channel Gate-All-Around Junctionless MOSFETs. Part-II: Total Charges and
Intrinsic Capacitance Characteristics," IEEE Transaction on Electron Devices, vol. 61,
pp. 3042-3046, 2014.
[10] Chun-Jung Su, Tzu-I Tsai, Yu-Ling Liou, Zer-Ming Lin, Horng-Chih Lin and Tien-
Sheng Chao, "Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon
Nanowire Channels," IEEE Electron Device Letters, vol. 32, pp. 521-523, 2011.
[11] Shubham Sahay and Mamidala Jagadesh Kumar, "Controlling L-BTBT and Volume
Depletion in Nanowire JLFETs Using Core-Shell Architecture," IEEE Transactions on
Electron Device, vol. 63, pp. 3790-3794, 2016.
[12] Yogesh Pratap, Manoj Kumar, Sneha Kabra, Subhasis Haldar, R. S. Gupta, and
Mridula Gupta, "Analytical modeling of gate-all-around junctionless transistor based
biosensor for detection of neural biomolecule species," Journal of Computational
Electrons, vol.17, pp. 288-296, August 2017.
[13] Shilpi Guin, Monali Sil, and Abhijit Malik, "Comparison of Logic Performance of CMOS Circuits Implemented with Junctionless and Inversion-Mode FinFETs," IEEE Transaction on Electron Devices, vol. 64, pp. 953-959, 2017.
[14] F. Lime, O. Moldovan, and B. Iniguez, "A Compact Explicit Model for Long-Channel Gate-All-Around Junctionless MOSFETs. Part I: DC Characteristics," IEEE Transactions on Electron Devices, 61, pp. 3036-3041, 2014
[15] S. Sahay and M. J. Kumar, "Spacer Design Guidelines For Nanowire Fets From Gate-Induced Drain Leakage Perspective," IEEE Transactions On Electron Devices, 64, pp. 3007-3015, July 2017.
[16] S. Sahay and M. J. Kumar, "Symmetric Operation in an Extended Back Gate JLFET for Scaling to the 5-nm Regime Considering Quantum Confinements," IEEE Transaction on Electronic Devices, 64, pp. 21-27, 2017.
[17] D. Moon, S. J. Choi, J. P. Duarte and Y. K. Choi, "Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistor Built on a Bulk Substrate," IEEE Transaction Electron Devices, 60, pp. 1355-1360, 2013.
[18] D. Tekleab, "Device Performance of silicon nanotube MOSFETS field effect transistor," IEEE Electron Device Letter, 35, pp. 506-508, 2014.

[19] H. Wong, H. Iwai, "On the scaling issues and high-k dielectric replacement of ultrathin gate dielectrics for nanoscale MOS transistors," Microelectronic Engineering, 83, pp. 1867-1904,2006.
[20] Masafumi Yokoyama, Sanghyeon Kim, Rui Zhang, Noriyuki Taoka, Yuji Urabe, Tatsuro Maeda, Hideki Takagi, Tetsuji Yasuda, Hisashi Yamada, Osamu Ichikawa, Noboru Fukuhara, Masahiko Hata, Masakazu Sugiyama, Yoshiaki Nakano, Mitsuru Takenaka, and Shinichi Takagi, "III-V/Ge High Mobility Channel Integration of InGaAs n-Channel and Ge p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Self-Aligned Ni-Based Metal Source/Drain Using Direct Wafer Bonding," Applied Physics Express, vol. 5, pp. 076501-3, 2012.
[21] R. K. Sharma, R. Gupta, M. Gupta, and R. S. Gupta, "Dual Material Double-Gate SOI n-MOSFET: Gate Misalignment Analysis," IEEE Transactions On Electron Devices, 56, pp. 1284-1291, 2009.
[22] P. Kasturi, M. Saxena, M. Gupta and R. S. Gupta, "Dual Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance— Part I: Impact of Gate Metal Workfunction Engineering" IEEE Transactions on Electron Devices, 55, pp. 372-381, 2008
[23] S. Rewari, V. Nath, S. Haldar, S. S. Deswal and R. S. Gupta, "Novel design to improve band to band tunnelling and gate induced drain leakages (GIDL) in cylindrical gate all around (GAA) MOSFET," Springer, Microsystem Technology, 25, pp. 1537-1546, 2017 [24] R. K. Baruah, and R. P. Paily, "A Dual-Material Gate Junctionless Transistor With High-k Spacer for Enhanced Analog Performance," IEEE Transactions On Electron Devices, 61, pp. 123-128,2014.
[25] A. Kundu, A. Dasgupta, R. Das, S. Chakraborty, A. Dutta and C. K. Sarkar, "Influence of Underlap on Gate Stack DG-MOSFET for Analytical Study of Analog/RF Performance," Superlattices andMicrostructures, 94, pp. 60-73, 2016..
[26] B. Jena, K. P. Pradhan , Prasanna Kumar Sahu, Sidharth Dash, Guru Prasad Mishra, Sushanta Kumar Mohapatra, "Investigation On Cylindrical Gate All Around (GAA) To Nanowire MOSFET For Circuit Application," Electronics and Energetics, 28, pp. 637 - 643, 2015
[27] B Jena, K. P. Pradhan, D. Dash, G. P. Mishra, P. K. Sahu and S. K. Mohapatra, "Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at

subthreshold regime," Advances in Natural Sciences: Nanoscience and Nanotechnology, 6, pp. 035010,2015.
[28] Sanjay, B. Prasad and A. Vohra, "Dual Material Gate Engineering to Reduce DIBL in Cylindrical GateAll Around Si Nanowire MOSFET for 7-nm Gate Length," Semiconductors, 54, pp. 1490-1495, October 2020.
[29]. D. Nagy, G. Indalecio, A. J. G. Loureiro, M. A. Elmessary, K. Kalna, and N. Seoane, "FinFET versus Gate-All-Around Nanowire FET: Performance, Scaling and Variability," IEEE Journal of the Electron Devices Society, 6, pp.332-340, 2018. [30] P. Zheng, Y. B. Liao, N. Damrongplasit, M. H. Chiang, and T. J. K. Liu, "Variation-Aware Comparative Study of 10-nm GAA Versus FinFET 6-T SRAM Performance and Yield," IEEE Transactions on Electron Devices, 61, pp. 3949 - 3954, December 2014. [31] Yi-Bo Liao, Meng-Hsueh Chiang, Nattapol Damrongplasit, Wei-Chou Hsu, and Tsu-Jae King Liu, "Design of Gate-All-Around Silicon MOSFETs for 6-T SRAM Area Efficiency and Yield," IEEE Transactions on Electron Devices, vol. 61, pp. 2371 - 2377, July 2014.
[32] Pedram Razavi and Giorgos Fagas, "Electrical performance of III-V gate-all-around nanowire transistors," Applied Physics Letters, vol. 103, pp. 063506, 2013. [33] JP Colinge, A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi, "Junctionless Nanowire Transistor (JNT): Properties and Design Guidelines," Solid State Electronics, vol. 65, pp. 33-37, 2011.