RAPID PARTIAL CONFIGURATION OF RECONFIGURABLE DEVICES
Field of the Invention
The present invention relates to a method and system for enabling rapid partial configuration
of reconfigurable devices.
Background Of The Invention
An FPGA typically includes configuration memory cells, configuration control elements and a matrix of logic blocks and I/O blocks.
Fig 2 of the accompanying drawings shows the flow diagram for the partial configuration as
described in US patent no. 5,781,756. It includes the following steps:
After the start of frame loading, it checks the end of the bit stream (2.1), If it is not the end of bit stream, then it retrieves the packet from the bit stream (2.2), checks whether it is a skip command or write command (2.3). If skip command it just increases the address of the memory latch column, and retrieve the next frame (2.6). And if it is write command, it stores the bit stream in a data register (2.4), strobe the Address register to load the data into memory cells (2.5) and then increment the address (2.6). This process goes on until the end of the bit stream.
Problem with this approach is that if we need to load only few frames, even then we need to load skip or write commands for all the frames. In this case there will be many skip commands. Again if most of the frames are to be loaded again, then there will be write command or skip command for all the frames. In this case there will be more write command. It will cause the large configuration time.
The object and summary of the invention
The object of this invention is to obviate the above drawbacks by enabling rapid partial configuration of reconfigurable devices.
To achieve the above objective this invention provides a system for enabling rapid partial
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configuration of reconfigurable devices comprising:
configuration definition means for defining the partial configuration requirements, containing at least one set of the following:
• starting address of configuration data for said partial reconfiguration,
• data size for specifying the number of contiguous locations to be
reconfigured,
• desired configuration data corresponding to said contiguous locations,
configuration loading means for loading the configuration data according to
said partial configuration requirements,
The said configuration definition means is a data frame and said starting address, said data size and said desired configuration data are elements of said data frame.
The said configuration means comprising:
an address counter means for storing said starting address of configuration
data,
index counter means for storing said data size,
configuring means for loading configuration data according to said partial
configuration data,
the arrangement being such that after loading each configuration data said address counter means is incremented, while said index counter means is decremented, said sequence continuing until said index counter value reaches zero.
The said data frame is stored in a frame register while said addres is stored in an address counter connected to the input of a decoder which controls a horizontal latch array and said configuration data is loaded into the selected latch column.
The said starting address of said configuration means corresponds to the address of the initial configuration latch column and said data size of said configuration means corresponds to number of contiguous latch columns.
The said address counter means stores a starting latch column address and said index counter
i means stores the number of contiguous latch columns.
The above system includes:
a controller to control the loading of the data into said index counter and
address counter,
an output of address counter is connected to a decoder circuit,
said decoder circuit output enables the loading of column latch data into a
selected configuration memory column.
The present invention further provides a method for enabling rapid partial configuration of reconfigurable devices comprising the steps of:
defining the partial configuration requirements in terms of at least one set of
the following:
• starting address of configuration data for said partial reconfiguration,
• data size for specifying the number of contiguous locations to be
reconfigured,
• desired configuration data corresponding to said contiguous locations,
and
performing the configuration according to said partial configuration requirements.
The said partial configuration requirements are defined as a data frame and said starring address, said data size and said desired configuration data are fields of said data frame.
The said configuration is performed by:
storing said starting address of configuration data in an address counter, storing said data size in an index counter,
storing said configuration data in the configuration memory of said configurable device at the stored address,
incrementing said address counter and decrementing said index counter storing each configuration data element, said sequence continuing until said index counter value reaches zero.
The said starting address of said configuration means corresponds to the address of the initial configuration latch column and said data size of said configuration means corresponds to the number of contiguous latch columns.
The said address counter stores a starting latch column address and said data size corresponds to the number of contiguous latch columns.
Brief description of the drawings:
Fig 1 shows the configuration Latch Matrix with frame register and Horizontal Latch Array.
Fig 2 shows the prior art for partial reconfiguration.
Fig 3 shows the block diagram of the partial reconfiguration of reconfigurable devices according to this invention.
Fig 4 shows the connectivity between different blocks ofjpartial reconfiguration for reconfigurable devices, according to this invention.
Fig 5 shows the Controller output uring partial configuration.
Fig 6 shows the flow diagram for the normal configuration.
Fig 7 shows the flow diagram for the partial configuration.
Fig 8(a) shows the waveform for partial configuration at the start of the configuration.
Fig 8(b) shows the waveform for partial configuration when Index counter value goes to 0.
DETAILED DESCRIPTION OF THE INVENTION
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Fig 1 shows the Configuration Latch matrix. Configuration frame is loaded into the frame register 110. Circuitry 100 is the Horizontal Latch Array. Outputs of the Horizontal Latch Array 101 and 102 provides the write enable signals to the latch column. 101 is connected to the latch column 131 and 102 is connected to the latch column 132.
When the write enable signal goes high data present on data line 111 is loaded into the corresponding latch column. If write enable 101 is high then data is loaded into the Latch column 131 and if 102 is high then data is loaded into the latch column 132.
Figure 3 shows the block diagram of the present invention. Address Counter 300 is used to store the address of the frame.
Index Counter 310 is used to store number of frames to be loaded in continuation during the partial configuration. During normal configuration it remains idle. Controller 320 is used to control the loading of the data into the Index Counter and Address Counter. Output of the address counter goes into the Decoder Circuit 200. Decoder decode the address represented by address counter and only one output of the decoder goes high. Output of the decoder goes into the Horizontal latch array 100. It checks the decoder value only after the complete frame is loaded into the frame register.
During the first time of configuration or full configuration, the configuration is done as prior normal operation. After loading the pre- configuration data, frame data is shifted into the frame register. Once the complete frame is loaded, Horizontal latch takes the decoder output and the frame is loaded in a particular column of latch. Counter value is then incremented and the next frame is loaded into the address represented by the counter value. Referring to figure 3 during the normal operation counter 300 works as a simple up-counter and the frames are loaded one by one. Index counter 310 remains idle.
During the partial configuration, after the pre-configuration frame is loaded, next data is loaded into the index counter 310 and then to address counter 300. The value of index counter 310 shows the number of frames in continuation and the value of address counter
300 shows the starting frame address. Decoder 200 decode this address and the particular
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output of the decoder goes high. But the output of the Horizontal latches 100 will not go high until the complete frame is loaded into the frame register. Now the next data, which are the frame data are shifted into the frame register. Once complete frame is loaded, Horizontal latch takes the decoder output and the frame is loaded in that particular column of latch whose address is represented by the address counter. Now the value of address counter 300 is incremented and the index counter 310 is decremented. And the next frame is loaded into this new address. Address counter 300 is again incremented and Index counter 310 decremented after the frame is loaded. When Index counter value goes to 0, it means that all the frames which were in continuation has been loaded. It trigs the controller circuit which enable to load new Index Counter and address counter value. Now the next coming frames are loaded starting from this new address. When configuration is completed, start up sequence starts and the device comes into the operational state.
Fig.4 is showing the connectivity between different blocks. The Comparator circuit generates a high pulse on output TRIG if index counter value is 0 or STARTTRIG goes high in case of N/P signal is 0. N/P signal remain high in case of Normal configuration and 0 in case of partial configuration. There is no strict requirement of the N/P signal to remain 0 in case of partial configuration and 1 in case of Normal configuration. It will change only the comparator design. Again there is no strict requirement of the TRIG signal to go high if index counter value is 0 or STARTTRIG goes high in case of N/P signal is 0. It also can go low, but in this case CONTROLLER will be activated on TRIG low not on TRIG high.
During normal configuration (Full Configuration) signal N/P remains high. In this case the Output of the controller ENB_INDEX remain 0 which disable the index counter and index counter remain in idle state. ENB_CNTR remains high which makes the Add. counter to work as a UP-Counter. Output of comparator circuit TRIG remain 0. It causes the CTRL, LD_CNTR and LDJNDEX signal to remains low.
CLK circuit select the clock for the Add counter and index counter. When CTRL signal is low FR_LOAD clock is selected otherwise configuration clock CLKN is selected. After one
frame is loaded in the Configuration latches, FR Load clock causes the Add. counter to
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increment it's value and Index counter to decrement it's value when selected.
Before proceeding to the partial configuration operation in fig.4, lets see the Controller outputs from fig5. Controller check the signal TRIG at the negedge of clock. If it is high, it generates the signal LDJNDEX, LD CTR and CTRL signal as shown. LD_CTR is the load signal to the address counter and LDJNDEX is load signal to the Index Counter. In this particular embodiment, Index and Address counters are assumed to be 16 bit and data is coming in byte. So two clock cycle will be required to load the Index Counter and two clock cycle for address counter. CTRL signal remains high during the loading of the data. When CTRL signal is high, ENBJNDEX and ENB_CNTR signal remains low, which disables the Index counter and address from decrementing or incrementing their value during the loading of the data.
Coming back to the fig4, in Partial configuration N/P signal remains 0. If either the STARTTRIG goes high or Index Counter value goes to 0, TRIG goes high. STARTTRIG is used for loading the INDEX Counter and Address Counter first time after pre- configuration frame has been loaded. It is internally generated signal after the pre-configuration frame. As the TRIG goes high then at negative edge of the clock CTRL and LD_INDEX signal goes high. CTRL signal remains high during the loading of the data. It disables the Index counter and address from decrementing or incrementing their value during the loading of the data. It also select the configuration clock CLKN during the loading of the frame. After the CTRL goes high, then at next two posedge of CLKN data coming from DIN is loaded into the Index Counter and then at next two posedge of CLKN it is loaded into the Address Counter. As the data is loaded into the Index Counter TRIG goes low.
After the data is loaded into the Index counter and Address Counter, then at next negedge of CLKN, CTRL goes low, Now clock FR_LOAD is selected by CLK circuit for Index Counter and Address Counter.
Fig. 6 shows the flow of frame loading in the Normal (Full) configuration mode. After loading the Pre-configuration frame, configuration data is loaded into the frame register. When
complete frame is loaded, It is shifted into the configuration latches. Now it checks whether
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all the frame has been loaded or not. If all the frames has been loaded (Memory Full) then it invokes the start- up, otherwise, frame address is incremented, new frame is loaded into the frame register and this process goes on until all the frames has been loaded.
Fig.7 shows the flow of frame loading in the partial configuration mode. After loading the Pre-configuration frame, it loads the number of frames in continuation in Index counter, then it loads the starting frame address in the Address Counter. After that configuration data is loaded into the frame register. When complete frame is loaded, It is shifted into the configuration latches. Now Address Counter value is incremented (Frame address value) and the index counter value is decremented. After this Index Counter value is checked, If it is not equal to 0, then new frame is loaded in the frame register and shifted to the configuration latches. Again Address Counter value is incremented and the index counter value is decremented. This process goes on until the Index counter value is equal to 0. When Index Counter value goes to 0, it checks whether all the frame has been loaded or not. If all the frames has been loaded (Configuration is complete) then it invokes the start-up, otherwise new index counter value new address counter (frame address) value is loaded. Index counter value represent the number of frames in continuation with this new Frame address value. Now the next frame is loaded and shifted into the configuration latch column whose address is decoded by the address counter value. Again address counter value is incremented and index counter value is decremented. This process goes on until the complete configuration is completed.
FigSa and figSb shows the waveforms for the partial configuration. FigSa shows the waveform at the start of the configuration when STARTRIG comes after the loading of the pre-configuration frame. Initially after reset value of index counter if all 1 and of address counter all O's. After STARTRIG goes high then at next negedge of the clock (CLKN), LD INDEX and CTRL signal goes high. WhenCTRL signal is high, CLKN is selected as the clock of the Index Counter and address counter, otherwise FR_LOAD is selected. At next two posedge of the CLKN, data is loaded into the Index counter. DIN is loaded into the LSB byte of the Index Counter and LSB byte is shifted into the MSB byte of the Index counter. Suppose we want to load 0014h in the Index Counter then at first posedge of CLKN DIN
value will be OOh and at next posedge DIN value will be 14h. Now at next negedge of the
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CLKN, LD_CTR goes high and LDJNDEX goes low. Then at next two posedge of the CLKN, data is loaded into the Address Counter. Data is loaded into the Address counter from DIN in the same manner as in the INDEX counter. Suppose we want to load 0122h in the address counter as the starting address, then at first posedge of CLKN DIN value will be 01 h and at next posedge, DIN value will be 22h. Now at next negedge of the CLKN, LD_CTR and CTRL will go low. Now FR_LOAD is selected as the clock for the Index Counter and address counter. When the posedge of the FR_LOAD come (after one complete frame is loaded into the frame register and shifted into the Configuration Latch Column) Index Counter value is decremented and the Address Counter value is incremented.
Fig8(b) shows the waveform for partial configuration when at the posedge of the FR_LOAD Index counter value goes to 0 (here we assume that posedge of FR_LOAD is in sync with posedge of CLKN). As the Index counter values goes to all O's TRIG goes high and at next negedge of the clock CLKN, CTRL and LD_INDEX goes high and again new Index counter and Address Counter value is loaded as in the previous case (fig 8a). This time TRIG goes low as the Index_Counter value changes from all O's to any other new value. Since atleast one frame will be loaded starring from the new address which will be loaded in the Address Counter, the minimum value which will be loaded in the Index Counter will be OOOlh.
In this particular case output of the Controller 320 is as shown in the fig5. But in general case the output LD_INDEX will remain high for the clock pulse taken by Index Counter 310 for loading the new data and LD CTR will remain high for the clock pulse taken by Address Counter 300 for loading the new data. And output CTRL will remain high through out the loading of the Address Counter and Index Counter.

CLAIMS:
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1. The system for enabling rapid partial configuration of reconfigurable devices
comprising:
configuration definition means for defining the partial configuration requirements, containing at least one set of the following:
• starting address of configuration data for said partial reconfiguration,
• data size for specifying the number of contiguous locations to be
reconfigured,
• desired configuration data corresponding to said contiguous locations,
configuration loading means for loading the configuration data according to
said partial configuration requirements,
2. A system as claimed in claim 1 wherein said configuration definition means is a data
frame and said starting address, said data size and said desired configuration data are
elements of said data frame.
3. A system as claimed in claim 1 wherein said configuration means comprising:
an address counter means for storing said starting address of configuration
data,
index counter means for storing said data size,
configuring means for loading configuration data according to said partial
configuration data,
the arrangement being such that after loading each configuration data said address counter means is incremented, while said index counter means is decremented, said sequence continuing until said index counter value reaches zero.
4. A system as claimed in claim 2 wherein said data frame is stored in a frame register
while said addres is stored in an address counter connected to the input of a decoder
which controls a hotizontal latch array and said configuration data is loaded into the
selected latch column.
5. A system as claimed in claim 1 wherein said starting address of said configuration
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means corresponds to the address of the initial configuration latch column and said data size of said configuration means corresponds to number of contiguous latch columns.
6. A system as claimed in claim 3 wherein said address counter means stores a starting
latch column address and said index counter means stores the number of contiguous
latch columns.
7. A system as claimed in claim 6 including:
a controller to control the loading of the data into said index counter and
address counter,
an output of address counter is connected to a decoder circuit,
said decoder circuit output enables the loading of column latch data into a
selected configuration memory column.
8. A method for enabling rapid partial configuration of reconfigurable devices
comprising the steps of:
defining the partial configuration requirements in terms of at least one set of the following:
• starting address of configuration data for said partial reconfiguration,
• data size for specifying the number of contiguous locations to be
reconfigured,
• desired configuration data corresponding to said contiguous locations,
and
performing the configuration according to said partial configuration requirements.
9. A method as claimed in claim 8 wherein said partial configuration requirements are
defined as a data frame and said starting address, said data size and said desired
configuration data are fields of said data frame.
10. A method as claimed in claim 8 wherein said configuration is performed by:
storing said starting address of configuration data in an address counter I
storing said data size in an index counter,
storing said configuration data in the configuration memory of said
configurable device at the stored address,
incrementing said address counter and decrementing said index counter
storing each configuration data element, said sequence continuing until said
index counter value reaches zero.
11. A method as claimed in claim 8 wherein said starting address of said configuration
means corresponds to the address of the initial configuration latch column and said
data size of said configuration means corresponds to the number of contiguous latch
columns.
12. A method as claimed in claim 10 wherein said address counter stores a starting latch
column address and said data size corresponds to the number of contiguous latch
columns.
13. The system for enabling rapid partial configuration of
reconflgurable devices substantially as herein described with
reference to the accompanying drawings.
14. A method for enabling rapid partial configuration of
reconflgurable devices substantially as herein described with
reference to the accompanying drawings.