TECHNICAL FIELD
The present disclosure relates to the field of Radar technology. More particularly, the present disclosure relates to a reconfigurable digital beam former apparatus with multi-channel optical backplane connectivity for active phase array Radar applications.
BACKGROUND
Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
Phased array antennas are known for their capability to steer the beam pattern electronically in an effective manner achieving minimal side lobe levels and narrow beam widths. Specifications of narrow beam width, considerable scanning range with high range resolution requires large number of antenna elements in the array. Use of more number of analog components results in increase in weight, power consumption and overall cost of maintenance. In addition, variations in device characteristics with time, temperature and environmental changes are more significant in analog components.
The United States Patent Document Number US6882311B2 discloses a receiver for a digital beamforming radar system, which includes a plurality of antenna elements, low-noise block converters, one or more analog-to-digital converters, and a processor. The antenna elements receive a radar signal and output a received signal. The low-noise block converters are modified commercially available components used in satellite television systems, respond to the received signal from a corresponding antenna element, and output an intermediate frequency signal. The low-noise block converters include at least one amplifier, a mixer, and a local oscillator input. The local oscillator input enables an external local oscillator signal to be inputted to the mixer. The analog-to-digital converters are responsive to the intermediate frequency signal of a corresponding low-noise block converter. The processor is responsive to the digital signals output by the analog-to-digital converters.
The cited document utilizes Commercial off the Shelf (COTS) Satellite TV based low noise receiver fine-tuned for RF down conversion to IF in this application. 8 COTS

Quad DSP Cards are used for IF digital down conversion to base band. Overall a total of 64
elements used for receive beam forming.
[0006] Another United Patent Document Number US6600446B2 discloses a
cascadable beamformer with the capability to cooperate with one or more cascadable
beamformers to build a customized beamforming apparatus. The architecture supports a
cascadable beamformer with a covariance estimate logic that supports cascading multiple
devices together to support different numbers of input channels, a weighted sum logic that
supports cascading multiple devices together to support different numbers of input channels,
and a weighted sum logic that supports cascading multiple devices together to support different
numbers of output beam.
[0007] The use of a greater number of components and cascaded arrangement of
beamformer in the above cited prior art document results in increase in size, weight, power
consumption and overall cost of maintenance of the apparatus.
[0008] Further, the use of multi-channel plug-and-play optical transceivers available in
being used in prior arts, require bigger foot prints on the PCB and accommodating multiple
fibre channels within standard form factor PCB is very challenging. In addition, the complexity
of PCB routing with multiple high-speed transceiver lanes routed on PCB substrate to the
processing chipset will result in signal integrity issues which is very critical.
[0009] Therefore, there is a need in the art for a compact, low powered reconfigurable
digital beam former apparatus with multi-channel optical backplane connectivity for active
phase array Radar applications.
OBJECTS OF THE PRESENT DISCLOSURE
[0010] Some of the objects of the present disclosure, which at least one embodiment
herein satisfies are as listed herein below.
[0011] It is an object of the present disclosure to provide re-configurable hardware
platforms resulting in compact, low cost and agile Radar processing hardware.
[0012] It is an object of the present disclosure to provide a re-configurable digital beam
former apparatus with multi-channel optical backplane connectivity.
[0013] It is an object of the present disclosure to provide a hardware scheme for digital
beam former for phased array radar receiver application, which can be used in fully scalable
antenna architecture with multiple group receivers.

[0014] It is an object of the present disclosure to provide a re-configurable hardware
having abundant computational resources for DDC, complex weighting multiplication and summation stages for forming multiple target beams.
[0015] It is an object of the present disclosure to reduce signal routing complexity of
the PCB of the former apparatus, thereby improving the signal integrity to achieve lane rates of multi-channel optical links.
SUMMARY
[0016] The present disclosure relates to the field of Radar technology. More
particularly, the present disclosure relates to a reconfigurable digital beam former apparatus
with multi-channel optical backplane connectivity for active phase array Radar applications.
[0017] An aspect of the present disclosure pertains to a reconfigurable digital beam
former (DBF) apparatus with multi-channel optical backplane connectivity, the apparatus
comprising: one or more digital beam former modules adapted to be operatively coupled to one
or more group receivers associated with sub-arrays of a phased array antenna, wherein each of
the one or more beam former modules may comprise: at least one transceiver configured to
receive a first set of signals from the one or more group receivers; and a processing unit
operatively coupled to the at least one transceiver, and which may be configured to: receive the
first set of signals from the at least one transceiver; de-multiplex the first set of signals to
generate a set of serial data; perform complex weighting and summation on the generated set
of serial data, based on a predefined summation coefficient, wherein the processing unit may
be configured to generate a set of output signals corresponding to a digital beam formed, in
response to the complex weighting and summation of the generated set of serial data.
[0018] In an aspect, the processing unit may comprise one or more serializer and
deserializer (SerDes) modules which may be configured to facilitate communication of the one
or more beam former modules with each other, and the one or more group receivers.
[0019] In an aspect, the apparatus may comprise a signal processor operatively coupled
to the one or more beam former modules through the one or more SerDes modules and the at
least one transceiver.
[0020] In an aspect, the signal processor may be configured to receive and process the
set of output signals to extract as set of target data to enable detection of a target.
[0021] In an aspect, the one or more beam former modules may be configured on a
printed circuit board (PCB), and wherein the one or more beam former modules may be
positioned in a stacked configuration on the PCB using a multi lane serial back plane interface.

[0022] In an aspect, the apparatus may comprise a set of front panel facia connectors
being configured on the PCB, and which may be configured to facilitate operative coupling of
the one or more group receivers to the at least one transceiver of the apparatus.
[0023] In an aspect, the at least one transceiver may be connected to any of the set of
front panel facia connectors and the multi lane serial back plane interface using one or more
fly-over cables.
[0024] In an aspect, the processing unit may be configured with a data transfer protocol
comprising any or a combination of serial front panel data port (sFPDP), serial rapid input
output (SRIO), and peripheral component interconnect express (PCIe).
[0025] In an aspect, the at least one transceiver may be a multi-channel optical
transceiver.
[0026] In an aspect, the first set of signals received may be multiplexed digitized down
converted signals generated by the one or more group receivers based on a set of incoming
signals sensed by the antenna.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The accompanying drawings are included to provide a further understanding of
the present disclosure, and are incorporated in and constitute a part of this specification. The
drawings illustrate exemplary embodiments of the present disclosure and, together with the
description, serve to explain the principles of the present disclosure.
[0028] The diagrams are for illustration only, which thus is not a limitation of the
present disclosure, and wherein:
[0029] FIG. 1 illustrates a single P-channel group receiver interfaced to array elements
enclosed in LRU, in accordance with an exemplary embodiment of the present disclosure.
[0030] FIG. 2 illustrates the proposed hardware of the reconfigurable digital beam
former (DBF) apparatus based on high speed SerDes I/O supporting multi-channel optical
Transceivers, in accordance with an exemplary embodiment of the present disclosure.
[0031] FIG. 3 illustrates an exemplary modular DBF system hardware based on serial
back plane interface, in accordance with an exemplary embodiment of the present disclosure.
[0032] FIG. 4 illustrates an exemplary connectivity method using multiple channel
flyover optical transceivers and serial backplane for maximum I/O bandwidth, in accordance
with an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION
[0033] The following is a detailed description of embodiments of the disclosure
depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0034] Various terms as used herein are shown below. To the extent a term used in a
claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0035] In some embodiments, the numerical parameters set forth in the written
description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0036] As used in the description herein and throughout the claims that follow, the
meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0037] The recitation of ranges of values herein is merely intended to serve as a
shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the

specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0038] Groupings of alternative elements or embodiments of the invention disclosed
herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.
[0039] The present disclosure relates to the field of Radar Systems. More particularly,
the present disclosure relates to a reconfigurable digital beam former apparatus with multi¬
channel optical backplane connectivity for active phase array Radar applications.
[0040] According to an aspect, the present disclosure elaborates upon a reconfigurable
digital beam former (DBF) apparatus with multi-channel optical backplane connectivity, the apparatus including: one or more digital beam former modules adapted to be operatively coupled to one or more group receivers associated with sub-arrays of a phased array antenna, wherein each of the one or more beam former modules can include: at least one transceiver configured to receive a first set of signals from the one or more group receivers; and a processing unit operatively coupled to the at least one transceiver, and which can be configured to: receive the first set of signals from the at least one transceiver; de-multiplex the first set of signals to generate a set of serial data; perform complex weighting and summation on the generated set of serial data, based on a predefined summation coefficient, wherein the processing unit can be configured to generate a set of output signals corresponding to a digital beam formed, in response to the complex weighting and summation of the generated set of serial data.
[0041] In an embodiment, the processing unit can include one or more serializer and
deserializer (SerDes) modules which can be configured to facilitate communication of the one
or more beam former modules with each other, and the one or more group receivers.
[0042] In an embodiment, the apparatus can include a signal processor operatively
coupled to the one or more beam former modules through the one or more SerDes modules and the at least one transceiver.
[0043] In an embodiment, the signal processor can be configured to receive and process
the set of output signals to extract as set of target data to enable detection of a target.

[0044] In an embodiment, the one or more beam former modules can be configured on
a printed circuit board (PCB), and wherein the one or more beam former modules can be
positioned in a stacked configuration on the PCB using a multi lane serial back plane interface.
[0045] In an embodiment, the apparatus can include a set of front panel facia
connectors being configured on the PCB, and which can be configured to facilitate operative
coupling of the one or more receivers to the at least one transceiver of the apparatus.
[0046] In an embodiment, the at least one transceiver can be connected to any of the
set of front panel facia connectors and the multi lane serial back plane interface using one or more fly-over cables.
[0047] In an embodiment, the processing unit can be configured with a data transfer
protocol including any or a combination of serial front panel data port (sFPDP), serial rapid input output (SRIO), and peripheral component interconnect express (PCIe).
[0048] In an embodiment, the at least one transceiver can be a multi-channel optical
transceiver.
[0049] In an embodiment, the first set of signals received can be multiplexed digitized
down converted signals generated by the one or more group receivers based on a set of incoming signals sensed by the antenna.
[0050] FIG. 1 illustrates a single P-channel group receiver interfaced to array elements
enclosed in LRU, in accordance with an exemplary embodiment of the present disclosure.
[0051] As illustrated in FIG. 1, the phased array antenna can be made up of plurality of
antenna elements "N" each of which is individual transmit and/or receive module. Further, a small group of "M" element can be combined within line replaceable unit (LRU) and their outputs can be combined at radio frequency (RF) level. Sub-array can be formed with "P" such group of such entities with each of the RF channels "P" being down converted to an Intermediate frequency (IF) frequency by the analog "P" channel receiver
[0052] In an embodiment, the group receiver 104 associated with sub array of (M x P)
elements digitize "P" channel IF frequencies, can perform digital down conversion (DDC) and translates the IF frequencies into In-phase and Quadrature (I & Q) phase base band. The In-phase and Quadrature phase base band data of "P" channels can be multiplexed and transmitted serially over optical fibre links to the proposed reconfigurable digital beam former apparatus for digital forming to form digital beam and further processing of the output data (digital beam formed) for detection of a target.
[0053] In an embodiment, the group receiver 104 can be a P channel group receiver
adapted to be operatively coupled to one or more LRU units 102-1 to 102-P through RF

channels. The group receiver 104 can include band pass filter (BPF) and low pass filter (LPF) to perform filtering od the signals received form the LRU units. The group receiver 104 can include a low-noise amplifier (LNA) and a mixer, an automatic gain controller (AGC), an analog to digital convertor (ADC), the DDC to process the received signals to generate the (I & Q) phase base band. The group receiver 104 can further include a Data Multiplexer 106 to multiplex the (I & Q) phase base band to generate multiplexed data output (also referred to as first set of signals, herein).
[0054] In an exemplary embodiment, the multiplexed data output can be serially
transmitted over optical fibre links 108 to the proposed hardware module for digital beam forming.
[0055] FIG. 2 illustrates the proposed hardware module of the reconfigurable digital
beam former (DBF) apparatus based on high speed SerDes I/O supporting multi-channel
optical transceivers, in accordance with an exemplary embodiment of the present disclosure.
[0056] As illustrated in FIG. 2, the hardware module 200 of the reconfigurable digital
beam former (DBF) apparatus is disclosed. The hardware module 200 (also referred to as digital beam former module 200, herein) can be adapted to be operatively coupled to one or more group receivers 104 associated with sub-arrays of the phased array antenna. The beam former module 200 can include at least one transceiver 202 (also referred to as multi-channel optical transceiver or transceiver 202, herein), which can be configured to receive the first set of signals from the group receivers 104, and transmit it to a re-configurable processing chipset 204 (also referred to as processing unit 204, herein) that is being operatively coupled to the transceiver 202.
[0057] In an exemplary embodiment, the proposed hardware module 200 can receive
the serially transmitted multiplexed data output from the optical fibre links 108 for digital beam forming.
[0058] In an embodiment, the processing unit 204 can be configured to receive the first
set of signals from the transceiver 202, de-multiplex the first set of signals to generate a set of serial data, and perform complex weighting and summation on the generated set of serial data, based on a predefined summation coefficient, to generate a set of output signals corresponding to a digital beam formed. The antenna radiation pattern required can be programmed on-the-fly by changing the beam summation coefficients computed by processing unit
[0059] In an embodiment, the processing unit 204 can include one or more serializer
and deserializer (SerDes) I/O modules 206-1 to 206-4 (collectively referred to as SerDes modules 206, herein) which can be configured to facilitate communication and connection of

the beam former modules 200 with each other, as well as with the one or more group receivers 104.
[0060] In another embodiment, the apparatus 200 can include a signal processor 218
operatively coupled to the beam former modules 204 through the SerDes modules 206 and the transceiver 202. The signal processor 218 can be configured to receive and process the set of output signals to extract as set of target data to enable detection of a target.
[0061] In an exemplary embodiment, the processing unit can include a mulit-channel
serial data serializer to transmit the output signals to the signal processor through the SerDes modules.
[0062] In an embodiment, the processing unit 204 can include a complex weighting
and summation unit 210 to receive the demultiplexed data form the SerDes module 206-1, 2016-2 through data first input first output (FIFO) module 208-1, 208-2 respectively, to perform complex weighting and summation on the demultiplexed serial data, based on a predefined summation coefficient. In an implementation, the processing unit 204 can include various computational resources (processors) and buffer memory 212 for complex multiplications, in a fully pipelined manner for achieving maximum throughput.
[0063] In an embodiment, the processing unit 204 can include a user protocol formatter
unit 214 that can be configured with a data transfer protocol including any or a combination of serial front panel data port (sFPDP), serial rapid input output (SRIO), and peripheral component interconnect express (PCIe). This feature facilitates the proposed apparatus 200 to be interfaced to other similar BFM modules 200 connected to backplane based on industry standard multi-lane serial protocols as mentioned above.
[0064] FIG. 3 illustrates an exemplary modular DBF system hardware based on serial
back plane interface, in accordance with an exemplary embodiment of the present disclosure.
[0065] In an implementation, for a large antenna arrays with "R" number of group
receivers (104-1 to 104-R) there will be "R" number of optic links to be handled by the proposed hardware. Also, the complex multiplications performed by the processing unit can depend upon the number of received virtual beams to be formed. For this purpose, the present invention can be made fully modular with each hardware module 200 (digital beam forming modules 200) handling a fixed number of optical channels, and the computational load be shared among multiple DBF module) as shown in FIG, 3. This design architecture can be fully scalable for larger antenna arrays of arbitrary size, with industry standard serial backplane based communication between the hardware modules.

[0066] In an embodiment, one or more digital beam former modules 200-1 to 200-N
(collectively referred to as digital beam former (DBF) modules 200, herein) can be configured on a printed circuit board (PCB), where beam former modules 200 can be positioned in a stacked configuration on the PCB using a multi lane serial back plane interface 302. As a result, the present disclosure provides a compact and low powered hardware scheme 300 for digital beam formers for phased array radar receiver application, which can be used in fully scalable antenna architecture with multiple group receivers 104-1 to 104-R.
[0067] As the phased array antennas require periodic calibration of the phase and
amplitude of individual antenna elements for proper radiation pattern with reduced side lobe levels. The present invention provides the means of effective calibration by controlling each of the group receivers in turn all the individual elements associated with it.
[0068] FIG. 4 illustrates an exemplary connectivity method using multiple channel
flyover optical transceivers and serial backplane for maximum I/O bandwidth, in accordance with an exemplary embodiment of the present disclosure.
[0069] In an embodiment, the proposed apparatus 400 can include a set of front panel
facia connectors 402-1, 402-2 (collectively referred to as front panel facia connector 402, herein) being configured on the PCB, and which can be configured to facilitate operative coupling of the group receivers 104 to the transceivers 202-1 to 204-2 (also referred to as plug-in optical transceiver 204, herein) of the apparatus. In another embodiment, the transceiver 204 can be connected to any of the set of front panel facia connectors 402 and the multi lane serial back plane interface 404 using one or more fly-over cables. The transceiver 202 can be multi¬channel optical transceiver.
[0070] Existing compact multi-channel plug-and-play optical transceivers available in
the art require bigger foot prints on the PCB and accommodating multiple fibre channels within standard form factor PCB is very challenging. In addition, the complexity of PCB routing with multiple high-speed transceiver lanes routed on PCB substrate to the processing chipset will result in signal integrity issues which is very critical.
[0071] In order to overcome the above technical problem, the present invention
provides a novel design approach to avoid conventional PCB trace routing of such high-speed transceiver lanes, by using fly-over cables for connecting the front panel facia to optical engines placed very close to the processing unit.
[0072] As illustrated in FIG. 4, the connection of the multi-channel optical transceivers
204-1 to 204-4 using the fly over cables from the set of front panel facia connectors 402-1,

402-2, as well as the set of serial back plane connectors 404, gives the proposed apparatus with
an additional flexibility in connecting multiple optical links.
[0073] In an implementation, the customization of the backplane connectors can be
done to make provision for rugged multichannel optical back plane interconnects (VITA66.1
standard) for applications which need to process data from large number of optical links routed
through back plane.
[0074] The method of connecting the optical transceivers 202 on the PCB with fly-over
cabling from the front panel facia connector 402 or the backplane connector 404 gives great
flexibility for system design and cabling. Also, their close placement to the SerDes IO pins of
the processing unit 204 results in avoiding longer PCB trace lengths for such high-speed serial
lanes, thereby significantly improving the signal integrity of the present invention.
[0075] As the design is provisioned to trade-off between the achievable lane rate for
serial transceivers and power dissipation requirements which in turn impacts the cooling
requirements and the design cost of heat sink required for the present invention.
[0076] Further, the method of serial backplane data communication between multiple
DBF modules 204 reduces the signal integrity issues associated in running wide parallel data
buses on the backplane PCB, thereby simplifying the routing complexity and hence reducing
the design cost of the present invention.
[0077] While the foregoing describes various embodiments of the invention, other and
further embodiments of the invention may be devised without departing from the basic scope
thereof. The scope of the invention is determined by the claims that follow. The invention is
not limited to the described embodiments, versions or examples, which are included to enable
a person having ordinary skill in the art to make and use the invention when combined with
information and knowledge available to the person having ordinary skill in the art.
ADVANTAGS OF THE INVENTION
[0078] The proposed invention provides a re-configurable hardware platform resulting
in compact, low cost and agile Radar processing hardware.
[0079] The proposed invention provides a re-configurable digital beam former
apparatus with multi-channel optical backplane connectivity.
[0080] The proposed invention provides a hardware scheme for digital beam former
for phased array radar receiver application, which can be used in fully scalable antenna
architecture with multiple group receivers.

[0081] The proposed invention provides a re-configurable hardware having abundant
computational resources for DDC, complex weighting multiplication and summation stages for forming multiple target beams.
[0082] The proposed invention provides reduces signal routing complexity of the PCB
of the former apparatus, thereby improving the signal integrity to achieve lane rates of multi-channel optical links.

We Claim:
1. A reconfigurable digital beam former (DBF) apparatus with multi-channel optical
backplane connectivity, the apparatus comprising:
one or more digital beam former modules adapted to be operatively coupled to one or more group receivers associated with sub-arrays of a phased array antenna, wherein each of the one or more beam former modules comprises:
at least one transceiver configured to receive a first set of signals from the one or more group receivers; and
a processing unit operatively coupled to the at least one transceiver, and configured to:
receive the first set of signals from the at least one transceiver; de-multiplex the first set of signals to generate a set of serial data;
perform complex weighting and summation on the generated set of serial data, based on a predefined summation coefficient, wherein the processing unit is configured to generate a set of output signals corresponding to a digital beam formed, in response to the complex weighting and summation of the generated set of serial data.
2. The apparatus as claimed in claimed 1, wherein the processing unit comprises one or more serializer and deserializer (SerDes) modules configured to facilitate communication of the one or more beam former modules with each other, and the one or more group receivers.
3. The apparatus as claimed in claim 2, wherein the apparatus comprises a signal processor operatively coupled to the one or more beam former modules through the one or more SerDes modules and the at least one transceiver.
4. The apparatus as claimed in claim 3, wherein the signal processor is configured to receive and process the set of output signals to extract as set of target data to enable detection of a target.
5. The apparatus as claimed in claim 1, wherein the one or more digital beam former modules are configured on a printed circuit board (PCB), and wherein the one or more beam former modules are positioned in a stacked configuration on the PCB using a multi lane serial back plane interface.
6. The apparatus as claimed in claim 5, wherein the apparatus comprises a set of front panel facia connectors being configured on the PCB, and configured to facilitate

operative coupling of the one or more group receivers to the at least one transceiver of the apparatus.
7. The apparatus as claimed in claim 6, wherein the at least one transceiver is connected to any of the set of front panel facia connectors and the multi lane serial back plane interface using one or more fly-over cables.
8. The apparatus as claimed in claim 1, wherein the processing unit is configured with a data transfer protocol comprising any or a combination of serial front panel data port (sFPDP), serial rapid input output (SRIO), and peripheral component interconnect express (PCIe).
9. The apparatus as claimed in claim 1, wherein the at least one transceiver is multi-channel optical transceiver.
10. The apparatus as claimed in claim 1, wherein the first set of signals received are multiplexed digitized down converted signals generated by the one or more group receivers based on a set of incoming signals sensed by the antenna.