Claims:I/We claim
1. A reconfigurable integrated platform to perform real-time simulations, wherein the platform comprises of:
an integrated hardware circuitry capable of reconfiguring to perform hardware-in-loop simulations, wherein the hardware circuitry consists of:
one master Field Programmable Gate Array (FPGA) board;
four Input/ Output (IO) boards configured to receive various kinds of input signals and configured to deliver various output signals;
four FPGA’s integrated to each IO board;
a backplane architecture for inter-connecting and inter-communication between each IO board
a plurality of standardized bus systems provided on the said backplane for communicating between the said IO boards;
two power supply module boards for supplying power to individual circuit boards;
a chassis frame for mounting all the hardware circuitry to perform real-time simulations;
a processor board configured for transferring data to master FPGA board through an operating system;
one PCI-express connector configured to transfer data from the processor board to the master FPGA;
an Integrated Development Environment (IDE),designed to provide a single platform for reconfiguring the hardware circuitry to create, modify, compile and/or optimize the application.

2. The master FPGA board according to claim 1, characterized to be connected with a plurality of interfaces at a plurality of ports to perform various operations include:
an interface to achieve high-speed operation;
a serial flash memory configured with advanced write protection mechanism and accessed by a high speed Serial Peripheral Interface (SPI) bus;
a clock oscillator interface for generating clock signals for FPGA;
a reset interface configured for generating internal-power fail signal when an out-of-tolerance condition is detected forcing the rest of the affected device to an active state;
a JTAG interface configured for emulating, debugging and downloading, allowing internal access to scan chains;
an RS232 standard for serial communication transmission of data; and
an Ethernet interface, provided to perform software programming to the master FPGA.

3. The FPGA’s other than the master FPGA according to claim 1, characterized to provide effective integration capabilities by connecting a plurality of interfaces at a plurality of ports to perform various operations include:
a clock oscillator interface for generating clock signals for FPGA;
a reset interface configured for generating internal-power fail signal when an out-of-tolerance condition is detected forcing the rest of the affected device to an active state;
a JTAG interface configured for emulating, debugging and downloading purpose allowing internal access to scan chains;
an Electrically Erasable and Programmable Read Only Memory (EEPROM) provided with cascade a feature to share two-wire buses;
a plurality of buffers configured to interface the signals of external connector to the FPGA;
a Digital to Analog Convertor (DAC) interface;
an Analog to Digital Convertor (ADC) interface;
an operational amplifier capable of choosing the gain bandwidth suitable for the application;
an opto-coupler configured for transferring signals using light for extremely high resolution; and
a poly-fuse for surface mount over current protection.

4. The four IO boards according to claim 1, characterized to also comprise a 51 pin D-connector for transferring output and input signals to the master FPGA.

5. The standardized bus according to claim 1, characterized to inter-connect and inter-communicate between the IO boards and includes a plurality of VME64X connectors.

6. The four IO boards according to claim 1, characterized for receiving and transferring output signals to the master FPGA, wherein the IO boards include:
board HP (high precision);
board B;
board C; and
board D.

7. The board HP according to claim 4, characterized for receiving various input signals and transferring output signals include:
three analog inputs signals of differential type;
fifteen digital input signals; and
fifteen digital output signals to front panel 51 pin D connector.

8. The board B according to claim 4, characterized for receiving various input signals and transferring output signals include:
three analog input signals of single-ended type;
eight digital input signals; and
fifteen digital output signals to front panel 51 pin D connector.

9. The board C according to claim 4, characterized for receiving various input signals and transferring output signals include:
twenty analog input signals of single-ended type;
eight digital input signals; and
eight digital output signals to front panel 51 pin D connector.

10. The board D according to claim 4, characterized for receiving various input signals and transferring output signals include:
three analog input signals of single-ended type;
sixteen analog output signals to front panel 51 pin D connectors; and
six digital output signals to front panel 51 pin D connectors.

11. The PCI-e connector according to claim 1, characterized to be used as an interface between the processor board and the master FPGA for two way data transfer.

12. The processor board according to claim 1, characterized for supporting a real-time operating system includes an (QNX) operating system.

13. The IDE according to claim 1, characterized to be used as an interface for monitoring, processing and controlling the working of hardware circuitry in an application used.

14. The integrated platform according to claim 1, characterized for reconfiguring the four IO boards by performing software programming through their integrated FPGA’s.

15. The power supply boards according to claim 1, characterized to supply power to on board components by internally generating the required power supplies through a plurality of components, wherein include:
a plurality of DC-DC regulators; and
a plurality of linear power supply regulators.

16. A method for transferring data from a reconfigurable integrated platform to perform real-time simulations, wherein the method comprises steps of:
accessing of an integrated hardware circuitry for reconfiguring;
transferring of data from a processor board to a master FPGA board through an operating system;
transferring of various signals to a master FPGA board through a plurality of interface at a plurality of ports;
receiving of various input signals by four IO boards;
processing of the received various input signals by the four IO boards;
sending of various output signals to the master FPGA by the four IO boards through a 51 pin D-connector; and
transferring of the received output signals from IO boards by the master FPGA.

17. The method according to claim 16, wherein receiving and sending of various input signals and output signals to the master FPGA board through IO boards includes:
board HP (high precision);
board B;
board C; and
board D.

18. The method according to claim 16, wherein includes a standardized bus for inter-connecting and inter-communicating between the IO boards consisting of a plurality of VME64X connectors.

19. The method according to claim 16, wherein the processor board is supported by a real-time operating system includes an (QNX) operating system.

20. The method according to claim 16, wherein uses an Integrated Development Environment (IDE) as an interface for monitoring, processing and controlling the working of hardware circuitry in an application used.

21. The method according to claim 16, wherein performs a software programming for reconfiguring the hardware circuitry through their integrated FPGA’s.
, Description:Technical Field of the Invention

[0001] Present invention relates to a reconfigurable integrated hardware platform. More particularly, the present invention relates to a method for transferring data from a reconfigurable integrated platform to perform real-time simulations.

Background of the Invention

[0002] Several types of hardware development platforms are available in the market for performing monitoring, processing and controlling of real-time operations through various integrated hardware platforms. These integrated hardware platforms are defined and designed for a particular application. If any person intended to use this hardware platform in any another application, there is a need to design a new hardware platform suitable for that application seeking to use for performing real-time operations which is adding high cost of designing and producing costs to the system.

[0003] Therefore, there is a need to an integrated hardware platform capable of reconfiguring according to the desired application which the platform is intended for performing real-time simulations/operations.

Brief Summary of the Invention

[0004] The present invention recognizes the limitations of the prior art and the need for systems and methods that are able to provide assistance to users in a manner that overcomes these limitations.

[0005] A principle object of the present invention is to provide a reconfigurable integrated hardware platform to perform real-time simulations.

[0006] Another object of the present invention is to provide a hardware platform for monitoring, processing and controlling operations according to the application configured.

[0007] According to a first aspect of present invention, a reconfigurable integrated platform to perform real-time simulations. The platform comprises of an integrated hardware circuitry capable of reconfigurable to perform hardware-in-loop simulations consisting of one master Field Programmable Gate Array (FPGA) board and four input/output (IO) boards configured to receive various kinds of input signals and configured to deliver various output signals.

[0008] In accordance with the first aspect of present invention, further the hardware circuitry consist of four FPGA’s integrated to each IO board, a back plane architecture for inter-connecting and inter-communication between each IO board, a plurality of standardized bus systems provided on the said backplane for communicating between the said IO boards, two power supply module boards for supplying power to individual circuit boards and a chassis frame mounting all the hardware circuitry to perform real-time simulations.

[0009] In accordance with the first aspect of present invention, further the hardware platform also comprises of a processor band configured for transferring data to master FPGA board through an operating system, one PCI-express connector configured to transfer data from the said processor board to the said master FPGA and an Integrated Development Environment (IDE) designed to provide a single platform for reconfiguring the hardware circuitry to create, modify, compile and/or optimize the application.

[0010] In accordance with the first aspect of present invention, the master FPGA board of the hardware platform is connected with a plurality of interfaces at a plurality of ports to perform various operations include an interface to achieve high-speed operation, a serial flash memory configured with advanced write protection mechanism and accessed by a high speed Serial Peripheral Interface (SPI) bus and clock oscillator interface for generating clock signals for FPGA.

[0011] In accordance with the first aspect of present invention, further the master FPGA board includes a reset interface configured for generating internal-power fail signal when an out-of-tolerance condition is detected forcing the rest of the affected device to an active state, a JTAG interface configured for emulating, debugging and downloading, allowing internal access to scan chains, an standard for serial communication transmission of data and an Ethernet interface is provided to perform software to the master FPGA.

[0012] In accordance with the first aspect of present invention, the FPGA’s other than the master FPGA provides an effective integration capabilities by connecting a plurality of interfaces at a plurality of ports to perform various operations include a clock oscillator interface for generating clock signals for FPGA, a reset interface configured for generating internal-power fail signal when an out-of-tolerance condition is detected forcing the rest of the affected device to an active state, a JTAG interface configured for emulating, debugging and downloading purpose allowing internal access to scan chains and an Electrically Erasable and Programmable Read Only Memory (EEPROM) provided with cascade a feature to share two-wire buses.

[0013] In accordance with the first aspect of present invention, further the FPGA’s other than the master FPGA provides a plurality of buffers configured to interface the signals of external connector to the FPGA, a Digital to Analog (DAC) interface, an operational amplifier capable of choosing the gain bandwidth suitable for the application, an opto-coupler configured for transferring signals using light for extremely high resolution and a poly-fuse surface mount over current protection.

[0014] In accordance with the first aspect of present invention, the four IO boards comprise a 51 pin D-connector for transferring output and input signals to the master FPGA.

[0015] In accordance with the first aspect of present invention, the standardized bus is employed for inter-connect and inter communicate between the IO boards and includes a plurality of VME64X connectors.

[0016] In accordance with the first aspect of present invention, the four IO boards are employed for receiving and sending input and output signals to the master FPGA. The IO boards include board HP (high precision), board B, board C and board D.

[0017] In accordance with the first aspect of present invention, the board HP is employed for receiving various input signals and transferring output signals include three analog inputs signals of different type, fifteen digital input signals of differential type and fifteen digital output signals to front panel 51 pin D connector.

[0018] In accordance with the first aspect of present invention, the board B is employed for receiving various input signals and transferring output signals include six analog input signals of single-ended type, eight digital input signals and fifteen digital output signals to front panel 51 pin D connector.

[0019] In accordance with the first aspect of present invention, The board C is employed for receiving various input signals and transferring output signals include twenty analog input signals of single-ended type, eight digital input signals and eight digital output signals to front panel 51 pin D connector.

[0020] In accordance with the first aspect of present invention, the board D is employed for receiving various input signals and transferring output signals include three analog input signals of single-ended type, sixteen analog output signals to front panel 51 pin D connector and six digital output signals to front panel 51 pin D connector.

[0021] In accordance with the first aspect of present invention, the PCI-e connector is used as an interface between the processor board and the master FPGA for two data transfer.

[0022] In accordance with the first aspect of present invention, the processor board for supporting a real-time operating system includes an (QNX) operating system.

[0023] In accordance with the first aspect of present invention, the IDE is used as an interface for monitoring, processing and controlling the working of hardware circuitry in an application used.

[0024] In accordance with the first aspect of present invention, the integrated platform for reconfiguring the four IO boards by performing software programming through their integrated FPGA’s.

[0025] In accordance with the first aspect of present invention, the power supply boards for supplying power to on board components by internally generating the required power supplies through a plurality of components include a plurality of DC-DC regulators and a plurality of linear power supply regulators.

[0026] According to a second aspect of present invention, a method for transferring data from a reconfigurable integrated platform to perform real-time. The method comprises steps of accessing of an integrated hardware circuitry for reconfiguring, transferring of data from a processor board to a master FPG board through an operating system and transferring of various signals to a master FPGA board through a plurality of interface at a plurality of ports.

[0027] In accordance with the second aspect of present invention, further the method comprises of receiving of various input signals by four IO boards, processing of the received various input signals by the four IO boards, sending of various output signals to the master FPGA by the four IO boards through a 5 pin D-connector and transferring of the received output signals from IO boards by the master FPGA to a graphical user interface through a PCI-express connector.

[0028] In accordance with the second aspect of present invention, the method for receiving and sending of various input signals and output signals to the master FPGA board through IO boards includes board HP (high precision), board B, board C and board D.
[0029] In accordance with the second aspect of present invention, the method includes a standardized bus for inter-connecting and inter-communicating between the IO boards consisting of a plurality of VME64X connectors.

[0030] In accordance with the second aspect of present invention, the method comprises the processor board is supported by a real-time operating system includes an (QNX) operating system.

[0031] In accordance with the second aspect of present invention, the method uses an Integrated Development Environment (IDE) as an interface for monitoring, processing and controlling the working of the hardware circuitry in an application used.

[0032] In accordance with the second aspect of present invention, the method performs a software programming for reconfiguring the hardware circuitry through their integrated FPGA’s.

Brief Description of the Drawings

[0033] Other objects and advantages of the present invention will become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments, in conjunction with the accompanying drawings, wherein like reference numerals have been used to designate like elements, and wherein

FIG. 1 illustrates a block diagram depicting a reconfigurable integrated hardware platform according to the present invention.

FIG. 2 illustrates a block diagram depicting a processor board according to the present invention.

FIG. 3 illustrates a block diagram depicting a FPGA master board connected with plurality of interfaces according to the present invention.

FIG. 4 illustrates a block diagram depicting a board HP for sending and receiving input and output signal to master FPGA according to the present invention.

FIG. 5 illustrates a block diagram depicting a board B for sending and receiving input and output signal to master FPGA according to the present invention.

FIG. 6 illustrates a block diagram depicting a board C for sending and receiving input and output signal to master FPGA according to the present invention.

FIG. 7 illustrates a block diagram depicting a board D for sending and receiving input and output signals to master FPGA according to the present invention.

FIG. 8 illustrates a perspective view depicting mechanical diagram of main chassis according to the present invention.

FIG. 9 illustrates a block diagram depicting an FPGA with plurality of interfaces according to the present invention.

FIG. 10 illustrates a block diagram depicting an opto-coupler interface with FPGA according to the present invention.

FIG. 11 illustrates a block diagram depicting an operational amplifier interface with FPGA according to the present invention.

FIG. 12 illustrates a block diagram depicting power supply interface for FPGA according to the present invention.

Detailed Description of the Invention

[0034] The present invention is directed towards a reconfigurable integrated hardware platform to perform real-time simulations and a method for transferring the data. Referring to the drawings, wherein like reference numerals designate identical or corresponding systems, preferred embodiments of the present invention are described.

[0035] Referring to the drawings, FIG. 1 illustrates a block diagram (100) depicting the reconfigurable integrated hardware platform according to the present inventions. A reconfigurable integrated platform performs real-time simulations for monitoring, processing and controlling. The reconfigurable integrated platform comprises a processor board (104), four input/output IO boards includes board HP (108), board B (110), board C (112) and board D (114), at least one master FPGA board (106), at least two power supply module boards (116a) and (116b) housed in a mechanical chassis (102) to perform real-time simulations and an Integrated Development Platform (120) for reconfiguring the hardware circuitry to create and/or modify and/or compile and/or optimize the application through switch (122). The data is transmitted from processor board to master FPGA through a PCI-express interface (118) for two way data transmission and the processor board (104) is supported by real-time operating system through (QNX) operating system.

[0036] FIG. 2 illustrates a block diagram (200) depicting the processor board (204) according to the present invention. The processor board (204) operated for performing real-time operations embedded with (QNX) operating system for transferring the data to the master FPGA board. The data is transmitted from the processor board (204) to the master FPGA board through a PCI-express connector (218). A reset interface (224) is connected to the processor board (204) for generating internal-power fail signal when an out-of-tolerance condition is detected forcing the rest of the affected device to an active state. The processor board (204) interfaces with IO connectivity of four serial ports includes two RJ45 Ethernet ports (236a) and (236b) with different MAC address and USB connectors (230a) and (230b). A double data memory (DDR3) (232) for high speed operations and a SPI BIOS (228) for advanced write protection mechanism.

[0037] FIG. 3 illustrates a block diagram (300) depicting FPGA master board (306) connected with plurality of interfaces according to the present invention. FPGA master board (306) is processor controlled IO board and is connected with a plurality of interfaces at a plurality of ports. The IO boards includes PCI-express connector (318), black plane architecture interface (338), RS232 (344), DDR2 (340), SPI-Flash (342), Ethernet (346), reset (324), clock (350) and JTAG (352). The PCI-express connector (318) transfers the data from the processor board (204) to the master FPGA board (306).

[0038] The received input signals from the master FPGA board (306) are transmitted to the four IO boards includes board HP (108), board B (110), board C (112) and board D (114) process it through RS232 (344) serial communication transmission of data. The processed input signals of four IO boards inter communicate and interconnecting through the black plane architecture (338) and sends the output signals to the master FPGA board (306) through 51 pin D-connector (470). The JTAG interface (352) emulates, debugs and downloads to allow internal access to scan chains and Ethernet interface (346) for performing software programming to the master FPGA board (306).

[0039] FIG. 4 illustrates a block diagram (400) depicting the board HP for sending and receiving input and output signal to master FPGA board according to the present invention. The standardized bus includes black plane architecture (338) of VME64X connectors (472) for inter connecting and inter communicating between the IO boards. The FPGA board (454) receives the analog inputs. The FPGA board (454) receives 15 digital inputs signals with an Op-Amp.

[0040] FIG. 5 illustrates a block diagram (500) depicting board B board for sending and receiving input and output signal to master FPGA board according to the present invention. The standardized bus includes black plane architecture (338) of VME64X external connectors (572) for inter connecting and inter communicating between the IO boards. The FPGA board (554) receives the analog inputs comprises six analog inputs of single-ended by choosing the gain bandwidth to FPGA board (554) and digital outputs (568) comprises 15 digital outputs transferred to front panel 51 Pin D connectors (570) with extremely high resolution for isolation by using digital input (562) comprises opto–coupler (not shown). The power regulators (560) to power all the internal components.

[0041] FIG. 6 illustrates a block diagram (600) depicting board C board for sending and receiving input and output signal to master FPGA board according to the present invention. The standardized bus includes black plane architecture (338) of VME64X connectors (672) for inter connecting and inter communicating between the IO boards. FPGA board (654) receives the analog inputs comprises twenty analog inputs of single-ended type external connectors (672) interface to configure buffers (658) within the choosing the gain band width to FPGA board (654). FPGA board receives the digital inputs (662) comprises eight digital inputs from the external connectors (672) interface to configure buffers (658) with Op-Amp (664) for choosing the gain band width to FPGA board (654) and digital output (668) comprises eight digital outputs transferred to front panel 51 Pin D connectors (670) with extremely high resolution for isolation by using digital input (662) comprises opto–coupler (not shown). The power regulators (660) power all the internal components.

[0042] FIG. 7 illustrates a block diagram (700) depicting board D board for sending and receiving input and output signals to master FPGA according to the present invention. The standardized bus connectors (772) for inter-connecting and inter-communicating between the IO boards. The FPGA board (754) receives the analog inputs comprises three analog inputs of single-ended external connectors (772) to configure buffers (758) within the Op-Amp (764) for choosing the gain bandwidth to FPGA board (754). The FPGA board (754) sends the analog outputs (762) comprises sixteen analog outputs from the VME64X external connectors (772) to configure buffers (758) to FPGA board (754) and digital output (768) comprises six digital outputs transferred to front panel 51 Pin D connectors (770) with extremely high resolution for isolation by using opto–coupler (not shown). The integrated platform (120) is used for reconfiguring the four IO boards by performing software programming through their integrated FPGA’s.

[0043] FIG. 8 illustrates a perspective view depicting mechanical diagram (800) of main chassis (102) according to the present invention. The main chassis (102) mounts all the hardware circuitry forms a reconfigurable integrated hardware platform to perform real time simulations.

[0044] FIG. 9 illustrates a block diagram (900) depicting FPGA (954) other than master FPGA (106) with a plurality of interfaces according to the present invention. The FPGA (954) comprising four IO boards each for receiving and sending input and output data from the FPGA master board (106). The buffers (958) are used to interface the signals of VME64X external connector (972) interface to the FPGA board (954). The VME64X external connector (972) interface signals are of 5V tolerance which is to be interfaced to the FPGA (954) through buffers (958) which accept 3.3V signals as output.

[0045] An Electrically Erasable and Programmable Read Only Memory (EEPROM) (956) provided with cascade a feature to share two-wire buses for low voltage operations. A Digital to Analog Convertor (DAC) (978) interface is a programmable voltage output used to convert the digital data into analog data and an Analog to Digital converter (ADC) (966) is configured through hardware or via a dedicated write only serial configuration port for input range and operating mode. The opto-coupler (976) provides extremely high resolution for transferring signals to FPGA board (954) using light. This high resolution output signal is transferred to the master FPGA (106). A poly fuse (not shown) interface provides surface mount over current protection for applications.

[0046] FIG.10 illustrates a block diagram 1000 depicting an opto-coupler interface with FPGA according to the present invention. The external connectors interface (1072) to FPGA (1054) and opto-coupler interface (1076) is connected to FPGA (1054). The digital outputs (1068) is transferred to front panel 51 Pin D connectors (1070) with extremely by using digital input (not shown) comprises opto–coupler (1076). FIG. 11 illustrates a block diagram 1100 depicting an operational amplifier interface with FPGA according to the present invention. The operational amplifier interface (1164) connected to an FPGA (1154) through an ADC (1166).

[0047] FIG. 12 illustrates a block diagram (1200) depicting power supply interface for on board components according to the present invention. The power supply boards supply power to the on board components such as FPGA (1254), buffers (1258), EEPROM (1256), Opto-coupler (1276), ADC (1266), Op-amp (1264), DAC (1278), D-connector (1270), VME64X connectors (1272), a Reset (1224), clock pulses (1250) and Opto-coupler (1276) by internally generating the required power supplies through a plurality of DC-DC regulators (348) and linear power supply regulators embedded on the backplane of the hardware platform.

[0048] The detailed description of the above embodiment of the present invention is only for ease of understanding the invention. The cited examples should not be construed as limiting the scope of the invention. Any person skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.