The present invention relates generally to aircraft avionics FDR (Flight Data Recording
System) with a method of recording and storing Built in Test results and, more particularly,
to time saving methods for FDRs including new data recording method and methods for
analyzing and diagnosing the FDR health without the need for time consuming efforts. It is a
feature of the invention that improved recording, storing and retrieval of FDR health
representing error words is obtained on consistent basis for different sorties not carrying
any digital data. The term “health” as used throughout this specification is intended to mean
the condition of various hardware modules of the FDR to perform the function required of it.
BACKGROUND OF THE INVENTION
The rotary wing light weight helicopter is required to maintain and provide historical
recording of certain flight parameters. The mandated flight data are derived from
continuous recording during operational flight of an aircraft and include a minimum number
of functional parameters considered essential for reconstructing the aircraft flight profile in
post‐ accident investigation proceedings.
According to one embodiment the FDRs, consists of the Flight data acquisition and retrieval
units. The FDRs is primarily an investigative tool for reconstructing and evaluating the
performance of an aircraft prior to and during an accident or incident. During an
investigation, the data recorded in the FDR is used to better assist the investigation of such
accidents and incidents.
The flight data are recorded on a flight data recording system designed to withstand crash
environments. The FDR system typically employs an ARINC‐717 and ARINC‐429 digital bus
transmitter and receiver for communication with other aircraft subsystems. The current
generation FDRs generally consist of logic running on main processor which first initializes
the Timers, WatchDog, different ports, digital bus transmitter and receiver, Ethernet Port,
RS232 Port and Crash Protected Memory interface, then performs built in test for the
system and acquires digital data then audio data continuously while in record mode. The
same data is then formatted as per the defined data and voice frame format and stored in
crash protected environment. This stored data can be retrieved for further analysis of
parameters.
Conventional recording methods have pre‐requisite condition of recording condition ON and
availability of digital data to start recording. In case of flights where there is problem in
digital interface recording will not take place which increases the difficulty of maintenance
crew, investigating agency to find out what actually went wrong.
Thus, there is a need in the art for a method for mandatorily recording FDR health related
error words and storing them in existing defined data frame formats without the need for a
complete hardware functionality checking of FDR again and again at ground which may be
time consuming.
SUMMARY OF PRESENT INVENTION
In accordance with one aspect of the present invention is to provide a flight data recorder
system that is capable of recording and storing PBIT error words as per data format even in
absence of digital data.
In accordance with another aspect of the present invention is to provide a flight data
recorder system with improved method for recording, storing and retrieval of FDR health
representing error words.
In accordance with yet another aspect of the present invention is to provide a cockpit voice
flight data recorder system which can form a dummy data frame with all words as 0x00 in
absence of digital data.
In accordance with yet another aspect of the present invention formatting and writing of
aircraft parameters and audio data to CPMM (Crash Protected Memory Module) happens
within 250 milliseconds.
In accordance with yet another aspect of the present invention the Fault Indication LEDs will
glow depending on the decision table given in figure 6 for Power on Built in Test.
In accordance with yet another aspect of the present invention PBIT results will be available
within 10 seconds.
In accordance with yet another aspect of the present invention Power on Built in Test PBIT
will check the functionality of all required hardware modules for example‐Power supply test,
processor test, random access memory test, FLASH test, Crash Protected Memory Module
test, shared RAM test, Non‐volatile RAM test, Ethernet Interface test, digital bus interface
test, RS232 test, Discrete test and CPLD test.
In accordance with yet another aspect of the present invention Continuous Built in Test CBIT
will check the functionality of some required hardware modules for exampleCPU test, CPLD
test, digital bus interface test, Crash Protected Memory Module test, Power supply test and
Discrete test.
In accordance with yet another aspect of the present invention PBIT and CBIT results will
consist of 3 error words (EW1, EW2, EW3) in which one error word will consists of test result
of DSP processor board and these will be placed at defined location in frame format.
Briefly the present invention is a method of recording and storing Built in Test results into
data frames according to the Data Format [Refer Figure‐ 4] and writes these data frames
along with the formatted A/c parameters to the CPMM.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will become more apparent and
descriptive in the description when considered together with figures/flow charts presented:
Fig. 1 is a Block Diagram of the CVFDR.
Fig. 2 is a Flow Chart of operational logic of previous FDRs
Fig. 3is a Flow Chart of operational logic of improved CVFDR
Fig. 4 is a Data Frame Format
Fig. 5 is Voice data format
Fig. 6 is Decision Table
DETAILED DESCRIPTION
The present invention provides a flight data recorder system that is capable of recording and
storing Built in Test (BIT) error word results in absence of digital data for a flight. The
recording, formatting and storing of PBIT and CBIT error words in CPMM helps in diagnosing
the problem due to which digital data was not available. This feature of CVFDR saves time of
the maintenance crew who used to record and download data again and again in case of not
receiving any data even with correct recording condition set. The non‐recording of digital data
may be due to incorrect recording condition or may be due to failure of digital bus interface.
The retrieval and extraction of Error words will clearly show that problem consistently
persisted due to which recording stopped.
With reference to figure 1 there is shown a block diagram for an improved FDR system
according to one embodiment of the invention. In essence, the CVFDR system utilizes one or
more digital data buses for quick access and retrieval of flight data parameters. Specifically, a
digital communication bus and local area network bus are provided within the FDR system for
data access and storage capabilities herein described.
With reference to figure 2 the operational logic running on main processor used to initialize all
the associated hardware modules, performs Power on built in test on the associated hardware
modules in order to monitor the health of the system, then acquires formatted aircraft
parameters sent via the ARINC‐717 Harvard Bi‐phase and ARINC‐429 interface simultaneously
carrying continuous built in test, acquires compressed audio data sent by the DSP processor
via the shared RAM, it then formats the acquired compressed audio data into data frames as
per voice data record formats (Ref figure 5). The internal parameters like Sync words, Sortie
Count, Error Words, Elapsed Time and Real Time Clock are then placed in the data frame. Now
this Aircraft data frame and audio data frame are stored in the crash protected memory
module. This stored data can be downloaded for further analysis. The prerequisite condition
for these FDRs to record internal parameters is correct recording condition set and availability
of digital data.
With reference to figure 3, the operational logic running on main processor used to follow the
same steps as stated above in addition to the recording error words (internal parameters) in
case of non‐ availability of digital data according to one aspect of the invention. As shown in
the flow chart if digital data is not available it will format the frame with dummy data
comprising all words as zero (0x00). Then the internal parameters will be placed at the defined
location as per the frame format and then the formatted audio data will be stored with these
dummy data in the crash protected memory module.
Another aspect of the invention is that the recorded and stored Built in Test results in absence
of digital data can be downloaded though a data downloading equipment. The extraction and
analysis of Built in Test error words will reveal what actually caused non‐availability of digital
data, as error words contains different bits corresponding to the health of different hardware
modules.
While the invention has been described with respect to specific preferred embodiments,
variations and modifications will become apparent to those skilled in the art upon reference
to this specification. It is therefore intended that the appended claims be interpreted as
broadly as possible in view of prior art to include all such variations and modification.

WE CLIAMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. I Claim

1. The method allowing recording and storage of error words data on the FDR even for those sorties in which aircraft data is missing because of digital communication bus interface failure or may be due to any other problem is novel.

2. The process of forming dummy frame with 0x00 in absence of acquired formatted aircraft data is monolithic.

3. The FDR according to claim 1 runs the operational logic on POWER PC along-with logic for audio processor without any compatibility issues.

4. In accordance with yet another aspect of the present invention PBIT results will be available within 10 seconds.

5. In accordance with yet another aspect of the present invention the Fault Indication LEDs will glow depending on the decision table given in figure 6 for Power on Built in Test.

6. In accordance with yet another aspect of the present invention Power on Built in Test PBIT will check the functionality of all required hardware modules for example- Power supply test, processor test, random access memory test, FLASH test, Crash Protected Memory Module test, shared RAM test, Non-volatile RAM test, Ethernet Interface test, digital bus interface test, RS232 test, Discrete test and CPLD test.

7. In accordance with yet another aspect of the present invention Continuous Built in Test CBIT will check the functionality of some required hardware modules for exampleCPU test, CPLD test, digital bus interface test, Crash Protected Memory Module test, Power supply test and Discrete test.

8. In accordance with yet another aspect of the present invention PBIT and CBIT results will consist of 3 error words (EW1, EW2, EW3) in which one error word will consists of test result of DSP processor board and these will be placed at defined location in frame format. ,TagSPECI:As per Annexure-II