Description
BACKGROUND
1. Field of the Invention
The present invention relates generally to design of an integrated circuit, particularly to reducing the effect of variation in constant current sources.
2. Related Art
Constant current sources are often used for driving a circuit portion in an integrated circuit. Desired value of constant current in general, is derived from multiple fixed constant current sources. The value of each fixed current sources is often set to equal to or proportional to a reference current source.
The reference current source is often constructed with higher precision and complexity. In one prior embodiment, the reference current source is implemented using a band gap reference generator as well known in the field of art. Multiple sources of constant current are then constructed using the reference current.
Often reference current is replicated (equal to / proportionate to the reference current) on an additional path using current mirror technique as well known in the field of art. Accordingly, multiple current mirrors are used as multiple constant current sources. A desired number of such current sources are grouped statically or dynamical to provide desired value of constant current to the circuit portion.
The value of the constant current from the current mirror often differs from the desired/designed value. For example, if the current mirror is designed to provide a constant current equal to the reference current, the replicated

current from the current mirror may differ in value from that of the reference current. Accordingly, it is desirable to reduce the effect of such an error either statically or dynamically.
BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described with reference to the following
accompanying drawings.
Figure 1 is a block diagram of an example portion of an integrated circuit in
which various aspect of the present invention may be implemented.
Figure 2 is an example implementation of multiple constant current sources.
Figure 3 is block diagram of a multiple constant current source with prior
calibration and compensation technique.
Figure 4 is a block diagram of an example implementation of calibration
block.
Figure 5 is a flowchart illustrating calibration and compensation of multiple
current sources in one embodiment of the present invention.
Figure 6 is a block diagram illustrating an example implementation of the
various aspect of the present invention.
Figure 7 is a block diagram illustrating an example current steering DAC.
Figure 8 is a block diagram of a current steering L bit DAC in an embodiment
of the present invention.
In the drawings, like reference numbers generally indicate identical,
functionally similar, and/or structurally similar elements. The drawing in
which an element first appears is indicated by the leftmost digit (s) in the
corresponding reference number.

DETAILED DESCRIPTION 1. Overview
According to an aspect of the present invention, each current source from a plurality of current sources is individually calibrated to determine corresponding individual error. A combined error is computed from individual error for a set of current sources. Compensation current is generated based on combined error. The outputs of the set of current sources and compensation current added and provided to a circuit portion as a constant current.
Due to the above approach, a combined compensation current is generated for s set of current sources and thereby reducing the power and size of the compensation circuit. According to another aspect of the present invention, a single calibration circuit time multiplexed to calibrate individually the current sources. Thus the resources are further reduced.
In one embodiment of the present invention, above technique are extended to a current steering digital to analog converter. Combined error for each digital code is computed and stored in memory. Accordingly, for each digital input, corresponding error value is fetched from memory and provided as compensation.
Several aspects of the invention are described below with reference to examples for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details, or with other methods, etc. In other instances, well-known

structures or operations are not shown in detail to avoid obscuring the features of the invention.
2. Example Environment
Figure 1 is a block diagram of an example portion of an integrated circuit in which various aspect of the present invention may be implemented. The block diagram is shown containing reference current source 110, current mirrors 120A-120N, connector 160, and circuit 180. Each block is described below in further detail.
Reference current source 110 provides a reference current IR on path 130. The other end of the reference current source 110 is shown connected to a reference terminal 149. Terminal 149 represents a constant potential node such as ground, , etc. In one embodiment, reference current source 110 is constructed using a band gap reference technique known in the field of art.
Current mirror 120A-120N receives the reference current IR on path 130 and mirror/replicate a constant current respectively on paths 140A-140N. The value of the constant current on each path 140A-HON is proportionate to the reference current IR. Accordingly, each path 140A-HON provides a constant current and hence referred to as constant current terminals of the constant current sources.
Circuit 180 receives a constant current from the current mirrors 120A -120N through connector 160. The magnitude of the constant current may be determined dynamically or statically. Accordingly, connector 160 connects (dynamically/statically) desired number of constant current terminal HOA-HOZ to the circuit portion 160. The number of constant current terminals

required to be connected is determined based on the constant current required for desired operation of circuit portion 180.
For example if the current IK represents the designed/desired constant current required for operation of circuit portion 180 and each current mirror 120A-120N is designed to provide ID current on the respective constant current terminal 140 A-140Z, then corrector 160 connects a X number of terminals such that X=IK/IR.
Often the constant current on each terminal 140A-140Z differs from the desired/ designed constant current. Hence the constant current on terminal 140J may be represented as ID±AIJ. Wherein, ID represents the designed constant current and AIj represents the difference/error on J th terminal.
The error is often caused by one or more circuit parameters. Example parameter that may cause the error on each terminal 140A-HON is described with reference Figure 2 below. Figure 2 is described below with reference to Figure 1 and the description is/are not repeated for the element(s) present in Figure 1 for conciseness.
Figure 2 is an example implementation of multiple constant current sources. Shown there is the reference current source 110 providing a reference current on path/terminal 249/149. The terminal 249 is shown connected to source terminal of transistor 250. The gate terminals of transistors 240A through 240N are connected (together) to the source terminal (249) of transistor 250. The drain terminal of the transistors 240A-240 N and 250 are connected (together) to a fixed potential node such as VDD-

Thus, each transistor 240A through 240N operates in combination with transistor 250 as current mirror as well known in the field of art. Accordingly, each current mirror (transistor 240A with 250, transistor 240B with 250 so on) replicate/mirror a constant current on terminals 270A - 270N respectively. The magnitude of the constant current mirrored on each terminal 270A - 270N is designed/ desired to be equal to the reference current provided on terminal 249.
However, in operation, constant current provided on each terminal 270A-270N differs from the reference current on the terminal 249. One reason for such a difference may be attributed to the difference in the transistors 240A-240N due to process variation. Another reason may be attributed to difference in the lead resistance due to varying distance in the layout from the reference current node.
Manner in which effect of such difference is reduced in one prior embodiment is described below.
3. Prior Technique.
Figure 3 is block diagram of a multiple constant current source with prior calibration and compensation technique. The block diagram is described with reference to Figure 1 for illustration. The block diagram is shown containing reference current source 110, current mirrors 120A-120N, calibration blocks 330A - 330N, error compensation blocks (EC) 340A -340N, connector 160 and circuit portion 180. Each block is described below in further details.
Reference current source 110, current mirrors 120A-120N, connector 160 and circuit portion 180 operate similar to the operation of the

corresponding blocks described with reference to Figure 1. The description is not repeated for conciseness.
Switches 310A-310N enable operation of current sources in two modes - calibration mode and functional mode. In functional mode, switches 310A-3 ION operate to connect terminals 140A-HON respectively to the inputs 320A-320N of the connector 160. In Calibration mode, switches 310A-310N operate to connect terminals 140A-140N respectively to the inputs of the calibration blocks 330A-330N.
Error compensation blocks (EC) 340A-340N generate compensation current and inject/ provide the compensation current to terminals 320A-320N respectively in functional mode. EC 340A-340N may receive an estimate of error from calibration blocks (CAL) 330A-330N.
Calibration blocks (CAL) 330A-330N respectively computes the difference between the reference current and the constant current on the terminals 140A-140N in calibration mode. The computed difference is then provided as estimate of error to the corresponding EC 340A-340N. An example implementation of CAL is illustrated below with reference to Figure 4.
Figure 4 is a block diagram of an example implementation of calibration block (CAL). The block diagram is shown containing reference current source 410, current mirror470, successive approximation registers (SAR) 450, digital to analog converter (DAC) 460, comparator (C) 440, and resistances/loads (R) 420 and 430. Each block is described below with further detail.

Reference current source 410 provides a reference current for calibration. Reference current sources such as 110 may be used with appropriate switching technique for the purpose of calibration. Current mirror 470 provides a constant current by replicating the reference current. Current mirror may represent one of the current mirrors 120A-120N.
Resistor/load 420 and 430 respectively converts reference current (from reference current source 410) and constant current (from current mirror 470) to corresponding voltage values on path 424 and 434. Comparator 440 compares the voltage values on path 424 (corresponding to reference current) and 434 (corresponding to constant current from current mirror 470) and generates a comparison result on path 445.
Successive approximation registers (SAR) 450 receives the comparison results and generate a digital value on path 456 corresponding to the comparison results received successively. Digital to analog converter (DAC) 460 converts the digital value received on path 456 to corresponding analog current on path 463. The analog current on path 463 is provided to the resistor.
Comparator 440, SAR 450, DAC 460 together operate iteratively to reduce the difference between the voltage levels on path 424 and 434 as well known in the field of art. Accordingly, on steady state the current on path 463 represents the difference/error between the reference current (from reference current source 410) and constant current (from current mirror 470). The computed error may be stored or provided to the error compensation block for compensating the error in functional mode.

It may be appreciated that, prior technique error compensation is implemented for each terminal (each current sources). Such an implementation often requires larger area and power. Various aspect of present invention over come at least some of the disadvantages noted.
4. Calibration and Compensation
Figure 5 is a flowchart illustrating calibration and compensation of multiple current sources in one embodiment of the present invention. The flowchart is described with reference to Figure 1 merely for illustration. The extension of the approaches to other image processing systems will be apparent to one skilled in the relevant art by reading the disclosure provided herein, and such implementations are contemplated to be covered by various aspects of the present invention. The flowchart begins in step 501 and control passed to step 510.
In Step 510, a circuit calibrates each constant current source and determines error. Calibration of the constant current may be performed with the desired reference current. For example, constant current on each terminal 140A - 140N may be calibrated independently with the reference current provided from reference current source 110.
In one embodiment, the error/difference determined for each terminal is
stored along with an index. Either terminal 140A-140N or current mirror 120A
-120N may be used as index. For example, lEk represents difference between
the constant current on terminal K and reference current. Accordingly in
calibration mode, errors on terminal 140A-140N may respectively be
represented and stored as IEA, IEB, IEC IEN.

In Step 530, the circuit computes the combined error for a set of current sources. Set of current sources (current mirrors) may be determined based on the magnitude of constant current required to operate circuit portion 180. The set of current sources may be determined statically or dynamically based on the desired operation of the circuit portion.
For example if current mirror 120A, 120B, and 120C represents a set of current sources determined for providing the desired constant current, then the combined error may be computed as lEAgg = IEA+ IEB+ IEC. Wherein, lEAgg represents the combined error corresponding to determined set of current sources 120A, 120B, and 120C.
In Step 540, the circuit generates aggregate compensation current corresponding to combined error computed. The aggregate compensation current is provided to the circuit portion as compensation. The flowchart ends in step 549.
It may be appreciated from the above description that, single error compensation is performed for a set of current sources. Thus required area and power is reduced while performing compensation for multiple constant sources. Flowchart may be implemented using any of the known techniques. An example implementation of flowchart is described below.
5. Example Implementation
Figure 6 is a block diagram illustrating an example implementation of the various aspect of the present invention, the block diagram is shown containing reference current source 610, current mirrors 620A-620N, switches 630A-630N, multiplexer 650, calibration block (CAL) 660, combined error

compensator 670, connector 680 and circuit portion 690. Each block is described below in further detail.
Reference current source 610, current mirrors 620A-620N, switches 630A - 63ON, connector 680 and circuit 690 operate similar to corresponding blocks 110, 120A-120N, 310A-310N, 160 and 180 in Figure 3. However each block is described in brief for continuity.
Reference current source 610 provides a reference constant current IR on path 149. Current mirrors 620A-620N operates as multiple constant current sources. Each current mirror 620A-620N mirrors/replicates a constant current (based on the reference constant current IR) respectively on terminals 640A-640N. The value of constant current on each terminal 640A-640N represents IR±AIJ. Wherein AIj represents the difference/error on J th terminal.
Switches 310A-310N connect terminals 640A-640N to MUX 350 in calibration mode and to connector 680 in functional mode. Connector 680 connects a pre determined set of terminals among the terminals 640A-640N to circuit portion 690.
Calibration Block (CAL) 660 determines difference (error) between the constant current on path 656 (one of the terminal selected among terminals 640A-640N based on the Multiplexer operation) and reference current (example IR). for example, calibration Block (CAL) 660 determines AIj when J th terminal 640J (not shown) is selected by MUX 650. Calibration block may be implemented in any known way. In one embodiment, CAL 660 is implemented similar to the calibration block described with reference to Figure 4.

Multiplexer (MUX) 650 selectively connects one of the terminals 640A-640N to path 656. Alternatively, Multiplexer (MUX) 650 may sequentially connect terminals 640A-640N to path 656. Accordingly, CAL 660 calibrates constant current on each terminal 640A-640N sequential and may store the error along with the index as described with reference to step 510. MUX 650 may maintain the connection for a predetermined time interval based on the CAL 660 operation.
Combined error compensator 670 generate a combined (aggregate) error current corresponding to predetermined set of current mirror that are connected to circuit portion in the functional mode. Combined error compensator 670 may receive individual error value for each current mirror in the set and compute an aggregate error. Alternatively, aggregate error may be directly received from CAL 660. The generated combined error current is provided to circuit portion 690 in functional mode along with the individual constant currents from the predetermined set of current mirror.
As a result, a single calibration circuit and single error compensation circuit may be used to calibrate and compensate for the errors. Alternatively, multiple CAL may be used corresponding to multiple current mirror to reduce the time to calibrate and the determined error may be provided to compensation block.
Approach described above may be used in various environments incorporating multiple current sources. An example environment is described below.
6. Current Steering DAC

Figure 7 is a block diagram illustrating an example current steering DAC. The block diagram is shown containing reference current source 710, current mirrors 720A- 720N switch network 760, resistors 770 and 780, and differential amplifier (DA) 790. Each block is described below in further detail.
Reference current source 710, provide a constant reference current IR. Current mirrors 720A- 720N operate similar to the operation of the corresponding current mirrors 620A - 620N in Figure 6. Number of current mirrors N is selected based on the desired resolution of DAC. For example, incase of an L bit DAC, the number of current mirrors N is selected as N=2^-1. Each current mirror 720A-720N is designed to provide a constant current (respectively on terminals 740A-740N) proportional to lowest significant bit (LSB).
Switch network 760 receives a digital value on path 761 and connects set of H number of constant current terminals to path 767. Switch network 760 selects set of H constant current terminal among N terminals 720A- 720N such that the sum of the constant current from selected set of H terminals is proportional to digital value received on path 761.
Switch network may convert L bit digital value to corresponding thermometric digital representation to determine set of H terminals as well known in the art. For example, a 4 bit digital value (example 1000) may be represented using 16 bit thermometric digital representation (0000000011111111). Further Switch may connect remaining terminals (N-H) to the path 768 to enable differential analog output as described below.

Resistor (R) 770 provides a voltage signal (on path 778) proportional sum of H constant currents received (on path 767) from selected J set of terminals. Similarly, Resistor (R) 780 provides a voltage signal (on path 768) proportional sum of (N-H) constant currents received (on path 767) from (N-H) set of terminals. Accordingly, each voltage provided on path 778 and 768 may be represented in terms of the corresponding set of terminal currents. Accordingly, the voltage provided on path 778 may be represented as;

terminals, AI represents the error/difference between references current IR and the constant current on each of the selected terminal, "other error" represents the error due to other circuit and operational parameters. Some of the reasons for the error AI are as noted in earlier sections. Dynamic switching error due to transient switching time as well known in the art represents an example component of "other error". Similarly, representation of voltage on path 768 is apparent to on skilled in the art by reading the disclosure provided herein. Hence the description is not repeated for conciseness.
Differential amplifier 790 provides an output (on path 799) voltage signal proportional to the difference between the voltages received on terminals 778 and 789, Further in case of single ended (common mode signal) requirement, path 789 may be connected to a reference potential such as ground. Accordingly, analog signal (voltage signal) on path 799 represents the corresponding digital signal received on path 761.

However, it may be appreciated that the analog value on path 799 contain error component as noted in Equations 1 and 2. Maier in which effect of such error may be reduced in an embodiment of the present invention is described below. The embodiment of the invention is described with reference to Figure 7 and 8.
7. Current Steering DAC with Error Compensation
Figure 8 is a block diagram of a current steering L bit DAC in an embodiment of the present invention. The block diagram contains the elements/blocks depicted in Figure 6 and 7 and are referred with same reference numbers. Accordingly, repeated blocks operate similar to the corresponding description provided above.
In addition, the block diagram is shown containing calibration and error computation block 830, memory 870, and auxiliary DAC 850. Each addition block is described below in further detail.
Calibration and error computation block 830 compute 2L possible errors on 767 corresponding to 2L possible digital values. Manner in which in an embodiment of the present invention, calibration and error computation block 830 computes 2^ errors is described below in further detail.
Calibration and error computation block 830 may determine the error ∆Ij (for all values of j from A to N) for each constant current terminal 740A-740N according to step 510. Calibration and error computation block 830 may be implemented using any known technique apparent to one skilled in the art. In one embodiment, calibration and error computation block 830 is implemented according to structure described with reference to Figure 6.

Further with determined individual error AIj, calibration and error computation block 830 may compute (according to step 530) a combined error

operation of switch network 760.

In an alternative embodiment, calibration and error computation block 830 determines the differential error between path 767 and 768 corresponding to a received digital code. For example, if switch network connects H terminals to path 767and N-H terminals to path 768 corresponding to a received digital code, then calibration and error computation block 830 may compute a differentia error (±EIH - ±EIN-H) and may store in memory.
Accordingly, memory 870 extracts the differential error corresponding to the received digital code and provides to auxiliary DAC 850. Auxiliary DAC 850 then generates a corresponding differential error current on terminals 801 and 802. The differential terminals 801 and 802 are connected to path 767 and 768 respectively to compensate the differential error.
Thus, it may be appreciated that, several errors affecting the precision/ accuracy of operation DAC are compensated with reduced complexity.
8. Conclusion
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims I/we claim,
1. Method of providing a constant current from a plurality of current sources,
wherein each current source providing a current output, said method
comprising;
individually calibrating each current source in said plurality of current sources to determine corresponding individual error;
computing a combined error from said individual errors for a set of current sources, wherein said set of current sources comprised in said plurality of current sources; and
generating a combined compensation current corresponding to said combined error.
2. The method of claim 1 further comprising;
adding outputs of said set of current sources with said combined compensation current to generate said constant current; and providing said constant current to a circuit portion.
3. The method of claim 2, wherein said plurality of current sources represents plurality of current mirrors each mirroring a reference current as said current output and wherein said individual error comprise the difference between said reference current and said current output.
4. The method of claim 3, wherein said set of current sources are determined based on a digital input.
5. The method of claim 4 wherein said combined error further comprise a other error wherein said other error is determined based on circuit parameters of said circuit portion.

6. A device operating to providing a constant current to a circuit portion from
a plurality of current sources, wherein each current source in said plurality of
current sources providing a current output, said device comprising;
means for individually calibrating each current source in said plurality of current sources to determine corresponding individual error;
means for computing a combined error from said individual errors for a set of current sources, wherein said set of current sources comprised in said plurality of current sources;
means for generating a combined compensation current corresponding to said combined error; and
means for adding outputs of said set of current sources with said combined compensation current to generate said constant current
7. The device of claim 6, wherein said plurality of current sources represents plurality of current mirrors each mirroring a reference current as said current output and wherein said individual error comprise the difference between said reference current and said current output.
8. The device of claim 7, wherein said set of current sources are determined based on a digital input.
9. The device of claim 8 wherein said combined error further comprise a other error wherein said other error is determined based on circuit parameters of said circuit portion,
10. A digital to analog converter converting an n bit digital code to
corresponding analog signal, comprising;
a plurality of current sources providing current output; a calibrator determining an individual error in each current sources in said plurality of current sources;

a switch network connecting a first set of current sources to a current to voltage converter based on said n bit digital code;
an error estimator estimating a combined error corresponding to said first set of current sources from said individual error; and
a compensator generating a compensation current based on said combined error,
wherein said compensation current is provided as input to said current to voltage converter when said n bit digital code is provided to said switch network.