DESC: TECHNICAL FIELD
[0001] The present disclosure relates to the field of protection relays.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] To further enhance protective control of electrical power distribution systems, intelligent protective relay devices have been developed that are provided with communication capabilities to communicate protective relay data. To date, network communication capabilities have been implemented using data rates of less than 1 Megabits per second using RS-485, RS-232, fiber optic asynchronous serial interfaces, or UART interfaces.
[0004] While the desire for protective relays having communications capabilities has been recognized, there are shortcomings associated with known schemes for communicating protective relay information. For example, known relay communication schemes do not adequately address potential problems relating noise (e.g., due to electromagnetic interference) and communication line faults, and do not adequately provide high speed (greater than 1Mbps) communication capability. Further, the environment in which intelligent protective relays operate is subject to severe conditions, including relatively wide temperature variations, which presents design challenges for potential solutions to the problem of providing a reliable, fault- tolerant, high-speed communications scheme for protective relays.
[0005] To further enhance protective control of electrical power distribution systems, intelligent protective relay devices have been developed that are provided with communication capabilities to communicate protective relay data. To date, network communication capabilities have been implemented using data rates of less than 1 Megabits per second, and using RS-485, RS-232, fiber optic asynchronous serial interfaces, or UART interfaces.
[0006] Protection relay and other protection devices used in industrial and commercial applications use Microprocessor and Micro Controllers to implement protection algorithms, wherein the entire protection of the system to be protected in such relays majorly depends upon redundancy of the Microcontroller and/or the MicroProcessor used. Any kind of hardware or software failure will inhibit such numerical relay operation.
[0007] There is therefore a need in the art for a method and an architecture/system that reduces failure rate of protection relays by reducing dependency on the single Micro controller or Microprocessor.
[0008] All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
[0009] In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0010] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0011] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0012] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all Markush groups used in the appended claims.

OBJECTS OF THE INVENTION
[0013] An object of the present disclosure is to provide a single protection relay having a master microcontroller and a slave microcontroller to reduce the probability of relay failure by 50%.
[0014] An object of the present disclosure is to provide a single protection relay having a master microcontroller and a slave microcontroller to enable runtime upgradation of firmware without system shutdown due to availability of two different systems running concurrently.
[0015] An object of the present disclosure is to provide a single protection relay having a master microcontroller and a slave microcontroller to enable the slave microcontroller to take over the functioning of the relay when the master microcontroller is not working properly.

SUMMARY
[0016] The present disclosure relates to the field of protection relays. In an embodiment, the present disclosure relates to a protection relay comprising a master microcontroller that is configured to operate the protection relay by default, and a slave microcontroller that is operatively coupled with the master microcontroller, wherein the slave microcontroller monitors signal pulses generated by the master microcontroller, and overtakes as a new master microcontroller when the master microcontroller misses a defined number of signal pulses.
[0017] In an aspect, the master microcontroller and/or the slave microcontroller can be configured to execute code for protection, and wherein inputs of the master microcontroller and the slave microcontroller have common parallel digital and analog inputs. In another aspect, the master microcontroller and the slave microcontroller can have a signal pulse line between them to synchronize signals.
[0018] In another aspect, output the master microcontroller can be connected to a first tri-state buffer, and wherein output the slave microcontroller can be connected to a second tri-state buffer. In yet another aspect, the first tri-state buffer and the second tri-state buffer can be connected to a common output terminal. In yet another aspect, output enable signal of the first tri-state buffer and the second tri-state buffer are controlled by the slave microcontroller.
[0019] According to one embodiment, clocks of the master microcontroller and of the slave microcontroller can be controlled by a common oscillator. Furthermore, at least one of the master microcontroller and the slave microcontroller can have a temporary memory to maintain local data set. In another aspect, the master microcontroller can generate a signal pulse clock at periodic rate by toggling its output pin. In another aspect, overtaking of the slave microcontroller as the new master microcontroller can include the step of overriding output bus of the master microcontroller by asserting a bus control signal to disable output from the master microcontroller.
[0020] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components

BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1 illustrates an exemplary architecture of the proposed redundancy design for protection relay in accordance with an embodiment of the present disclosure.
[0022] FIG. 2 illustrates an exemplary flow diagram of the working of the master Microcontroller in accordance with an embodiment of the present disclosure.
[0023] FIG. 3 illustrates an exemplary flow diagram of the working of the slave Microcontroller when the same becomes the master Microcontroller in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0024] As employed herein, the term “number” shall mean one or an integer greater than one (i.e., a plurality).
[0025] As employed herein, the term “processor” means a programmable analog and/or digital device that can store, retrieve, and process data; a computer; a workstation; a personal computer; a microprocessor; a microcontroller; a microcomputer; a central processing unit; a mainframe computer; a mini-computer; a server; a networked processor; or any suitable processing device or apparatus.
[0026] As employed herein, the terms “protection relay” or “protective relay” can include, for example and without limitation, a number of current and/or voltage sensors, a processor, and a control circuit to open and close a contactor. The relay and/or current and/or voltage sensors can be part of or be separate from a contactor.
[0027] As employed herein, the term “switchgear” includes, for example and without limitation, an assembly of one or more motor starters that can also contain circuit breakers and fused switches.
[0028] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0029] Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[0030] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0031] The present disclosure relates to the field of protection relays. In an embodiment, the present disclosure relates to a protection relay comprising a master microcontroller that is configured to operate the protection relay by default, and a slave microcontroller that is operatively coupled with the master microcontroller, wherein the slave microcontroller monitors signal pulses generated by the master microcontroller, and overtakes as a new master microcontroller when the master microcontroller misses a defined number of signal pulses.
[0032] In an aspect, the master microcontroller and/or the slave microcontroller can be configured to execute code for protection, and wherein inputs of the master microcontroller and the slave microcontroller have common parallel digital and analog inputs. In another aspect, the master microcontroller and the slave microcontroller can have a signal pulse line between them to synchronize signals.
[0033] In another aspect, output the master microcontroller can be connected to a first tri-state buffer, and wherein output the slave microcontroller can be connected to a second tri-state buffer. In yet another aspect, the first tri-state buffer and the second tri-state buffer can be connected to a common output terminal. In yet another aspect, output enable signal of the first tri-state buffer and the second tri-state buffer are controlled by the slave microcontroller.
[0034] According to one embodiment, clocks of the master microcontroller and of the slave microcontroller can be controlled by a common oscillator. Furthermore, at least one of the master microcontroller and the slave microcontroller can have a temporary memory to maintain local data set. In another aspect, the master microcontroller can generate a signal pulse clock at periodic rate by toggling its output pin. In another aspect, overtaking of the slave microcontroller as the new master microcontroller can include the step of overriding output bus of the master microcontroller by asserting a bus control signal to disable output from the master microcontroller.
[0035] FIG. 1 illustrates an exemplary architecture 100 of the proposed redundancy design for protection relay in accordance with an embodiment of the present disclosure. In an aspect of the present disclosure, the protection relay can be configured to include a second Micro controller in slave mode in conjunction with a first Microcontroller that acts as the master controller for the protection relay. As shown in FIG. 1, first Microcontroller 102 can be configured as the Master Controller, and second Microcontroller 104 can be configured as the Slave Controller, wherein both the master 102 and the slave 104 microcontrollers can execute code for protection having same analog and digital input.
[0036] According to one embodiment, signal pulse line 106 can include a synchronizing signal between the master 102 and the slave 104 microcontrollers. According to another embodiment, unidirectional analog (from 110) and digital input signals (from 108) can be connected in parallel to inputs of both master 102 and slave 104 microcontrollers.
[0037] In another embodiment, all unidirectional output can be connected to output terminal via tristate buffer. In an aspect, unidirectional output of master microcontroller 102 can be connected to tristate buffer (EN1) 112, and unidirectional output of slave microcontroller 104 can be connected to tristate buffer (EN2) 114, both having N output channels. In another aspect, output enable signal of both tri-state buffers112 and 114 can be controlled by the slave microcontroller 104.
[0038] In yet another aspect, clock of both the microcontrollers 102 and 104 can be provided by oscillator 116.Both the microcontrollers 102 and 104 can also have their own separate temporary storage memory 118 and 120 respectively to maintain local set of data. In yet another aspect, in bidirectional lines, output 122 can be controlled by slave microcontroller 104 and master microcontroller 102 through the temporary storage memory 120.
[0039] In yet another embodiment, both the master microcontroller 102 and the slave microcontroller 104 can observe the same set of analog and digital inputs108/110 to evaluate the output 122, wherein the slave microcontroller 104 can observe pulse signals generated by the master microcontroller 102. In another aspect, the master microcontroller 102 can generate signal pulse clock at periodic rate by toggling its output pin. Any hardware or software failures can cease the master microcontroller 102 to generate the heart bit signal, in which case the slave microcontroller 104 can override the output bus by asserting bus control signal to disable output from the master microcontroller 102 in the event of missing pulse signal. As both the controllers 102/104 are synchronized by a common clock and system synchronization pulse, override between the master microcontroller 102 and the slave microcontroller 104 can be done in minimum time without compromising protection functionality. Furthermore, in order to have software redundancy, measurement and protection algorithm execution sequence can be altered with different configurations so that probability firmware failure at same time is reduced.
[0040] In an aspect, instead of using two or more protection devices in combination to increase redundancy of protection system, a single relay as proposed in the present disclosure can be used to do the same. By using the proposed architecture, the probability of relay failure is reduced by at least 50%. Furthermore, having different protection and measurement algorithms on two different controllers reduces the probability of firmware failure. Runtime up-gradation of the firmware without system shutdown can be possible due to availability of two different systems running concurrently.
[0041] FIG. 2 illustrates an exemplary flow diagram 200 of working of the master Microcontroller in accordance with an embodiment of the present disclosure. As shown, at step 202, the relay can be initialized and at step 204, it can be evaluated as to whether the signal pulse is missing, wherein at step 206, in case the signal pulse is not missing, master microcontroller can be enabled and activated, and at 208, measurement can be done by the master microcontroller, followed by protection at step 210, and updation of output at step 212, and finally storing of data at step 214. On the other hand, in case the signal pulse is missing, the master microcontroller output can be disabled at step 216, and slave microcontroller output can be enabled at 218. An alarm can then optionally be raised at step 220 before the method returns back to step 208.
[0042] FIG. 3 illustrates an exemplary flow diagram 300 of working of the slave Microcontroller when the same becomes the master Microcontroller in accordance with an embodiment of the present disclosure. When the slave microcontroller becomes the new master microcontroller, the system can be initialized at 302 and the signal pin can be toggled at 304. At step 306, the new master microcontroller (prior salve microcontroller) can undertake measurement, followed by undertaking protection at 308, and then updating the output at step 310, wherein the data can finally be stored at step 312 to then finally toggle the signal pin 314.
[0043] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0044] The present disclosure provides a single protection relay having a master microcontroller and a slave microcontroller to reduce the probability of relay failure by 50%.
[0045] The present disclosure provides a single protection relay having a master microcontroller and a slave microcontroller to enable runtime upgradation of firmware without system shutdown due to availability of two different systems running concurrently.
[0046] The present disclosure provides a single protection relay having a master microcontroller and a slave microcontroller to enable the slave microcontroller to take over the functioning of the relay when the master microcontroller is not working properly.
,CLAIMS:1. A protection relay for distribution equipment for a power distribution system comprising:
a master microcontroller configured to operate the protection relay by default; and
a slave microcontroller operatively coupled with the master microcontroller, wherein the slave microcontroller monitors signal pulses generated by the master microcontroller, and overtakes as a new master microcontroller when the master microcontroller misses a defined number of signal pulses.

2. The protection relay of claim 1, wherein the master microcontroller and/or the slave microcontroller are configured to execute code for protection, and wherein inputs of the master microcontroller and the slave microcontroller have common parallel digital and analog inputs.

3. The protection relay of claim 1, wherein the master microcontroller and the slave microcontroller have a signal pulse line between them to synchronize signals.

4. The protection relay of claim 1, wherein output the master microcontroller is connected to a first tri-state buffer, and wherein output the slave microcontroller is connected to a second tri-state buffer.

5. The protection relay of claim 4, wherein the first tri-state buffer and the second tri-state buffer are connected to a common output terminal.

6. The protection relay of claim 4, wherein output enable signal of the first tri-state buffer and the second tri-state buffer are controlled by the slave microcontroller.

7. The protection relay of claim 1, wherein clocks of the master microcontroller and of the slave microcontroller are controlled by an oscillator.

8. The protection relay of claim 1, wherein at least one of the master microcontroller and the slave microcontroller has a temporary memory to maintain local data set.
9. The protection relay of claim 1, wherein the master microcontroller generates a signal pulse clock at periodic rate by toggling its output pin.

10. The protection relay of claim 1, wherein overtaking of the slave microcontroller as the new master microcontroller comprises overriding output bus by asserting a bus control signal to disable output from the master microcontroller.

11. A method of controlling a protection relay, comprising:
initializing the protection relay having a master microcontroller and a slave microcontroller operatively coupled with each other;
enabling the master microcontroller to measure and protect a circuit breaker;
determining if the master microcontroller has missed a defined number of signal pulses; and
configuring the slave microcontroller to act as the new master microcontroller if it is determined that the master microcontroller has missed a defined number of signal pulses.

12. The method of claim 11, wherein the master microcontroller continues to operate the protection relay if it is determined that the master microcontroller has not missed a defined number of signal pulses.