RESISTANCE MULTIPLICATION CIRCUIT
Field of invention
This invention relates to a field of semiconductor integrated circuits, and more specifically to a resistance multiplication circuit for multiplying the resistance value at a node, so that a high-value resistance can be provided in less area with low / or zero DC currents through the realized resistor.
Background of the invention
In integrated circuit designs, a high-value resistance is often needed in various applications, such as in performing filtering functions, in realizing very low frequency poles, etc. Directly creating such a high-value resistance element may be either unfeasible or undesirable due to various factors, such as performance and/ or size of such a resistance element. For example, one conventional technique for realizing high-value resistances in an integrated circuit includes using a silicon resistance. The silicon resistance can be a base region of an NPN bipolar transistor to form the resistance element. The NPN base region offers sufficient accuracy with good thermal and voltage coefficients, but for a large resistance value a very large area is required. For instance, a typical sheet resistance of the base region is 2 k-ohm / square, so to obtain a 500 k-ohm resistor it will require 250 squares. Not only is the area consumed by 250 squares significant, but also the capacitance associated with the resulting resistance element is undesirably large, causing significant degradation in the element's frequency response
Another conventional technique for realizing high-value resistances in the integrated circuit involves using a weakly-enhanced, long-channel length MOS transistor. Although such resistance element may provide a more compact realization than the previous technique, but the resistance value will vary more widely over process conditions and temperature variations.
The conventional techniques for providing a high resistance value in the integrated circuit are not preferred, as these either require large silicon area to implement or the resulting resistance element exhibits large resistance variations due to voltage variations.
Therefore, a technique of resistance realization is needed in which the resistance realized is a certain multiple of a passive resistance. The technique can be used to realize very high values of resistance without requiring a large area provided the voltage drop across the resistance is small (a few milivolts) or zero in steady state.
Summary of the invention
It is an object of the present invention to provide a resistance multiplication circuit capable of providing a high resistance value using a small and a cost effective structure.
It is another object of the present invention to provide a resistance multiplication circuit realizing a high resistance value for very low / zero dc currents through the realized resistor.
To achieve said objectives, the present invention provides a resistance multiplication circuit coupled to a first node for providing a high resistance value, the circuit comprising:
a resistor coupled between the first node and a second node for providing a potential drop to generate a specific current;
an NMOS transistor having its first current handling terminal connected to a third node, and its second current handling terminal connected to the first node with its gate connected to a fourth node for providing the high resistance value; and
an operational amplifier (op-amp) having a first input connected to the second node, a second input connected to the third node, and an output connected to the gate of
the NMOS transistor through the fourth node for biasing the NMOS transistor, such that a potential drop across the NMOS transistor and the resistor is equal
, wherein the resistance multiplication circuit compares a voltage drop across the resistor for the specific current, and forces a fraction of the specific current through the NMOS transistor with same voltage drop, such that a resistance of the NMOS transistor is multiplied by an inverse of the fraction to provide the high resistance value.
Further, the present invention provides a resistance multiplication circuit coupled to a first node for providing a high resistance value, the circuit comprising:
a resistor coupled between the first node and a second node for providing a potential drop to generate a specific current;
a PMOS transistor having its first current handling terminal connected to a third node, and its second current handling terminal connected to the first node with its gate connected to a fourth node for providing the high resistance value; and
an operational amplifier (op-amp) having a first input connected to the second node, a second input connected to the third node, and an output connected to the gate of the PMOS transistor through the fourth node for biasing the PMOS transistor, such that a potential drop across the PMOS transistor and the resistor is equal
, wherein the resistance multiplication circuit compares a voltage drop across the resistor for the specific current, and forces a fraction of the specific current through the PMOS transistor with same voltage drop, such that a resistance of the PMOS transistor is multiplied by an inverse of the fraction to provide the high resistance value.
Further, the present invention provides a method for providing a high resistance value through a resistance multiplication circuit at a first node, the method comprising the steps of:
coupling a resistor between the first node and a second node to provide a potential drop for generating a specific current;
coupling a MOSFET having its first current handling terminal connected to a third node, and its second current handling terminal connected to the first node with its gate connected to a fourth node for providing the high resistance value; and
coupling an operational amplifier (op-amp) having a first input connected to the second node, a second input connected to the third node, and an output connected to the gate of the MOSFET transistor through the fourth node to bias the MOSFET transistor, such that a potential drop across the MOSFET transistor and the resistor is equal
, wherein comparing a voltage drop across the resistor for the specific current, and forcing a fraction of the specific current through the MOSFET transistor with same voltage drop, such that a resistance of the MOSFET transistor is multiplied by an inverse of the fraction.
Brief Description of the drawings
The present invention is described with the help of accompanying drawings.
FIGURE 1 is a circuit diagram of a resistance multiplication circuit according to the present invention.
FIGURE 2 is a circuit diagram of a resistance multiplication circuit according to a first embodiment of the present invention.
FIGURE 3 illustrates a circuit incorporating a resistance multiplier circuit according to one embodiment of the present.
FIGURE 4 illustrates a circuit incorporating a resistance multiplier circuit according to another embodiment of the present.
FIGURE 5 illustrates a flow diagram of a method for providing a high resistance value through a resistance multiplier circuit at a first node according to the present invention.
Detailed Description of the Invention
The present invention provides a resistance multiplication circuit coupled at a first node to provide a high resistance value without requiring a large area. In this manner, a high-value resistance can be provided.in an integrated circuit by using a comparatively small and a cost effective structure. In an embodiment of the present invention, the resistance multiplication circuit includes a resistor, a MOSFET, and an operational amplifier (op-amp). The resistor is coupled between a first node and a second node to generate a specific current. The MOSFET having its first current handling terminal connected to a third node, and its second current handling terminal connected to the first node with its gate connected to a fourth node for providing large resistance values. The operational amplifier (op-amp) having a first input connected to the second node, a second input connected to the third node, and an output connected to the gate of the MOSFET through the fourth node for biasing the MOSFET, such that a potential drop across the MOSFET and the resistor is equal.
The resistance multiplication circuit of the present invention offers many advantages. First, the resistance multiplication circuit includes a resistor, a MOSFET, and an operational amplifier, which requires less silicon area to implement, while providing for very high resistance'values. Second, the circuit can achieve stability over voltage variations. Lastly, because the circuit can achieve large resistance in a small area, the parasitic capacitance of the resulting structure is much lower than that of other conventional structures.
The basic operating principle of the resistance multiplication circuit is to compare a voltage drop across a known resistor for a given current and force a fraction of that current through a MOSFET working in linear region, with the same voltage drop. Then the resistance of the MOSFET is multiplied by the inverse of that fraction.
FIGURE 1 is a schematic diagram of a resistance multiplication circuit 100 in accordance with an embodiment of the present invention. FIGURE 1 illustrates the principle using an NMOS transistor. A current forced through the resistor 102 is 'n' times the current through the NMOS transistor 104. The operational amplifier 106 biases the NMOS transistor 104 so that the voltage drop across the NMOS transistor 104 is the same as that of the resistor 102. It is known that if a MOSFET is working in a linear region, then the current to voltage (drain to source) is roughly constant for small voltage drops. Hence, if the voltage dropped across the resistor 102 is a few millivolts (or tens of millivolts), then the NMOS transistor 104 resistance is roughly
R-realized = n * R, where n is the fraction value.
The structural circuit of the resistance multiplication circuit 100 is described in the following paragraphs.
The resistance multiplication circuit 100 includes a resistor 102, an NMOS transistor 104, and an operational amplifier 106. The resistor 102 is coupled between a first node (NODE 1) and a second node (NODE 2) for providing a potential drop to generate a specific current. The NMOS transistor 104 having its first current handling terminal connected to a third node (NODE 3), and its second current handling terminal connected to the first node (NODE 1) with its gate connected to a fourth node (NODE 4) for providing said high resistance value. The operational amplifier (op-amp) 106 having a first input connected to the second node (NODE 2), a second input connected to the third node (NODE 3), and an output connected to the gate of the NMOS transistor 104 through the fourth node (NODE 4) for biasing the NMOS transistor 104, such that a potential
across the NMOS transistor 104 and the resistor 102 is equal. The NMOS transistor 104 works in a linear region mode.
Let us assume that we need to realize a resistor at some node D in FIGURE 3, which is at a voltage V in a steady state condition. As shown in FIGURE 1, the node X is ensured to be at the same voltage V. This can be realized as necessary. The node X may be either at negative supply or may be connected to the output of a unity gain buffer or may be connected to the drain of a diode connected NMOS transistor, as necessary. One skilled in the art will know how to hold the voltage at node X at the desired level, depending on the circuitry involved at node D.
The NMOS in FIGURE 1 is realized as a parallel connection of 'm' transistors of dimension 'w/P. The gate node O (NODE 4) is automatically biased by the operational amplifier to the required voltage. Now if an NMOS transistor of dimension 'w/l is connected at node D with its gate biased by node O, and if the voltage drop across the mentioned transistor is a few millivolts (the current is very small or zero), then the resistance of this transistor at node D would be
R-realized = n*m*R.
So the resistance multiplication would be achieved at the desired node D. Also, if the dc current through this transistor needs to be zero, then we can connect 'k' transistors of dimension 'wA' in series as shown in FIGURE 3. Then the resistance realized at node D is approximately
R-realized = n*m*k*R
In FIGURE 3 the value of 'k' is 3.
FIGURE 2 is a schematic diagram of a resistance multiplication circuit 200 in accordance with another embodiment of the present invention. FIGURE 2 illustrates the
principle using a PMOS transistor. Here the voltage drop across the PMOS transistor is forced to be equal to that of the resistor R. But since the current is 'n' times lower so its resistance is R-pmos = n*R
The resistance multiplication circuit 200 includes a resistor 202, a PMOS transistor 204, and an operational amplifier 206. The resistor 202 is coupled between a first node (NODE 1) and a second node (NODE 2) for providing a potential drop to generate a specific current. The PMOS transistor 204 having its first current handling terminal connected to a third node (NODE 3), and its second current handling terminal connected to the first node (NODE 1) with its gate connected to a fourth node (NODE 4) for providing the high resistance value. The operational amplifier (op-amp) 206 having a first input connected to the second node (NODE 2), a second input connected to the third node (NODE 3), and an output connected to the gate of the PMOS transistor 204 through the fourth node (NODE 4) for biasing the PMOS transistor 204, such that a potential drop across the PMOS transistor 204 and the resistor 202 is equal. The first node X (NODE 1) is held at the desired potential v by some circuitry, depending on the actual circuitry at node D. The first node (NODE 1) could be connected to one of a positive supply voltage, an output of a unity gain buffer, and a drain of a diode connected PMOS transistor, etc. The PMOS transistor 204 works in a linear region mode.
Now if one such PMOS transistor is connected to the node D (FIGURE 4), with its gate connected to node O (FIGURE 2), then the resistance realized would be R-realized = n*m*R
For circuits where the dc current through the desired resistor, at node D is zero, 'k' such transistors can be connected in series so that the resistance realized would be R-realized = n*m*k*R.
In this way a large multiplication factor can be achieved and mega-ohms of resistance can be easily achieved.
FIGURE 5 illustrates a flow diagram of a method for providing a high resistance value through a resistance multiplier circuit at a first node according to the present invention. At step 502, a resistor is coupled between the first node and a second node to provide a potential drop for generating a specific current. At step 504, a MOSFET is coupled having its first current handling terminal connected to a third node, and its second current handling terminal connected to the first node with its gate connected to a fourth node for providing said high resistance value. At step 506, an operational amplifier is coupled having a first input connected to the second node, a second input connected to the third node, and an output connected to the gate of the MOSFET transistor through the fourth node to bias the MOSFET transistor, such that a potential drop across said MOSFET transistor and the resister is equal.
The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is defined by the appended claims.

We claim:
1. A resistance multiplication circuit coupled to a first node for providing a high
resistance value, said circuit comprising:
a resistor coupled between the first node and a second node for providing a potential drop to generate a specific current;
an NMOS transistor having its first current handling terminal connected to a third node, and its second current handling terminal connected to the first node with its gate connected to a fourth node for providing said high resistance value; and
an operational amplifier (op-amp) having a first input connected to the second node, a second input connected to the third node, and an output connected to the gate of said NMOS transistor through the fourth node for biasing the NMOS transistor, such that a potential drop across said NMOS transistor and said resistor is equal
, wherein said resistance multiplication circuit compares a voltage drop across the resistor for the specific current, and forces a fraction of the specific current through the NMOS transistor with said voltage drop, such that a resistance of said NMOS transistor is multiplied by an inverse of said fraction to provide the high resistance value.
2. The resistance multiplication circuit as claimed in claim 1, wherein said first node
is connected to a group of circuit comprising a negative supply voltage circuit, an
output of a unity gain buffer circuit, and a drain of a diode connected NMOS
transistor circuit.
3. The resistance multiplication circuit as claimed in claim 1, wherein said second
node and said third node are connected to a first supply voltage.
4. The resistance multiplication circuit as claimed in claim 1, wherein said first node
is connected to a second supply voltage.
5. The resistance multiplication circuit as claimed in claim 1, wherein said NMOS
transistor works in a linear region mode. 6. A resistance multiplication circuit coupled to a first node for providing a high
resistance value, said circuit comprising:
a resistor coupled between the first node and a second node for providing a potential drop to generate a specific current;
a PMOS transistor having its first current handling terminal connected to a third node, and its second current handling terminal connected to the first node with its gate connected to a fourth node for providing said high resistance value; and
an operational amplifier (op-amp) having a first input connected to the second node, a second input connected to the third node, and an output connected to the gate of said PMOS transistor through the fourth node for biasing the PMOS transistor, such that a potential drop across said PMOS transistor and said resistor is equal
, wherein said resistance multiplication circuit compares a voltage drop across the resistor for the specific current, and forces a fraction of the specific current through the PMOS transistor with said voltage drop, such that a resistance of said PMOS transistor is multiplied by an inverse of said fraction to provide the high resistance value. 7 The resistance multiplication circuit as claimed in claim 6, wherein said first node is connected to a group of circuit comprising a positive supply voltage circuit, an output of a unity gain buffer circuit, and a drain of a diode connected PMOS transistor circuit.
8. The resistance multiplication circuit as claimed in claim 6, wherein said second
node and said third node are connected to a ground voltage.
9. The resistance multiplication circuit as claimed in claim 1, wherein said first node
is connected to a supply voltage.
10. A method for providing a high resistance value through a resistance multiplication
circuit at a first node, said method comprising the steps of:
coupling a resistor between the first node and a second node to provide a potential drop for generating a specific current;
coupling a MOSFET having its first current handling terminal connected to a third node, and its second current handling terminal connected to the first node with its gate connected to a fourth node for providing said high resistance value; and
coupling an operational amplifier (op-amp) having a first input connected to the second node, a second input connected to the third node, and an output connected to the gate of said MOSFET transistor through the fourth node to bias the MOSFET transistor, such that a potential drop across said MOSFET transistor and said resistor is equal
, wherein comparing a voltage drop across the resistor for the specific current, and forcing a fraction of the specific current through the MOSFET transistor with same voltage drop, such that a resistance of said MOSFET
transistor is multiplied by an inverse of said fraction to provide the high resistance value.
11. The method as claimed in claim 10, wherein said MOSFET is selected from one of a NMOS transistor and a PMOS transistor.
12. The method as claimed in claim 10, wherein said MOSFET works in a linear
region.
13. A resistance multiplication circuit coupled to a first node for providing a high
resistance value substantially as herein described with reference to the
accompanying drawings.
14. A method for providing a high resistance value through a resistance multiplication
circuit at a first node substantially as herein described with reference to the
accompanying drawings.