Description
BACKGROUND
1. Field of the Invention
The present invention relates generally to design of an integrated circuit, particularly to design of a reuse circuit enabling efficient testing.
2. Related Art
A reuse circuit, in general, refers to an electric/electronic circuit portion that may be incorporated in multiple integrated circuits that are functionally different. Due to use of the reuse circuit in the design of a new integrated circuit, design time and resources (such as manpower) requirement may be reduced.
Reuse circuits are often constructed under different design situations. In one situation, a portion of circuit from the current design may be identified as reusable and archived for future use as reuse circuit. On the other hand, circuits may be designed to perform standard operations/functions (for example Fourier transform, signal processing) and provided as reuse circuit.
Integrated circuit is often designed to operate in test mode and functional mode. In functional mode, components of the integrated circuit are connected to perform desired operation according to the design. While in test mode components are connected to test integrated circuit. For example, in test mode, the components are connected as scan chains as well known in the field of art.

Accordingly, to enable the dual mode of operation, an additional components and connections (together referred to as test enable hardware) are added to the original design of the integrated circuit. Test enable hardware is designed considering the components and relative connectivity in the functional mode (design). In case of an integrated circuit incorporating a reuse circuit, test enable hardware is designed and implemented for entire integrated circuit including the reuse circuit portion. Time and resources required to design test enable hardware may lead to increase in the time to market and cost of the product.
BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described with reference to the following
accompanying drawings.
Figure 1 is a block diagram of an example integrated circuit implemented according to prior approach.
Figure 2 is block diagram of an integrated circuit illustrating the manner in which test enable hardware is implemented according to a prior approach.
Figure 3A is a flowchart illustrating the manner in which a integrated circuit is designed according to present invention.
Figure 3B is a flowchart illustrating the manner in which a reuse circuit of the present invention may be incorporated in the development of a integrated circuit according to another aspect of the invention.
Figure 4 is a block diagram of an integrated circuit implemented according to present invention.
Figure 5 is a block diagram of an integrated circuit implemented by incorporating the reuse circuit of the present invention.

In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit (s) in the corresponding reference number.
DETAILED DESCRIPTION 1. Overview
An integrated circuit design technique provided according to an aspect of the present invention determines a reusable circuit portion within the integrated circuit. A first test enable hardware is added to determined reuse portion enabling the independent testing of reusable circuit portion. A second test enable hardware is added to the remaining portion of the integrated circuit enabling the testing of remaining portion of the Integrated circuit.
A reuse circuit provided according to another aspect of present invention includes the test enable hardware enabling testing of the reuse circuit. Thus, time and resources requirement is reduced when the reuse circuit of the present invention is incorporated into the design of new integrated circuit.
Yet another aspect of the present invention, the reuse circuit is provided with a test port to enable interface/inter connectivity of between test enable hardware of the reuse circuit and the test enable hardware of the remaining portion of the integrated circuit.
Several aspects of the invention are described below with reference to examples for illustration. It should be understood that numerous specific

details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details, or with other methods, etc. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the features of the invention.
2. Example Environment
Figure 1 is a block diagram of an example integrated circuit implemented according to prior approach. Integrated circuit 100 is shown containing reusable circuit 190 and other circuit portion 109. Reusable circuit portion 190 is shown further comprising registers 110, memory 120, combinational logic 130, sequential logic 140, IP core 160, processor 150 and connectivity 101. Similarly, other circuit portion 109 is shown comprising analog circuit 170, combinational logic 180, sequential logic 185, processor 175 and connectivity 102, Each block is described below in further detail.
Registers 110 temporarily stores binary data is an array of data storage elements (such as flip-flops, SRAM cells). Size of the array is determined based on the application. For example, the size of the array may be selected as 32, 64, 128 etc. Register 110 may be used for temporally storing data while a desired operation is performed on the data.
Memory 120 stores block of data (data relatively larger in size) in a data storage space. Memory 120 may be implemented using any of the known technology such as volatile, non volatile etc. Memory 120 often stores larger data compared to the registers.

Combinational logics 130 and 180 perform logical operations on the data. The combinational circuit may also operate to provide desired delay on the data path. Combinational logic 130 and 180 may be implemented using various logic gates such as NAND, NOR etc.
Sequential logics 140 and 185 perform sequential operation controlled by a clock signal. Sequential logics may be implanted as part of various clock based operations such as shifting operation, counting operation etc.
Processor 150 and 175 process the data from memory and may coordinate the operations of the other blocks. Analog circuit 170 process and propagates analog signals such as RF signals, audio signals from the sensors etc.
IP core 160 performs specific function (such as computing Fast Fourier transform) or may process the data adapting a suitable technique (for example, DSP core). IP core 160 represents a reuse circuit incorporated into the Integrated circuit 100. IP core 160 provides a interface pins (ports) for extemal interface.
Connectivity 101 connects (elements within the block) and interconnects (elements of different blocks) the elements of registers 110, memory 120, combinational logic 130, sequential logic 140, IP core 160 and processor 150 according to desired design. Accordingly, blocks (elements of the blocks) 110, 120, 130, 140, 150 and 160 together (reuse circuit 190) operate to perform one sub function of integrated circuit 100.

Similarly, connectivity 102 connects and interconnects the elements of combinational logics 180, sequential logic 185, analog circuit 170, and processor 175 according the design. Accordingly, blocks 180, 185, 170 and 175 together (other portion 109) operate to perform another sub function of the integrated circuit.
The two sub functional blocks (190 and 109) are integrated to perform a desired (main function of IC 100) operation by designing an interconnection between the functional blocks. In one embodiment, an extemal interface 195 is provided to reuse circuit 190. Accordingly, connectivity 102 is also designed to connect reuse circuit 190 to the other circuit portion 109.
Reuse circuit 190 is archived for reuse in the future design of integrated circuit or may be provided as IP core for implementation in other integrated circuit. Various disadvantages of prior reuse circuit are illustrated below.
Often to enable testing of integrated circuit, test enable hardware is implemented in the integrated circuit. The manner in which the test enable hardware is implemented according to a prior approach is described below with reference Figure 1 and Figure 2.
3. Prior Test Enable Hardware Implementation.
Figure 2 is block diagram of an integrated circuit illustrating the manner in which test enable hardware is implemented according to a prior approach. Integrated circuit 200 is shown containing test enable hardware 250 and blocks of integrated circuit 100 (namely registers 110, memory 120,

combinational logic 130, sequential logic 140, IP core 160, processor 150 and connectivity 101 in reuse circuit 190 and analog circuit 170, combinational logic 180, sequential logic 185, processor 175 and connectivity 102 in other circuit portion 102). Accordingly, the respective blocks operate similar to the descriptions provided above with reference to Figure 1.
The test enable hardware facilitates testing of integrated circuit 200. Test enable hardware 250 shown containing test elements 260 such as multiplexer and test mode connection 230. The test mode connection cormects input/output of test elements to the elements of the blocks registers 110, memory 120, combinational logic 130, sequential logic 140, IP core 160, processor 150 and connectivity 101 in reuse circuit 190 and analog circuit 170, combinational logic 180, sequential logic 185, processor 175 and connectivity 102 in other circuit portion 102. test mode connection 230 and test elements are designed based on the test requirement using any of the known technique.
For example, in order to test combinational logics in the integrated circuit 200, test enable hardware is implemented to enable sequential scan chain (scan based) testing. Accordingly, test mode connection connects selected sequential laments comprised in integrated circuit 200, as a chain to load/unload a test/result vector. Accordingly test elements 260 (multiplexers) are built for each selected sequential elements to enable the test mode (as scan chain) or functional mode (operation as per the design) connection.
Similarly in case of memory test requirement, the test enable hardware 250 is designed to perform memory test according to BIST scheme as well known in the field of art.

It may appreciate that, test enable hardware 250 is implemented by considering the details of the individual blocks within reuse circuit 190. As a result, the resource and time to design the test enable hardware is repeated for the reuse circuit 190 every time the reuse circuit 190 is implemented in the new design.
Various aspect of present invention at least reduces some of the disadvantages noted above. Accordingly, the invention is described below with reference to Figure 3.
4. Reuse Circuit Design.
Figure 3A is a flowchart illustrating the manner in which an integrated circuit is designed according to present invention. The flow chart begins in step 301 and control passes to step 310.
In Step 310, design process determines/selects a circuit portion of an integrated circuit as reusable. The determination may be made at various design stages of an integrated circuit. For example, the designer may determine the reuse portion of the circuit after generation of netlist and before layout stage or any other stage of design that is suitable for implementing the test enable hardware.
In Step 320, the design process adds test enable hardware to determined circuit portion enabling testing of the determined portion. Test enable hardware may be implemented to test memory operation, combinational logics, etc. Test enable hardware may be implemented to perform desired

testing using any of the known/standard techniques such as BIST, Sequential scan etc.,
In Step 330, the design process provides determined circuit portion with added test enable hardware as reuse circuit. A functional interface and a test interface are added to reuse circuit. The functional interface enables integration of reuse circuit with other portion in the functional mode. The test interface enable integration of reuse circuit in the test mode. The functional interface and test interface may be provided using number of leads or ports. The flow chart ends in step 349.
The reuse circuit with functional and test interface may be archived for the purpose of reusing in the development of other integrated circuit or may provided as IP core. Further step 310 enable selection of portion of circuit that has been completed for parallel development of test enable hardware.
The manner in which the reuse circuit of present invention may be incorporated in the design of a integrated circuit according to another aspect of present invention is described below with reference to figure 3B,
Figure 3B is a flowchart illustrating the manner in which a reuse circuit of the present invention may be incorporated in the development of a integrated circuit according to another aspect of the invention. The flow chart begins in step 351 and control passes to step 360.
In Step 360, design process receives reuse circuit with functional mode interface and test mode interface. The reuse circuit may be received in the

form of netlist or other representations of the electric/electronic circuit used in the design tool.
In Step 370, design process determines other circuit portion of the integrated circuit for desired operation. The other portion of the integrated circuit may be designed to perform desired operation of the integrated circuit being developed.
In Step 380, design process integrates reuse circuit with other circuit portion using functional interface. Integration may be performed by making suitable connection (conductive path) between the functional interface and nodes of the other circuit portions.
In Step 390, design process determines test hardware for other circuit portion and integrates with reuse circuit using test interface. Test hardware is implemented considering the components of the other circuits. Connectivity in the test mode is extended to the test interface provided in the reuse circuit for performing a integrated testing of reuse circuit and other circuit portion, the flowchart ends in step 399.
Due to use of above approach, resource and time for designing the test enable hardware is reduced when the reuse circuit of the present invention is used in the development of an integrated circuit.
Various aspect of the present invention is illustrated with an example integrated circuit. The description is provided with reference to flowcharts 3A and 3B,

5. Example Embodiment
Figure 4 is a block diagram of an integrated circuit implemented according to present invention. Integrated circuit 400 is shown containing registers 410, memory 420, combinational logic 430 and 480, sequential logic 440 and 485, IP core 460, processor 450 and 475, connectivity 401 and 402, analog circuit 470, and test enable hardware 491 and 492. Each block is described below in further detail.
Blocks 410, 420, 430, 440, 450, 460, 470, 475, 480, 485, 401 and 402 respectively operate similar to 110, 120, 130, 140, 150, 160, 170, 175, 180, 185, 101 and 102 described with reference to Figure 1. Description is not repeated for conciseness.
Circuit portion containing registers 410, memory 420, combinational logic 430, sequential logic 440, IP core 460, processor 450 connected according to connectivity 401 is determined/selected as reusable circuit portion in accordance with step 310.
Test enable hardware 491 enable testing of the selected circuit portion comprising registers 410, memory 420, combinational logic 430, sequential logic 440, IP core 460, processor 450. In one embodiment test enable hardware is implemented to test the memory 420 according to BIST scheme. However, the test enable hardware 491 may be implemented simultaneously to perform tests in accordance different standards. For example, BIST and sequential scan test may be implemented simultaneously.

Selected portion containing 410, 420, 430, 440, 460, 450 connected according to connectivity 401 and test enable hardware 491 is provided as reuse circuit 490. functional interface 495 and test interface 496 is provided to reuse circuit 490 for extemal interface. Functional interface 495 provide interface (terminals) to connect reuse circuit with other circuit in functional mode and interface 496 provide test interface.
In one embodiment, interface 496 comprise terminals scan in, scan out, clock, and mode select. Scan in terminal receives the scan vectors and loads the vector into the selected sequential elements. Scan out provides the result of the test per clock signal provided on the clock terminal. Mode select selects the connectivity within the selected portion between functional mode and test mode, the interface 496 also comprise other terminals to support BIST test.
Mode select terminal may be incorporated in interface 495 as an alternative embodiment. In one embodiment of the present invention, test interface 496 is provided as one of the extemal interface to integrated circuit 400 enabling independent testing of reuse circuit 490.
Circuit portion containing combinational logic 480, sequential logic 485, processor 475 and analog circuit 470 connected according to connectivity 402 represents other circuit portion. Test enable hardware 492 enable testing of other portion. In one embodiment the other portion is integrated with the reuse portion using interface 495 and 496.

The manner in which the reuse circuit 490 is implemented in the development of new integrated circuit is illustrated below with reference to Figure 5.
Figure 5 is a block diagram of an integrated circuit implemented by incorporating the reuse circuit of the present invention. The block diagram is shown containing reuse circuit of the present invention 490, sequential logic510, memory 520, analog circuit 540, combinational logic 560, test enable hardware 580, connectivity 402. Each block is descried below in further detail.
Connectivity 402 connects and interconnects the elements of sequential logic510, memory 520, analog circuit 540, and combinational logic 560 to form a desired circuit. Connectivity 402 also connects the terminals of the functional interface 495 to desired nodes of other circuit 492, according to a design, to integrate the functions of reuse circuit 490 with 510, 520, 540, and 560. As a result design effort for the portion of reuse circuit 490 is reduced.
Test enable hardware 580 adds test elements such as multiplexer and test enable connection between and within blocks 510, 520, 540, and 560 as per test requirement. In one embodiment test enable hardware is implemented to perform memory test in accordance with BIST. Test enable hardware 580 connects nodes of the test enable connection to the BIST interface terminals of the test interface 496. As a result. Integrated BIST test is performed.

As a result, time and resource required to design/implement the test enable hardware for the reuse portion 490 is reduced.
8. Conclusion
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims
1/ we claim
1. Methods of designing an integrated circuit, wherein said method
comprising;
selecting a first circuit portion within said integrated circuit;
adding a first test enable hardware enabling testing of said first circuit portion;
providing a first external interface to said first test enable hardware;
adding a second test enable hardware enabling testing of a second circuit portion of said integrated circuit; and
Integrating said second test enable hardware with said first extemal interface to perform an integrated testing of said first portion and said second portion.
2. The method of claim 1, wherein said first test enable hardware is implemented to perform sequential scan test, and said first extemal interface provide interface to perform sequential scan test.
3. The method of claim 1, wherein said first test enable hardware is implemented to perform built in self test (BIST), and said first external interface provide interface to perform BIST
4. The method of claim 1, wherein said first test enable hardware implemented
before implementation of said second circuit portion.

5. Method of designing a first integrated circuit to perform first operation and
a second integrated circuit to perform second operation said method
comprising;
selecting a first circuit portion within said first integrated circuit;
adding a first test enable hardware enabling testing of said first circuit portion;
providing a first external interface to said first test enable hardware;
archiving said first circuit portion, said first test enable hardware and said first external interface together as a reuse circuit;
incorporating said reuse circuit in the design of said second integrated circuit,
adding third circuit portion in said second integrated circuit to perform desired second operation; and
adding a third test enable hardware,
wherein said third test enable hardware is interfaced with said first test interface to perform integrated testing of said first circuit portion and said third circuit portion.
6. A reuse circuit comprising;
a functional circuit portion performing a desired operation according to a
design;
a test enable hardware enabling testing of said functional circuit portion;
a functional interface to integrate said functional circuit portion with an
external circuit; and
a test interface to integrate said test enable hardware with external test circuit.
7. An integrated circuit comprising;

a first circuit portion;
a second circuit portion;
a first test enable circuit, enabling testing of said first circuit portion, having
plurality of interface nodes; and
a second test enable hardware connected to said plurality of nodes;
wherein said second test enable hardware enables testing of said integrated