DESC:FIELD OF INVENTION
[0001] The present invention relates generally to Radio Frequency (RF) signal processor and particularly to RF signal processor and up-converter based on RF System-on-Chip (RFSoC).

BACKGROUND
[0002] A Radio Frequency (RF) front end interfaces antenna section and baseband processing section in an RF system. Typically, an RF system includes a receiving section and a transmitting section. The receiving section generally includes an antenna, a low noise amplifier, a band pass filter, a demodulator, and an analog to digital converter. The transmitting section generally includes a digital to analog converter, a filter, a modulator, a power amplifier, and the antenna. The RF system also includes a mixer to up-convert or down-convert frequencies of the RF signals.
[0003] Hence, multiple components are required for essential functioning of the RF system. These components occupy space and consume power.
[0004] Similarly, it is common practice in modern radars to utilize down-conversion to an intermediate frequency or base band before analog to digital conversion takes place. Several microwave components are needed for this down-conversion process, including a tunable local oscillator, band pass filters, amplifiers, and other signal conditioning devices.
[0005] In US 20090036160 A1, direct sampling of radar signals is discussed. D1 discloses a direct digital radio having a RF front end in communication with an antenna, and a radio subsystem that can be configured to form a multi-channel, full duplex transceiver system. The RF front end provides a digital signal to the radio subsystem. Each transceiver includes a waveform processing subsystem that makes use of a linear, phase-B cubic spline interpolating finite impulse response (IFIR) filter for filtering the received RF signal.
[0006] In TIDA-01442 titled “Direct RF-Sampling Radar Receiver for L-, S-, C- and X-Band Using ADC12DJ3200 Reference Design”, a direct sampling radar receiver is discussed. The TIDA-01442 TI Design utilizes the ADC12DJ3200 EVM to demonstrate a direct RF-sampling receiver for a radar operating in HF, VHF, UHF L, S, C, and part of X-band. The wide analog input bandwidth and high sampling rate (6.4 GSPS) of the analog-to-digital converter (ADC) provides multi-band coverage with a single receiver or ADC.
[0007] There is still a need for an efficient RF system that includes less components and consumes less power.

SUMMARY
[0008] This summary is provided to introduce concepts related to a Radio Frequency (RF) unit and an RF System on Chip (RFSoC). This summary is neither intended to identify essential features of the present invention nor is it intended for use in determining or limiting the scope of the present invention.
[0009] In an embodiment of the present invention, a Radio Frequency (RF) unit is provided. The RF unit includes a plurality of connectors, an RF System on Chip (RFSoC), and a clock system. The RFSoC includes one or more Analog to Digital Converters (ADC) configured to receive an RF input signal from an RF front end through the connector and generate a digital RF signal. The RFSoC includes a down converter and radar signal processor configured to down-convert the digital RF signal and generate an output signal. The output signal is provided to a display/tracker. The RFSoC includes a waveform generator and up converter configured to generate and up-convert a signal to provide an up-converted signal. The RFSoC includes one or more Digital to Analog Converters (DAC) configured to receive the up-converted signal and generate an analog RF signal. The analog RF signal is provided to a transmitter through the connector. The clock unit configured to generate and provide a clock signal to the RFSoC.
[0010] In an embodiment of the present invention, a Radio Frequency (RF) System on Chip (SoC) is provided. The RFSoC includes one or more Analog to Digital Converters (ADC), a down converter and radar signal processor, a waveform generator and up converter, and one or more Digital to Analog Converters (DAC). The ADC is configured to receive an RF input signal from an RF front end through a connector and generate a digital RF signal. The down converter and radar signal processor configured to down-convert the digital RF signal and generate an output signal. The output signal is provided to a display/tracker. The waveform generator and up converter is configured to generate and up-convert a signal to provide an up-converted signal. The DAC is configured to receive the up-converted signal and generate an analog RF signal. The analog RF signal is provided to a transmitter through the connector.
[0011] In an embodiment, the RF unit includes an Ethernet interface configured to receive one or more radar control parameters and provide the output signal to the display/tracker.
[0012] In an embodiment, the clock unit includes a plurality of clock distributors and synthesizers for generating a system reference (SYSREF) signal and the clock signal for the ADC and the DAC.
[0013] In an embodiment, the RF unit includes a master beam forming unit connected to a plurality of multi-Gigabit optical transceiver channels to provide beamformed signals.
[0014] In an embodiment, the RF unit is a single card enclosed in a metal housing.
[0015] In an embodiment, the system reference (SYSREF) signal and the clock signal are programmable.
[0016] In an embodiment, the multi-Gigabit optical transceiver channels are scalable for multiple RFSoCs.
[0017] In an embodiment, the RF unit includes further comprising a booting section configured to boot the RF unit.
[0018] In an embodiment, the RF unit includes a plurality of memory modules (SRAMs and DDR4) configured to support implementation of one or more signal processing techniques.
[0019] In an embodiment, the RF unit includes an SMA (Sub-Miniature version A) connector configured to receive external RF ADC clock.

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0020] The detailed description is described with reference to the accompanying figures.
[0021] Figure 1 illustrates a schematic block diagram of a scalable wideband Radio Frequency (RF) signal processor and up-converter based on RF System on Chip (RFSoC) in accordance with an embodiment of the present invention.
[0022] Figure 2 illustrates an RFSoC based module in accordance with an embodiment of the present invention.
[0023] Figure 3 illustrates a clocking scheme in accordance with an embodiment of the present invention.
[0024] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present invention. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

DETAILED DESCRIPTION
[0025] The various embodiments of the present invention provide a scalable wideband Radio Frequency (RF) signal processor and up-converter based on RF System on Chip (RFSoC).
[0026] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details.
[0027] One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.
[0028] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the presently invention and are meant to avoid obscuring of the presently invention.
[0029] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0030] The present invention is related to the hardware design for scalable wide-band RF signal processor and up-converter based on RFSoC (simply referred to as “RF unit”) for L-, S- and C-Band. The RF unit with RFSoC acts as a single card solution for the entire receive front end, signal processor, waveform generator, RF down-converter and up-converter for radars. The RF unit utilizing RFSoC caters to all requirements of future generation RFSoC such that direct replacement can be made possible. The present invention provides a fully scalable hardware architecture to control the individual antenna elements. This feature enables the radar to play multiple beams simultaneously and keep track of multiple targets simultaneously, eliminating the scan delays currently observed in conventional radars. The present invention provides a clocking scheme implementation for radar synchronization with higher degree of software control. Due to the elimination of intermittent stages, there is a considerable decrease of system power requirements. Also, system space, cost and maintenance requirements are reduced significantly. For high speed applications like digital beam forming, two numbers of 10G optical interface, can be utilized. Partial beam forming can be performed and the processed data can be sent over the optical interface. For digital beam forming, the number of optical channels can be completely scalable by using multiple such hardware on a custom backplane which can be further interfaced to a master beam former unit.
[0031] Referring now to Figure 1, a schematic block diagram of a scalable wideband Radio Frequency (RF) signal processor and up-converter based on RF System on Chip (RFSoC) is illustrated in accordance with an embodiment of the present invention. An RF system (100) includes an RF unit (102) which is the scalable RF signal processor and up-converter based on RFSoC. The RF unit (102) comprises an RFSoC (104), a power module (106), a DDR4 RAM (108), a booting section (110), SRAM (112), an 8-channel RF connector for ADC (114), an 8-channel RF connector for DAC (116), a 10G small form-factor pluggable (SFP) transceiver interface (118), an Ethernet physical interface (120), balun (122 and 124). The booting section (110) includes QSPI (126), SD Card (128), and JTAG (130). Figure 1 illustrates the RF channel up-converter, receiver and signal processing section as well as available booting options and communication interfaces.
[0032] Referring now to Figure 2, the RF unit (102) on a board (200) is illustrated in accordance with an embodiment of the present invention. The RF unit (102) includes an antenna unit (202), an RF front end (204), a transmitter (206), a display/tracker (208), and the RFSoC (104). The RFSoC (104) includes an RF ADC (212), a down-converter and radar signal processor (214), an RF DAC (216), and a waveform generator and up-converter (218). Figure 2 depicts entire data flow from the RF Receiver to the signal processing module and to the display unit along with the up-converter section.
[0033] Referring now to Figure 3, a clocking scheme is illustrated in accordance with an embodiment of the present invention. Figure 3 also illustrates availability of reference clocks for implementing the radar synchronization with higher degree of software control.
[0034] The present invention provides the hardware design for scalable wide band RF signal processor and up-converter based on Radio Frequency System on Chip (RFSoC) (104) for L, S- and C-Band (upto 6GHz). The RFSoC (104) includes an 8-channel RF receiver, up-converter and signal processor designed in a compact form factor of 300mm*200mm and enclosed in a 1U metal housing. From the radar point of view, the receive section of the RF unit (102) can directly interface the RF front end (204) following the antenna unit (202), the transmit section can directly interface the radar transmitter (206) and the signal processing section (214 & 218) can directly interface the tracker/display unit (208) as shown in Figures 1-2. Therefore, the RF unit (102) eliminates all the analog conditioning stages and the associated space, maintenance and cost.
[0035] The RF unit (102) acts as a single card solution replacing all the subsystems like receive front end, signal processor, waveform generator, RF down-converter and up-converter used in conventional radars. This not only facilitates dramatic system footprint reduction and shorter design cycle but also reduces the system power requirement significantly. In a conventional radar, power loss of 3dB can be observed at every mixer stage. Moreover, with multiple analog filters in the path a significant power loss can be observed. Eliminating multiple intermittent stages not only reduces the power loss but also reduces the non-linearity introduced due to the intermittent amplification and filter stages.
[0036] Scalability is one of the salient features of the hardware architecture of the RF unit (102) of the present invention. In applications where array antennas are used, each individual antenna element can be controlled by using multiple cards. For every eight antenna elements, one hardware can be used to transmit and receive RF directly controlling every individual antenna element. This provides total configurability of the antenna elements. In this configuration, multiple beams can be played in parallel. Moreover, this feature enables the radar to keep track of multiple targets eliminating the scan delays currently observed in conventional radars.
[0037] The current hardware designed of the RF unit (102) is planned with a footprint replacement for the future release version of RFSoC (104) which can receive an analog input upto 6 GHz with 16 channel ADCs (5GSPS) and DACs (10GSPS). The signal integrity, power integrity, thermal and RF analysis performance of the present design ensures to cater to all the requirements of future version of RFSoC (104). Moreover, the component selection is also done keeping in mind the requirements of future version of the RFSoC (104).
[0038] The design based on the RFSOC (104) combines a powerful Processing System (PS) and Programmable Logic (PL) in the same device. The RFSoC (104) has eight multi-giga sample (4.096 GSPS), 12 bit RF analog-to-digital converter (RF ADC) and eight multi-giga sample (6.544GSPS), 14 bit RF digital-to-analog converter (RF DAC) and can receive a maximum RF input of 4GHz. Hence, the RFSOCs (104) act as a single chip solution with dynamically reconfigurable high-performance programmable logic and DSP blocks, 28Gb/s transceivers, quad-core ARM Cortex-A53, dual-core ARM Cortex-R5 embedded processors, optional 256-bit PUF, and ruggedized-packages supporting -55C to +125C environmental operations.
[0039] The conceptual realisation of the board is (200) shown in figure 2. The board has two 8-channel RF connectors (114 and 116) for both the RF DACs (216) and the RF ADCs (212). The up-converted analog output from the eight channel RF DAC (216) is routed to the eight on-board wide band frequency baluns (30MHz-6000MHz) (124) with -1dB Pi pad attenuators. The filtered analog output is then fed to the on-board 8-channel RF connector (116) which can transmit analog output upto 6 GHz. This analog output is used to excite the radar transmit modules and subsequently the antenna elements.
[0040] The board (200) also has 8-channel RF connector (114) to receive analog input upto 6 GHz. This 8-channel analog input is then routed to the eight on-board wide band frequency baluns (30MHz-6000MHz) (122) with -1dB Pi pad attenuators. The filtered analog input is then fed to the RF ADCs (212) integrated in the RFSoC (104). In this configuration, the wideband RF signal received from the antenna followed by the radar receive modules can directly be fed to the RF connector and thereby to the RFSoC (104). This eliminates the front end microwave components in the radar and significantly reduces the system power and space.
[0041] The board (200) includes on-board RF data converter clocking which includes primary on-board reference PLL and on-board RF PLLs to generate RF ADC and RF DAC sample clocks. In addition to this, external clock may also directly drive ADC bank clocks and DAC bank clocks. The external RF ADC clock is received from SMA (Sub-Miniature version A) connector (324) and fed to a wide bandwidth (DC- 6000MHz) 4way-0 degree splitter (320) to feed across the ADC banks of RFSoC (104). Similarly, the external RF DAC clock received from the SMA connector (326) is fed to an ultra-wide bandwidth (0.5 – 9.5GHz) 2 way-0 degree splitter (322) to feed across the DAC banks of RFSoC (104). The detailed clocking scheme is illustrated in Figure 3. Moreover, the board (200) includes a mixed signal microcontroller which enables the online programming of RF clocks.
[0042] The RFSoC data converters also include power efficient digital down-converters (DDCs) and digital up-converters (DUCs) that include programmable interpolation, decimation rates, a numerically controlled oscillator (NCO) and a complex mixer. The digitally down-converted data received from the RF data converter tool is then passed through multiple signal processing stages such as digital pulse compression, side lobe cancelling, side lobe blanking, moving target indication, Doppler filtering, and constant false alarm rate. In addition to the RFSoC (104) on-chip resources, implementation of all the signal processing techniques will be supported by PL-side memory viz. two SRAMs and PS-side memory viz. DDR4. The processed signal output in the form of digital video can be routed to the tracker using PL-side or PS-side Ethernet PHY. Also, for high speed applications like digital beam forming, two numbers of optical interface can be utilized. Partial beam forming can be performed on this card and the processed data can be send over the optical interface. For digital beam forming, the number of optical channels can be completely scalable by using multiple such hardware on a custom backplane which can be further interfaced to the Master beam former unit.
[0043] The booting and configuration of the RFSoC (104) on the board (200) can be done through JTAG or Quad SPI or SD-card which can be selected by an on-board switch.
[0044] Further, multiple communication interfaces supporting different IO-standards (LVDS, LVTTL, RS422) and throughput requirements are provided in the board (200). A system monitor feature is also included in the board (200). Also, communication protocols like PS-side and PL-side I2C, PS-side USB are provided and multiple GPIOs are made available for PS-PL communication and for communication with external subsystems.
[0045] Realisation of this multiple layer PCB addresses all the system level requirements and qualifications including the EMI-EMC aspects. In order to address noise isolation, crosstalk and P/N skew control associated with RF/Analog lines, micro-vias, via-on-pad, blind vias and buried vias are introduced. Also, techniques like use of differential breakouts with neck down traces, guard traces with ground stitching vias and critical AC/DC coupling and trace routing guidelines are incorporated. For thermal analysis, Delphi thermal modelling is used in place of the conventional two-resistor model for thermal simulation.
[0046] In an embodiment of the present invention, a scalable wide-band signal processor and up-convertor based on RFSoC, referred to as RF unit (102), for L-, S- and C-Band is provided. The RF unit (102) comprises a plurality of RF ADC channels (114) for direct reception of RF signals, a plurality of RF DAC channels (116) for direct transmission of RF signals, a plurality of clock distributors and synthesizers (312, 314, 316) for generating system reference (SYSREF) and clock inputs for RF ADCs (212) and RF DACs (216), a plurality of Ethernet interface (120) to receive radar control parameters and to send the video output to the display/tracker unit (208), a plurality of multi-Gigabit transceiver channels (118) to transfer the beamformed data and to support other high speed applications, a plurality of RFSoC (104) booting and configuration options (110), a plurality of communication interfaces (132, 134, 136, 138) supporting different IO-standards and throughput requirements, a plurality of memory (SRAMs and DDR4) (112 and 118) to implement the signal processing techniques, and a metal housing for the hardware for EMI/EMC shielding.
[0047] In an embodiment, the RF unit (102) provides dramatic reduction of system maintenance, space and cost with the direct reception of RF signals. The RF unit (102) acts as a single card solution replacing all the subsystems like multichannel RF Receiver, signal processor, waveform generator, RF down-converter and up-converter used in conventional radars. The RF unit (102) provides an improvement of reliability of the hardware with the elimination of analog conditioning stages.
[0048] In an embodiment, a significant reduction in system power requirement, i.e., upto 70% of the conventional radar power requirement is achieved due to the elimination of intermittent stages by the RF unit (102).
[0049] In an embodiment, the RF unit (102) provides a fully scalable hardware architecture to control the individual antenna elements. The RF unit (102) allows playing multiple beams simultaneously and tracking multiple targets simultaneously.
[0050] In an embodiment, a future upgrade of the RFSoC (104) is footprint replaceable and also the hardware caters to all the signal integrity, power integrity, RF and thermal requirements of the upgrade version of the RFSoC (104).
[0051] In an embodiment, a plurality of SYSREF signals are generated for radar synchronization with higher degree of software control. A plurality synchronous phase coherent sampling clocks are generated for plurality of RF ADCs and RF DACs. The RFSoC (104) includes a mixed signal microcontroller for online programming of the RF clocks.
[0052] In an embodiment, the board includes a tri mode Ethernet port (120) interfacing with the RFSoC (104) to dynamically configure the parameters based on the radar computers instruction.
[0053] In an embodiment, for high speed applications like digital beam forming, plurality of multi-Gigabit optical interface can be utilized. Partial beam forming can be performed on the RF unit (102) and the processed data can be sent over the optical interface. For digital beam forming, the number of optical channels can be completely scalable by using multiple such hardware on a custom backplane which can be further interfaced to the master beam former unit.
[0054] In an embodiment, a metal casing is used to ensure the RF unit (102) compliance for EMI/EMC, better thermal performance and physical stability for the hardware
[0055] In operation, the present invention describes the hardware design and architecture of a scalable wide band RF signal processor and up-converter based on RF System on Chip (RFSoC) for L-, S- and C-Band (upto 6GHz). The board consists of an 8-channel RF up-converter receiver and signal processor designed in a compact form factor and enclosed in a 1U metal housing. From the radar point of view, the receive section of the module can directly interface the RF front end following the antenna unit, the transmit section can directly interface the radar transmitter and the signal processing section can directly interface the tracker/display unit.
[0056] Advantageously, the design eliminates all the analog conditioning stages and the associated power requirements, space, maintenance and cost. The design provides total configurability of the individual antenna elements, and thereby allows playing multiple beams simultaneously and tracking multiple targets simultaneously. Also, the current design is planned with a footprint replacement for the future release version of RFSoC which can receive an analog input upto C-Band with 16 channel ADCs (5GSPS) and DACs (10GSPS).
[0057] The scalable wide band RF signal processor and up-converter eliminates many microwave components in the radar receiver by sampling the received signal directly, without down-conversion or mixing. The manipulation of the received signals that was formerly done with microwave hardware is now done in a digital signal processor. In addition to simplifying the receiver hardware, this invention will also lead to better utilization of the frequency band, less interference from adjacent bands, improvements in system reliability and stability, reduction in system operation and maintenance costs, and will facilitate future system modifications and upgrades.
[0058] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.

,CLAIMS:

1. A Radio Frequency (RF) Unit (102) comprising:
a plurality of connectors (114 and 116);
an RF System on Chip (RFSoC) (104) comprising:
one or more Analog to Digital Converters (ADC) (212) configured to receive an RF input signal from an RF front end (204) through the connector (114) and generate a digital RF signal;
a down converter and radar signal processor (214) configured to down-convert the digital RF signal and generate an output signal, wherein the output signal is provided to a display/tracker (208);
a waveform generator and up converter (218) configured to generate and up-convert a signal to provide an up-converted signal; and
one or more Digital to Analog Converters (DAC) (216) configured to receive the up-converted signal and generate an analog RF signal, wherein the analog RF signal is provided to a transmitter (206) through the connector (116); and
a clock unit (300) configured to generate and provide a clock signal to the RFSoC (104).

2. The RF unit (102) as claimed in claim 1, further comprising an Ethernet interface (120) configured to receive one or more radar control parameters and provide the output signal to the display/tracker (208).

3. The RF unit (102) as claimed in claim 1, wherein the clock unit (300) includes a plurality of clock distributors and synthesizers (312, 314, 316) for generating a system reference (SYSREF) signal and the clock signal for the ADC (212) and the DAC (216).

4. The RF unit (102) as claimed in claim 1, further comprising a master beam forming unit connected to a plurality of multi-Gigabit optical transceiver channels (118) to provide beamformed signals.

5. The RF unit (102) as claimed in claim 1, wherein the RF unit (102) is a single card enclosed in a metal housing.

6. The RF unit (102) as claimed in claim 3, wherein the system reference (SYSREF) signal and the clock signal are programmable.

7. The RF unit (102) as claimed in claim 4, wherein the multi-Gigabit optical transceiver channels (118) are scalable for multiple RFSoCs (104).

8. The RF unit (102) as claimed in claim 1, further comprising a booting section (110) configured to boot the RF unit (102).

9. The RF unit (102) as claimed in claim 1, further comprising a plurality of memory modules (SRAMs and DDR4) (112 and 118) configured to support implementation of one or more signal processing techniques.

10. The RF unit (102) as claimed in claim 1, further comprising an SMA (Sub-Miniature version A) connector (324) configured to receive external RF ADC clock.

11. A Radio Frequency (RF) System on Chip (RFSoC) (104) comprising:
one or more Analog to Digital Converters (ADC) (212) configured to receive an RF input signal from an RF front end (204) through a connector (114) and generate a digital RF signal;
a down converter and radar signal processor (214) configured to down-convert the digital RF signal and generate an output signal, wherein the output signal is provided to a display/tracker (208);
a waveform generator and up converter (218) configured to generate and up-convert a signal to provide an up-converted signal; and
one or more Digital to Analog Converters (DAC) (216) configured to receive the up-converted signal and generate an analog RF signal, wherein the analog RF signal is provided to a transmitter (206) through the connector (116).