NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

SELF POWERED TAMPER PROOF MECHANISM FOR ELECTRONIC EQUIPMENTS

FIELD OF INVENTION

The present invention relates to a self-powered tamper proof mechanism to protect electronic equipments and its sensitive data. More particularly, the present invention relates to a tamper proof mechanism having an irreversible tamper proof routine. Further, the present invention provides a tamper proof mechanism to detect tamper attempt through any or all of the means of mechanical, electrical and environmental provisions. The present invention provides a built-in power source to detect and power tamper protection circuit and manage its status and life through appropriate means. In addition, the present invention provides a reliable memory multiple erase mechanism to ensure erasure of all memory data and to ensure that any attempt to read the memory is rendered futile.

DESCRIPTION OF PRIOR ART

Several attempts are made by various people to provide a safe and reliable protection to electronic equipment that contain sensitive data or functions and prevent such data or functions to be revealed to unauthorized or unintended persons who may attempt to get those by any means. Predominant focus has been towards securing the fasteners of the enclosure and electronic authenticating keys for authorizing the use of the equipment. For instance, US patent 7205883 deals with enclosure securing, token authenticating and automatic token exchange in case of power outage.

US6512454 describes a tamper resistant enclosure having an external and internal cover secured by four screws. A circuit is interrupted if any one of the screw is partially removed and the

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

internal cover moved. The circuit is designed to give an alarm and destroy all sensitive information contained in the protected electronic device.

US6957345 describes a system for protecting electronic devices from mechanical intrusion attempt by means of circuit traces, which is able to detect change in the resistance characteristics of the electric circuit.

The above referred patents have one or more of the following disadvantages such as the panels of the equipment has to be physically separated to trigger the tamper detection, the tamper detection will not function when the panels are cut open, the mechanism may not work when the external power to the unit is disconnected, the backup power status is not available which may defeat the purpose if the tamper is initiated when the backup power has drained out, memory erasure process may not be robust enough to completely mask the data and may be vulnerable.

A comprehensive protection against instances such as protection against even attempt to remove the enclosure fasteners without requiring physical separation, cutting open of the enclosure panels, attempt to tamper without external power; attempt to tamper in total darkness, reading the memory content by any means through multiple cycles of erasures, protection through innovative circuit to prolong the life of the internal power source; indication for internal power source low capacity through audio/visual annunciation have not been attempted so far.

Accordingly, there exist a need for providing a tamper proof mechanism having all the above features and associated novelties unified in a single embodiment, using very economical deployment and easy to manage circuitry.

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED OBJECTS OF THE INVENTION

One or more of the problems of the conventional prior art may be overcome by various embodiments of the system and method of the present invention.

The primary object of the present invention is to provide a self-powered tamper proof mechanism that protects electronic equipments and its sensitive data.

It is another object of the present invention to provide a self-powered tamper proof mechanism that protects electronic equipments and its sensitive data through an irreversible tamper proof routine.

It is another object of the present invention to provide a self-powered tamper proof mechanism to detect tamper attempt through any or all of the means of mechanical, electrical and environmental provisions.

It is another object of the present invention, wherein the self-powered tamper proof mechanism is provided with an enclosure comprising of outer panel(s) secured together by fastening means.

It is another object of the present invention, wherein the self-powered tamper proof mechanism has a mechanical and electrical interface that can detect tamper attempts to the enclosure of the electronic equipment and trigger the tamper protection mechanism.

It is another object of the present invention, wherein the self-powered tamper proof mechanism is provided with an electromagnetic interface to detect the cutting open of the panels of the enclosure without disturbing the fasteners.

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

It is another object of the invention, wherein the self-powered tamper proof mechanism is provided with an electronic infrared source and detector to detect cutting away of the panels of the enclosure without disturbing the fasteners or the electromagnetic interface arrangement.

It is another object of the invention, wherein the self-powered tamper proof mechanism is provided with a built-in power source and its associated management circuit to provide power to the tamper detection circuit in the absence of external power and manage its status and life through appropriate means.

It is another object of the invention, wherein the self-powered tamper proof mechanism is provided with an arrangement to measure and indicate the status of an internal battery so that the user is aware of the effectiveness of the built-in power source supply.

It is another object of the invention, wherein the self-powered tamper proof mechanism has a memory management program that enables multiple erasure cycles of the memory to prevent any access to the prior data.

It is another object of the invention, wherein the self-powered tamper proof mechanism is controlled by the equipment's central processing unit to enable tamper detection and to ensure data protection.

It is another object of the present invention to provide a means to test the effectiveness of the tamper proof mechanism manually without attempting to tamper.

It is another object of the present invention to provide a self-powered tamper proof mechanism to enable and control the tamper routine from the equipment's central processing unit.

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

It is another object of the present invention to provide a self-powered tamper proof mechanism that is versatile and user friendly.

SUMMARY OF THE INVENTION

Thus according to the basic aspect of the present invention there is provided a self-powered tamper proof mechanism for protecting electronic equipments comprising:

» Tamper detection and protection circuit;

» Built-in power source circuit;

» Memory management program;

» Central processing unit (CPU);

» An enclosure to house the tamper detection and protection circuit, built-in power source circuit, memory management program and central processing unit; and

» Fastening means, wherein the tamper detection and protection circuit comprising:

» Printed circuit board (PCB);

» One or more lid switches;

» One or more magnets;

» One or more reed switches; and

» Infrared (IR) trigger mechanism.

It is another aspect of the present invention, wherein pressure of the fastening means is used to activate and deactivate the lid switches.

It is another aspect of the present invention, wherein the fastening means are screws, rivets or other locking and fastening elements that has a long body.

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

It is another aspect of the present invention, wherein the reed switches are positioned directly below the magnets on one side of the PCB and positioned on the other side of the PCB directly above the magnets.

It is another aspect of the present invention, wherein the memory management program enables multiple erasure cycles of the memory to prevent any access to the prior data.

It is yet another aspect of the present invention, wherein the built-in power source circuit provides power to the tamper detection and protection circuit in the absence of external power.

According to another aspect of the present invention there is provided a self-powered tamper proof mechanism for protecting electronic equipment, wherein the IR trigger mechanism comprising:

» IR transmitter;

» Reflector; and

» IR receiver, wherein during power on condition, the IR receiver receives the IR beam from the IR transmitter through the reflection, and wherein the power supply to the IR transmitter and receiver is through the magnetic reed switches.

According to another aspect of the present invention there is provided a self-powered tamper proof mechanism for protecting electronic equipment, wherein the built-in power source circuit comprising:

» Battery; and

» One or more relays,

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

wherein the battery connected to the tamper detection and protection circuit provides power to the lid switches, manual erase switch and the magnetic reed switches, and wherein one of the relay selects power to the tamper detection and protection circuit from either the equipment's internal supply or the battery.

It is another aspect of the present invention, wherein when lever of any of the lid switches is released by the removal of the fastener, the switch closes and provides a tamper signal to a tamper detection wire.

It is another aspect of the present invention, wherein when proximity between the reed switch and the magnet is disturbed due to removal or cutting away of the panel, the reed switch closes and provides a tamper signal to the tamper detection wire.

It is another aspect of the present invention, wherein during disturbance due to removal of lid or cutting away of the reflector portion of the panel results in the loss of receiving IR light and thereby providing a tamper signal on the tamper detection wire.

It is another aspect of the present invention, wherein the IR receiver detects tamper and provides a signal on the tamper wire either due to disturbance of the magnetic circuit or removal of the panel.

It is another aspect of the present invention, wherein the power supply is provided through a regulator and managed by a potential divider.

It is another aspect of the present invention, wherein the tamper signal to the CPU is maintained by one of the relays even after the tamper attempt detection thereby ensuring continued operation of tamper protection and memory erasure.

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

It is another aspect of the present invention, wherein the mechanism resets after the tamper protection cycle has been completed.

It is another aspect of the present invention, wherein the mechanism is provided with a means to measure and indicate the status of the internal battery.

According to another aspect of the present invention there is provided a method of providing tamper detection for protecting electronic equipment using the said system comprising:

» Enabling the tamper detection circuit through the CPU;

» Providing power to the lid switches, reed switches and IR circuit by the internal power supply or from built-in battery;

» Detecting tamper through the closure or disturbance of the any or all of these switches;

» Enabling an internal clock in the CPU;

» Providing continuous tamper signal to the wire by the relay, thereby keeping the CPU in tamper protection mode;

» Enabling the CPU by the battery in the absence of the internal power source;

» Erasing the memory contents;

» Repeating the erase and write cycle for a predetermined count; and

» Disabling the battery from the circuit and de-energizing the tamper signal.

It is another aspect of the present invention, wherein erasing the memory contents includes erasing the entire contents and filling the memory with junk data.

It is another aspect of the present invention, wherein the relays are reversed disabling the battery from the circuit and de-energizing the tamper signal on reaching the predetermined count.

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

The details of the invention, its objects and advantages are explained hereunder in greater detail in relation to non-limiting exemplary illustrations as per the following accompanying figures.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

Figure 1: Illustrates the mechanical arrangement of the lid switches when the equipment is closed and in an un-tampered condition.

Figure 2: Illustrates the mechanical arrangement of the magnetic reed switches.

Figure 3: Illustrates the mechanical arrangement of the IR switches.

Figure 4: Illustrates the electric wiring diagram of the lid switches.

Figure 5: Illustrates the electric wiring diagram of the magnetic and IR switches.

Figure 6: Illustrates the electric wiring diagram of the battery, power management and relays.

Figure 7: Illustrates the electrical wiring diagram of the CPU and Memory.

Figure 8: Over all circuit representation of the tamper proofing arrangement (In un-tampered condition).

DETAILED DESCRIPTION OF THE INVENTION WITH REFERENCE TO THE ACCOMPANYING DRAWINGS

The present invention will be described with reference to the embodiments thereof. The present invention is not restricted to a specific hardware device, which may be described in the following nor is the invention restricted to one particular software solution regarding the operation and protection of the equipment. Various modifications to the disclosed embodiment will be readily apparent to those skilled in the art and general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this invention. Thus, the present invention is not intended to be limited to the embodiment disclosed, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

The present invention provides a self-powered tamper proof mechanism that protects electronic equipments and its sensitive data through an irreversible tamper proof routine. Further, the present invention describes a novel adaptation of an electronic circuit that can detect attempts to tamper the electronic equipments by way of protecting/deleting the memory data and ensuring that the action can be completed with or without power from any external source. The key data of the electronic system functions and configuration is stored in the electronic memory of the equipment in the flash/non-volatile memory and can be very vulnerable if either the system or the memory contents fall into the hands of unintended users. The deployment of the present invention provides a mean to ensure safety and security of intelligence contained within. The tamper detection and protection function is activated by the action of attempt at removing the equipment enclosure covers, trying to cut it open without removal of any fastener or attempts to unscrew the fasteners of the enclosure covers. Once the action is initiated, the tamper detection and protection action cannot be reset by returning the equipment to pre tamper condition and the memory protection/deletion action completes and renders the equipment non-functional needing to manually re-program.

The self-powered tamper proof mechanism can be used to detect tamper attempt through any or all of the means of mechanical, electrical and environmental provisions. The mechanism is protected in a triple layer through tamper recognition, irrevocable protection and memory management to ensure data opacity to the miscreant. The circuit of the present invention is protected against malfunction while in normal operation. The circuit has a ready state, a detect state and a protect state whereby distinct features are built-in to protect the electronic system from attempts of tamper and incase of such tampering, to protect the IP or software and data storage from falling into unauthorized hands. The circuit uses low cost elements for an effective

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

tamper resistance mechanism. The mechanical arrangement uses the normal packaging elements and does not involve any special made component. The tamper proof mechanism has a unique deployment of power saving and power management of the power source to ensure long storage and reliable operation.

The self powered tamper proof mechanism comprising of tamper detection and protection circuit; built-in power source circuit; memory management program; central processing unit (CPU); an enclosure to house the tamper detection and protection circuit, built-in power source circuit, memory management program and central processing unit; and fastening means. The enclosure comprises of outer panel(s) secured together by the fastening means. The fastening means are screws, rivets or other locking and fastening elements that has a long body. The tamper detection and protection circuit comprises of printed circuit board (PCB) (35); one or more lid switches (5, 6, 7 and 8); one or more magnets (20, 22); one or more reed switches (21, 23) and infrared (IR) trigger mechanism (11, 12 and 13). The effectiveness of the tamper proofing mechanism can be tested manually without attempting to tamper. The arrangement can be easily adapted to any logic based control unit and deployable around a wide range of electronic systems including security, crypto and network protection gadgets.

Referring to accompanying figures 1, 2, 3 and 4, the lid switches (5, 6, 7 and 8) that are normally closed are kept open i.e. deactivated and activated by the pressure of the fasteners (37) that hold the top and the bottom panels (34 and 36) of the enclosure. The PCB (35) is positioned within the enclosure. The fasteners (37) are provisioned in such a way that the operating lever of the lid switches (5, 6, 7 and 8) is in operated position making the switch open the electrical circuit and there by not providing any electrical signal to a tamper detection wire (14). Once lever of any of the lid switches (5, 6, 7 and 8) of the circuit is released by the removal of the fastener (37), the

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

lid switch (5, 6, 7 or 8) closes and provides a tamper signal to the tamper detection wire (14).

This is the operational description of the lid switches (5, 6, 7 and 8).

Referring to accompanying figures 2 and 5, the permanent magnets (20 and 22) are placed inside the panels (34 and 36) of the equipment and corresponding reed switches (21 and 23) are positioned directly below the magnets on one side of the PCB and positioned on the other side of the PCB directly above the magnets. During normal state of the equipment, the proximity between the magnet (20 and 22) and reed switch (21 and 23) ensures that the reed switch (21 and 23) are in operated condition (open) and the tamper detection wire (14) has no tamper signal. Once the proximity to the magnet (20 or 22) is disturbed due to removal or cutting away of the top and the bottom panels (34 or 36), then the reed switch (21or 23) closes and the tamper signal is detected by the tamper detection wire (14).

Referring to accompanying figures 3 and 5 the IR trigger comprises of an IR transmitter (11), a reflector (12) fixed inside panel (34) and IR receiver (13). The inside of the enclosure panel consists of a reflector (12) which is positioned in such a way that in powered on condition, the IR receiver (13) receives the IR beam from the IR transmitter (11) through the reflector (13). Any disturbance or block in the reflection path either due to removal of lid or cutting away of the reflector (12) portion of the panel (34) will result in the IR light not being received by the receiver (13) thereby putting a tamper signal on the tamper detection wire (14) through the resistor (16, 17) and transistor (18). In another embodiment, the power supply to the IR transmitter and receiver can be controlled through the magnetic reed switch (21 and 23) and there by the IR receiver can detect tamper and put a signal on the tamper wire (14) either due to disturbance of the magnetic circuit or due to top and the bottom panels (34 and 36) removal. The

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

IR beam is invisible to human eye and works even in darkness or low luminous environment also.

Reference is invited to accompanying figure 6 that illustrates the electric wiring of the battery, power management and relays. The built-in power source circuit includes a combination of the battery (4) and relays (3, 10, 19 and 26) to form the power circuit for the tamper detection and protection circuit. The built-in power source circuit provides power to the tamper detection and protection circuit in the absence of external power. The battery (4) is a simple unit of alkaline cells of 6 Volts with a long shelf life. The battery is connected to the normally closed contact (301) of the relay (3) which is a latching type of relay. The relay toggles between the two states of on and off through the reversal of its coil (302) current. The coil current is controlled by the central processing unit (27) and 5-volt converter (2) of the equipment. In normal operating condition of the equipment (the ready state), the coil (302) is energized in such a way that the battery is connected to the circuit to power the tamper detection through the closed contacts (301) of the relay (3). The power is made available to the lid switches (5, 6, 7 and 8), manual erase switch (9) and the reed switches (21 and 23). The power to IR transmitter (11) and receiver (13) is also routed through the reed switches (21 and 23).

Relay (19) is a power selection scheme wherein the power to the tamper circuit is selected from the equipment's internal supply of 5V dc connection (33) or the built-in battery (4). When internal supply of 5 V DC (33) is available, then the coil (1902) of relay (19) is energized and the normally open contact (1901) of the relay (19) is closed. Then 5V DC supply is made available to the CPU (27) and memories (28, 29 and 30) through 3v3 regulator (2). Normally closed contact (1901) of the relay (19) is connected to the pole of contact (1001) of the relay (10). When there is no internal power supply and the relay (10) is energized through signal from tamper

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

detection (14), the pole of contact (1001) of relay (10) is connected to the built-in battery (4) through contact (1001) of the relay (10) and this in turn provides the battery voltage to the CPU power regulator (1) through the contacts (1901) of the relay (19).

The coil (1002) of the relay (10) is energized through the tamper wire (14) signal. So the battery powers the CPU (27) only when the internal 5V DC (33) is not available and if there is a tamper signal. This helps in conserving the battery power for a longer duration. Further, the battery power is controlled by relay (3) which is a latching type relay. The CPU (27) de-energizes the relay coil (302) through 5 V converter (2) once the tamper protection routine of memory erasure is completed and this prevents further power drain from the battery. When equipment's internal DC power (33) is available, coil (1902) of relay (19) is energized to provide this power to the CPU (27) and memories (28, 29 and 30) thereby reducing the drain on battery (4) which is used only for tamper detection.

Relay (26) is another latching relay used for maintaining tamper signal to the CPU (27) even if the tamper conditions are reversed after the tamper attempt is detected. Once the tamper is detected from the tamper detection wire(14), the CPU (27) energizes the coil (2601) of relay (26) through 5V converter (32) and contacts (2601) of the relay (26) is closed and provide battery signal to the tamper wire even if the tamper conditions are removed. This ensures continued operation of tamper protection and memory erasure once the tamper is detected for even a small time. This relay coil (2601) is de-energized by the CPU (27) and 5V converter (32) once the tamper protection routine and memory erasure is completed. The battery (4) is managed by a potential divider (31) consisting of resistors (3101 and 3102) to provide analog voltage data to the CPU (27) for indicating the battery status. The 5 V converters (2 and 32) are electronic

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

bridge circuits to convert the 3.3V signal from the CPU (27) to 5V supply to the relay coils (302 and 2602) since the internal power supply of the equipment provides only 3.3 Volts to the processor and integrated circuits (IC).

Reference is invited to accompanying figure 7 that illustrate the electrical wiring of the CPU and memory. The memory bank (28, 29 and 30) is connected to the CPU (27) and powered from either the internal power supply (33) or the built-in battery (4) through the 3v3 converter (1).

Reference is invited to accompanying figure 8 that illustrates the complete schematic of die tamper detection and protection circuit. Once the equipment is ready for operation, the tamper detection is enabled through the CPU (27) and coil (302) of the relay (3) is energized which connects the battery (4) power to the lid switches (5, 6, 7 and 8), reed switches (21 and 23) and IR circuit (11 and 13) to detect tamper through the closure of the any or all of these switches. Once the tamper is detected, an internal clock in the CPU is started. In addition, the relay (26) is energized to provide continuous tamper signal to the wire (14) and thereby put the CPU (27) in tamper protection mode. The battery power keeps the CPU (27) operational in case there is no power from the equipment's internal power source (33), and begins the erasure of the memory (28, 29 and 30) in following order. Erase memory contents fully, fill memory with junk data, and increment the counter by one. This erase and write cycle is repeated for a predetermined count and on reaching the pre-determined count, the latching relays (3) and (26) are reversed disabling the battery (4) from the circuit and de-energizing the tamper signal (14) also. The multiple erasure of memory contents helps to prevent expert memory recalling and reading attempts. Thus, the tamper protection routine is completed. The logic and algorithm used does not require any additional processor and can utilize the system CPU itself. In addition, the system can be

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

easily reset after the tamper protection cycle has been completed and involves no change of components.

The potential divider (24) made of resistors (2401 and 2402) and voltage buffer (25) consisting of resistors (2501 and 2502) with transistor (2503) is for converting the 6 V battery power to allowable voltage compatible to the CPU (27) input requirement.

The manual erase switch (9) is for testing the effectiveness and operation of the tamper proof scheme and for memory erasure if needed. Closing this switch (9) enables the tamper detection signal (14) and the tamper protection routine to function as described. The tamper proof routine can be defunct with high security authorization only.

Suitable indication to the front panel of the equipment can be provided from the battery management logic in CPU (27) to indicate the status of the built-in battery (4) and take necessary proactive actions to ensure effectiveness of the tamper proof mechanism.

The present invention thus provides a tamper proof mechanism that is versatile, user friendly having an internal back-up power source to detect and power the tamper protection and manage its status and life through appropriate means. The invention further provides a reliable memory multiple erase mechanism to ensure erasure of all memory data and ensure that any attempt to read the memory is rendered futile.

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED WE CLAIM:

1. A self-powered tamper proof mechanism for protecting electronic equipments comprising:

Tamper detection and protection circuit;

Built-in power source circuit;

Memory management program;
Central processing unit (CPU) (27);

An enclosure to house the tamper detection and protection circuit, built-in power source circuit, memory management program and central processing unit; and

Fastening means (37), wherein the tamper detection and protection circuit comprising:
Printed circuit board (PCB) (35);
One or more lid switches (5, 6, 7 and 8);
One or more magnets (20, 22);
One or more reed switches (21, 23); and
Infrared (IR) trigger mechanism.

2. A self-powered tamper proof mechanism as claimed in claim 1, wherein pressure of the fastening means (37) is used to activate and deactivate the lid switches (5, 6, 7 and 8).

3. A self-powered tamper proof mechanism as claimed in claims 1 and 2, wherein the fastening means (37) are screws, rivets or other locking and fastening elements that has a long body.

4. A self-powered tamper proof mechanism as claimed in claim 1, wherein the reed switches (21, 23) are positioned directly below the magnets (20, 22) on one side of the PCB (35) and positioned on the other side of the PCB directly above the magnets.

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

5. A self-powered tamper proof mechanism as claimed in claim 1, wherein the memory management program enables multiple erasure cycles of the memory to prevent any access to the prior data.

6. A self-powered tamper proof mechanism as claimed in claim 1, wherein the built-in power source circuit provides power to the tamper detection and protection circuit in the absence of external power.

7. A self-powered tamper proof mechanism as claimed in claim 1, wherein the IR trigger mechanism comprising:

IR transmitter (11);

Reflector (12); and IR receiver (13),

wherein during power on condition, the IR receiver (13) receives the IR beam from the IR transmitter (11) through the reflection, and wherein the power supply to the IR transmitter and receiver is through the magnetic reed switches (21 and 23).

8. A self-powered tamper proof mechanism as claimed in claims 1 and 6, wherein the built-in power source circuit comprising:

Battery (4); and
One or more relays (3, 10, 19 and 26),

wherein the battery (4) connected to the tamper detection and protection circuit provides power to the switches (5, 6, 7 and 8), manual erase switch (9) and the reed switches (21 and 23), and wherein one of the relay selects power to the tamper detection and protection circuit from either the equipment's internal supply or the battery (4).

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

9. A self-powered tamper proof mechanism as claimed in claims 1 to 8, wherein when lever of any of the lid switches (5, 6, 7 and 8) is released by the removal of the fastener (37), the switch closes and provides a tamper signal to a tamper detection wire (14).

10. A self-powered tamper proof mechanism as claimed in claims 1 to 9, wherein when proximity between the reed switch and the magnet (20 or 22) is disturbed due to removal or cutting away of the panel (34 or 36), the reed switch (2lor 23) closes and provides a tamper signal to the tamper detection wire (14).

11. A self-powered tamper proof mechanism as claimed in claim 7, wherein during disturbance due to removal of lid or cutting away of the reflector (12) portion of the panel (34) results in the loss of receiving IR light and thereby providing a tamper signal on the tamper detection wire (14).

12. A self-powered tamper proof mechanism as claimed in claims 7 and 11, wherein the IR receiver detects tamper and provides a signal on the tamper wire (14) either due to disturbance of the magnetic circuit or removal of the panel.

13. A self-powered tamper proof mechanism as claimed in claims 1 to 12, wherein the power supply is provided through a regulator (2) and managed by a potential divider.

14. A self-powered tamper proof mechanism as claimed in claims 1 to 13, wherein the tamper signal to the CPU (27) is maintained by one of the relays even after the tamper attempt detection thereby ensuring continued operation of tamper protection and memory erasure.

15. A self-powered tamper proof mechanism as claimed in claims 1 to 14, wherein the mechanism resets after the tamper protection cycle has been completed.

NAME OF THE APPLICANT: SYNORO TECHNOLOGIES LIMITED

16. A self-powered tamper proof mechanism as claimed in claims 1 to 15, wherein the mechanism is provided with a means to measure and indicate the status of the internal battery.

17. A method of providing tamper detection for protecting electronic equipment using the system as claimed in anyone of claims 1 to 16, comprising:

Enabling the tamper detection circuit through the CPU (27);

Providing power to the lid switches (5, 6, 7 and 8), magnetic reed switches (21 and 23) and IR circuit (11 and 13) by the battery (4);

Detecting tamper through the closure or disturbance of the any or all of these switches;
Enabling an internal clock in the CPU;

Providing continuous tamper signal to the wire (14) by the relay, thereby enabling the CPU in tamper protection mode;

Enabling the CPU by the battery in the absence of the internal power source (33);
Erasing the memory contents;

Repeating the erase and write cycle for a predetermined count; and

Disabling the battery (4) from the circuit and de-energizing the tamper signal (14).

18. A method as claimed in claim 17, wherein erasing the memory contents includes erasing the entire contents and filling the memory with junk data.

19. A method as claimed in claim 17, wherein the relays (3) and (26) are reversed disabling the battery (4) from the circuit and de-energizing the tamper signal (14) on reaching the predetermined count.