SELF-TIMING READ ARCHITECTURE FOR SEMICONDUCTOR MEMORY AND METHOD FOR PROVDING THE SAME
Field of Invention
The instant invention relates to self-timing read architecture for semiconductor memory device.
Background of the Invention
A semiconductor memory is composed of data storage cells arranged in rows and columns. The process of reading from the memory is accomplished by means of control, address and input/output signals. At the time of reading, a set of external control signals and clock are activated. The memoiy cell from which the data is to be read is accessed and then the data is read by the read circuitry connected between the output data lines of the memory. The read circuitry performs the reading operation by sensing the voltage difference developed across the data lines. However, in order to ensure that desired data is read correctly, the read operation should be performed only when sufficient voltage differential has been developed across the data lines. This is done by ensuring a predetermined time delay between accessing of memoiy cell and reading the bit value. This time delay is controlled by a timing circuit coupled to the read circuitry. The time delay can be determined if memory structure and its likely behavior, i.e. likely time for a sufficient voltage difference to be developed, is known. However, the memoiy behavior depends on other factors such as memory size and PVT (process voltage and temperature conditions) as well. Moreover, since different process tolerances are involved in the manufacture of memories, this means that any two memories may not have identical behavior.
To overcome the aboye-mentioned problems, the concept of 'dummy cells' has been successfully used in semiconductor memory devices. These cells are provided in the memoiy region of the semiconductor device and have same structure as the actual memory cells. As a result, it takes the same time for a predetermined voltage differential to be developed across dummy bit line as in the case of normal bit line. This fact can be exploited to make the timing circuit responsive to the operating conditions of the
memory. The timing circuit receives the voltage developed on the dummy bit line as a control input. It produces a timing signal when voltage developed on dummy bit line reaches a predetermined value. The timing signal, also known as 'sense on' signal, then, simulates the read circuitry to read the voltage across the normal bit line.
In one of the configurations commonly used, the dummy memory cell is provided farther away than the memory cell which is farthest away from the control circuit. As a result, the path along which the dummy memory cell signal is retrieved has timing delay longer than that of the critical path that has the longest timing delay in the memory cell array. This ensures that the process of reading the data from all memory cells is properly performed. However, in this configuration the load of driving the dummy bit line is greater than the maximum load that can be incurred when reading data from a normal memory cell. This leads to a problem of higher power consumption.
To overcome this problem, another configuration was introduced in which the dummy memory cell and its associated circuitry are situated at a corner of the memory cell array closest to the control circuit. As a result, the dummy path for emulating data access path can be implemented as a relatively shorter path which results in dummy drive circuit having a smaller drive capacity than the signal drive circuit.
However, in all the above mentioned configurations, since the discharge circuit for normal bit line depends on the position of normal memory cell accessed and the discharge circuit for dummy bit line is fixed, the dummy bit line and the normal bit line have different resistances. Also, the vertical process gradient causes mismatch between the dummy discharge cell and the normal discharge cell. Since the position of the normal memory cell accessed in every read operation is different, this leads to statistical deviation between predermined voltage creation on bit line and 'sense on' signal arrival. This in turn reduces the speed of the operation of the memory device.
Therefore there is a need for a semiconductor memory device that is provided with a self-timing circuit so as to ensure stability against variation in operating conditions where the self-timing circuit ensures high speed and robustness.
Object and Summary of the Invention
An object of the present invention is to provide a semiconductor memory device with a self-timing circuit which provides stability against variation in operating conditions and at the same time ensures high speed of operation and robustness.
The above-mentioned object of the present invention is achieved by providing a semiconductor memory device with a control circuit, a decoder circuit, a timing circuit, an output circuitry and a memory region. Each memory array of the memory region is divided into clusters of N consecutive memory cells. One of the memory arrays is a dummy array and each cluster of dummy array shares a common circuitry. The number of dummy memory cells in a cluster determines the relationship between the voltage developed on dummy bit line and the normal bit line. Whenever a normal memory cell is accessed during the read operation, the circuitry of the corresponding dummy row enables dummy bit line to discharge. When the voltage across the dummy bit line reaches a predetermined value, a timing signal, also known as sense on signal is produced by a timing circuit present in the memory device. On receiving the sense on signal, the output circuitry of the memory device reads the voltage across the normal bit line which is nothing but the data stored in the normal memory cell accessed.
Since the discharge of dummy bit line occurs by the circuitry which is close to the accessed normal memory cell, the resistance on dummy bit line and normal bit line is always the same. This prevents any mismatch between dummy discharge cell and normal memory cell due to process gradient. Moreover, the statistical deviation between predetermined voltage creation on bit line and the arrival of 'sense on' signal is also very small. All these factors provide high speed and robustness to the memory device. An additional advantage of the clustered dummy cells is that the relationship between the voltages developed on dummy bit line and the normal bit line can be changed by simply changing the number of dummy memory cells in a particular cluster. Therefore the time delay between accessing a normal memory cell and reading the data stored in the accessed memory cell can be controlled easily by controlling the number of dummy memory cells in a particular cluster.
To achieve the aforesaid objects the instant invention provides a self-timing read
architecture for semiconductor memory device comprising:
an array of storage cells grouped into at least one cluster; - at least one dummy cell corresponding to each of the clusters, located in a manner such that the electrical characteristics of the dummy cells remain in constant proportion to the like characteristics of the corresponding cluster over the operating temperature range and manufacturing process variations;
at least one decoder for simultaneously enabling the output of a desired set of storage cells within a single cluster over a storage cell output bus and the output of the dummy cells corresponding to said cluster over a dummy cell output bus;
at least one output detector coupled to the dummy cell output bus for signaling the availability of valid output data during a read operation; read circuitry coupled to the storage cell output bus and enabled by the output of said detectors; and output drive circuitry coupled to the output of said read circuitry.
The said dummy cells are storage cells..
The said dummy cells are logic circuits.
The read access time of said dummy cells is same as the read access time of storage cells in the corresponding cluster.
The read access time of the storage cells in the corresponding cluster by a predefined value.
The said output detector is a voltage detector.
The said read circuitry is a set of sense amplifiers.
The said detectors trigger timing circuit for enabling said read circuitry.
Further the invention provides the method for self-timing read architecture for semiconductor memory device comprising the steps of:
arranging the array of storage cells in clusters;
providing at least one dummy cell corresponding to each of the clusters, located in a manner such that the electrical characteristics of the dummy cells remain in constant proportion to the like characteristics of the corresponding cluster over the operating temperature range and manufacturing process variations;
simultaneously enabling the output of a desired set of storage cells within a single cluster over a storage cell output bus and the output of the dummy cells corresponding to said cluster over a dummy cell output bus;
- monitoring the dummy cell output bus and signaling the availability of
valid output data during a read operation;
enabling read circuitry coupled to the storage cell output bus based on the output of said detectors; and coupling output drive circuitry to the output of said read circuitry.
The said signaling is based on the voltage level of the dummy cell output bus. The read circuitry is enabled using a timing sequence triggered by said signal.
Brief Descriptions of the Drawings
The present invention is described with the help of accompanying drawings:
FIGURE-1 shows the block diagram of a known semiconductor memory device.
FIGURE-2 shows the block diagram of another configuration of a known semiconductor memory device.
FIGURE-3 shows the block diagram of the semiconductor memory device as disclosed by the present invention.
Detail Description of the Invention
FIGURE-1 shows the block diagram of a semiconductor memory device presently used. The device includes a control circuit (11), a decoder circuit (12), a memory cell array (13), a read write amplifier (14), a dummy word decoder (15), a dummy word line (16), a dummy memory cell (17), and a dummy bit line (18). During read operation, the decoder circuit (12) selectively activates a word line of a memory cell array (13) when a clock signal and an address signal are supplied to the control circuit (11) from an exterior of the device. The decoder circuit supplies a read signal to a memory cell (19). The read signal propagates along the path PI, P2, P3. Data read from the memory cell (19) is then supplied to the read - write amplifier through a path P4. In parallel the dummy word decoder (15) activates the dummy word line (16) based on the clock signal CK. and the address signal ADDRESS supplied to the control circuit (11) from the exterior of the device, thereby supplying a read signal to the dummy memory cell (17). The path along which this read signal propagates is shown as PI, P6, and P7. A dummy memory cell signal read from the dummy memory cell (17) is supplied through the dummy bit line (18) to the control circuit (11). Based on this dummy memory sense signal, the control circuit (11) supplies a sense on signal to read write amplifier (14) so as to amplify the data that is read. The path along which the dummy memory cell signal and sense on signal propagate is shown as paths P8, P9 and P5. The data is then output to the exterior of the device through path P10. The path along which the dummy memory cell signal is retrieved has a timing delay longer than that of the critical path that has the longest timing delay in the memory cell array (13). This ensures that the reading of data along any path is properly performed.
In the configuration described above, the dummy memory cell (17) is provided farther away than the memory cell (19) that is farthest away from the control circuit (11). As a
result, the load of driving the dummy word decoder (15), the dummy word line (16), the dummy bit line (18) etc. is greater than the maximum load that can be incurred when reading data from the memory cell array (13). Therefore the power consumption by the self-timing circuit increases. In order to overcome this drawback, another configuration is used. It is shown in FIGURE-2.
FIGURE-2 illustrates another configuration of a semiconductor memory device designed to overcome the drawbacks of configuration shown in FIGURE-1. The device consists of a control circuit (21), decoder circuit (22), memory cell array (23), read write amplifier (24), dummy word decoder (25), dummy word line (26), dummy memory cell (27). and a dummy bit line circuit (28). The dummy word decoder (25), the dummy word line circuit (26), the dummy memory cell (27), and the dummy bit line circuit (28) together constitute a self-timing circuit. In the present configuration, the dummy word decoder (25), the dummy word line circuit (26), the dummy memory cell (27) and the dummy bit line circuit are situated at a position closer to the control circuit (21) than the memory cell array (23). PI, P2, P3 and P4 together form the data retrieval path. The path along which the read signal for the dummy memory cell propagates is shown as paths PI, P6, and P7. The path along which the dummy memory cell signal and the sense on signal propagate is shown as paths P8, P9 and P5. The data is then output to the exterior of the device through a path P10. In this configuration, since the self-timing circuit is provided at a position which is closest to the word decoder and the read write amplifier. As a result, the circuit consumes less power.
Although, the above-mentioned configuration overcomes the drawbacks of the device shown in FIGURE-1, however both the configurations of the prior art explained above still have some shortcomings. In both these configurations, the position of dummy memory cell is fixed whereas the position of normal memory cell accessed varies with each read operation. As a result, the dummy bit line resistance becomes fixed whereas the resistance of normal bit line varies depending upon the row accessed. Also, the vertical process gradient causes mismatch between the dummy discharge cell and the normal discharge cell. Moreover, since the position of the normal memory cell accessed in every
read operation changes, a statistical deviation between predermined voltage creation on bit line and 'sense on' signal arrival is created.
To overcome the shortcomings of the prior art, a novel semiconductor memory device is disclosed by the present invention. It is shown in FIGURE-3. The device consists of control circuit (31), decoder circuit (32), a normal memory cell array (33), and a dummy column (34). The dummy column (34) may comprise of memory cells or any logic devices. The memory array is divided in clusters (35) of N consecutive rows. For each cluster of N rows a common circuitry is used in block (36). A dummy bit line (38) is connected to the dummy column and a timing circuit (39). A normal bit line (37) connected to the nonnal memory cells (33) provides the read normal bit to an input/output logic (40).
During read operation, a clock signal and an address signal are supplied to the control circuit (31) from an exterior of the device. The decoder logic (32) then selectively activates a word line of a memory cell array (33) according to the address supplied to the control circuit (31). The decoder circuit (32) supplies a read signal to a normal memory cell (33). The circuitry of the block (36) of the cluster corresponding to the normal cell accessed enables the dummy bit line (38) to discharge. When the voltage across dummy bit line (38) reaches a predetermined value, a 'sense on' signal is generated by the timing circuit (39). This signal activates the sensing circuitry in input/output logic (40) to read the normal memory cell (33) data. The discharge rate of dummy bit line (38) and hence the time at which the sense on signal is generated depends on the logic device used in block (36).
In the present configuration, the time delay between the clock pulse and the generation of sense on signal depends on the discharge rate of the dummy bit line (38). The discharge rate in turn varies with the process voltage and temperature conditions and also with memory size. However, since the increase or decrease in discharge rate happens both in dummy bit line (38) and nonnal bit line (37), therefore, the time delay varies with the variation in operating conditions and the memory size. Hence, read self-timing is achieved by the present invention.
Moreover, the discharge of dummy bit line (38) is always enabled by the circuitry which corresponds to the row of the normal cell (33) which is accessed. As a result, dummy bit line (38) discharge circuit is always close to the accessed row. This results in same resistance on the normal bit line (37) and the dummy bit line (38). This in turn prevents any mismatch between dummy discharge cell and normal memory cell due to process gradient as seen in memory devices shown in FIGURE-1 and FIGURE-2. Moreover, there is very small statistical deviation between predetermined voltage creation on bit line and the arrival of 'sense on' signal. This reduction in the statistical deviation enables the memory device to attain high speed and robustness.
In a preferred embodiment of the present invention, the dummy column (34) comprises of dummy memory cells that have the same structure as that of the normal memory cells (33). The relationship between the voltage developed on the dummy bit line (38) and the voltage differential developed between the bit lines of the normal memory cell depends on the number of dummy cells in a particular cluster. As a result, this relationship can be easily changed by simply changing the number of dummy memory cells in a particular cluster.
Moreover, the discharge rate of the dummy bit line (38) may be altered by keeping one or more of the dummy cells in a cluster blank. The rest of the dummy cells in a cluster have same structure as that of the normal memory cell (33). By doing so, the load on the dummy bit line (38) can be reduced. This in turn reduces the discharge time of the dummy bit line (38). Similarly, the load on the dummy bit line (38) may be increased by decreasing the number of blank dummy cells.
Another advantage of having dummy clusters corresponding to each normal memory cell (33) is that the circuitry used for selection of a normal memory cell (33) and the circuitry for sending a signal to the dummy cell is common till the dummy clusters. As a result, variation in the signal strength occurring due to variations in the operating conditions is same for these two signals.
It is to be understood that the above-described configurations are only illustrative of the application of the principles t)f the present invention. Numerous modifications and alternative configurations may be devised by those skilled in the art without departing from the scope of the present invention, and the appended claims are intended to cover such modifications and arrangements.

claim:
1. A self-timing read architecture for semiconductor memory device comprising:
an array of storage cells grouped into at least one cluster;
at least one dummy cell corresponding to each of the clusters, located in a
manner such that the electrical characteristics of the dummy cells remain
in constant proportion to the like characteristics of the corresponding
cluster over the operating temperature range and manufacturing process
variations;
at least one decoder for simultaneously enabling the output of a desired set
of storage cells within a single cluster over a storage cell output bus and
the output of the dummy cells corresponding to said cluster over a dummy
cell output bus;
at least one output detector coupled to the dummy cell output bus for
signaling the availability of valid output data during a read operation;
read circuitry coupled to the storage cell output bus and enabled by the
output of said detectors; and
output drive circuitry coupled to the output of said read circuitry.
A self-timing read architecture for semiconductor memory device as claimed in claim 1, wherein said dummy cells are storage cells.
A self-timing read architecture for semiconductor memory device as claimed in claim 1, wherein said dummy cells are logic circuits.
A self-timing read architecture for semiconductor memory device as claimed in claim 1, wherein the read access time of said dummy cells is same as the read access time of storage cells in the corresponding cluster.
A self-timing read architecture for semiconductor memory device as claimed in claim 1, wherein the read access time of the storage cells in the corresponding cluster by a predefined value.
A self-timing read architecture for semiconductor memory device as claimed in claim 1, wherein said output detector is a voltage detector.
A self-timing read architecture for semiconductor memory device as claimed in claim 1, wherein said read circuitry is a set of sense amplifiers.
A self-timing read architecture for semiconductor memory device as claimed in claim 1, wherein said detectors trigger timing circuit for enabling said read circuitry.
A method for providing self-timing read architecture for semiconductor memory device comprising the steps of:
arranging the array of storage cells in clusters;
providing at least one dummy cell corresponding to each of the clusters,
located in a manner such that the electrical characteristics of the dummy
cells remain in constant proportion to the like characteristics of the
corresponding cluster over the operating temperature range and
manufacturing process variations;
simultaneously enabling the output of a desired set of storage cells within
a single cluster over a storage cell output bus and the output of the dummy
cells corresponding to said cluster over a dummy cell output bus;
monitoring the dummy cell output bus and signaling the availability of
valid output data during a read operation:
enabling read circuitry coupled to the storage cell output bus based on the
output of said detectors; and
coupling output drive circuitry to the output of said read circuitry.
10. A method for providing self-timing read architecture for semiconductor memory
device as claimed in claim 9, wherein said signaling is based on the voltage level
of the dummy cell output bus.
A method for providing self-timing read architecture for semiconductor memory device as claimed in claim 9, wherein the read circuitry is enabled using a timing sequence triggered by said signal.
A self-timing read architecture for semiconductor memory device substantially as herein described with reference to the accompanying drawings.
A method for providing self-timing read architecture for semiconductor memory device substantially as herein described with reference to the accompanying drawings.