DESCRIPTION Title of the Invention: SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME Technical Field [0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which a JTE (Junction Termination Extension) region is formed in a silicon carbide (SiC) substrate, and a method for manufacturing the same . Background Art [0002] A power semiconductor device includes a Schottky diode, a pn diode, an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and the like which use a silicon carbide (SiC) substrate. In these power semiconductor devices, various termination structures are introduced in order to prevent an electric field from concentrating on a pn junction portion in the SiC substrate. The termination structure includes a JTE (Junction Termination Extension) structure (for example, see Non-Patent Document 1). [0003] The JTE structure has a feature that it can easily be formed by ion implantation. Moreover, the JTE structure also has a feature that it can easily be designed because a carrier concentration of a JTE region is preferably designed in order to cause the JTE region to be perfectly depleted in a dielectric breakdown. [0004] Referring to a semiconductor device having the JTE structure (which will be hereinafter referred to as a "device" in some cases), the following techniques are proposed in order to reduce an electric field intensity on a surface of the JTE region. For example, in Patent Document 1, the technique for giving a concentration gradient to a JTE region is proposed. In Patent Document 2, moreover, there is proposed the technique for covering a pn junction and a JTE region with a third layer. By these techniques, a semiconductor device having a high withstand voltage is attempted to be implemented. Prior Art Documents Patent Documents [0005] Patent Document 1: Japanese Translation of PCT International Application Publication No. 2000 – 516767 Patent Document 2: Japanese Translation of PCT International Application Publication No. 2002-507325 Non-Patent Document [0006] Non-Patent Document 1: B. Jayant Baliga, "FUNDAMENTALS OF POWER SEMICONDUCTOR DEVICES", pl49 - pi55 Summary of the Invention Problems to be Solved by the Invention [0007] In the semiconductor devices having a high withstand voltage disclosed in Patent Document 1 and Patent Document 2, a peak of an electric field intensity is generated between JTE regions or in a junction portion of the JTE region and an epitaxial layer when a comparatively high reverse voltage is applied to a pn junction. There is a problem in that creeping discharge is generated on an outside of a substrate and the withstand voltage of the semiconductor device is thus dropped remarkably if a peak value of the electric field intensity reaching a surface of the substrate is great. In addition, there is a problem in that the peak value of the electric field intensity is gradually increased with a rise in the withstand voltage in a withstand specification of the semiconductor device. [0008] The JTE structure for controlling the peak value of the electric field intensity includes the structure in which a concentration gradient is given to the JTE region as disclosed in Patent Document 1 and the structure in which the pn junction and the JTE region are covered with the third layer as disclosed in Patent Document 2. [0009] With the JTE structure disclosed in Patent Document 1 and Patent Document 2, however, the JTE regions do not always have a retrograde distribution. The "retrograde distribution" indicates a distribution having a peak of an impurity concentration at a back side of a substrate, that is, an inner side from a surface on one of sides in a thickness direction of the JTE region. [0010] More specific description will be given. With the JTE structures disclosed in Patent Document 1 and Patent Document 2, the high impurity region having a comparatively high impurity concentration is formed to reach the surface of the JTE region. Accordingly, there is a problem in that the peak value of the electric field intensity reaching the surface of the JTE region or the surface of the device cannot be reduced sufficiently. [0011] With the JTE structure disclosed in Patent Document 2, moreover, the third layer covering the pn junction and the JTE region does not always have a higher impurity concentration than the drift layer. When a comparatively high reverse voltage is applied to the device, accordingly, the third layer is perfectly depleted to hold the electric field. For this reason, there is a problem in that it is impossible to sufficiently reduce the peak value of the electric field intensity which reaches the surface of the device. [0012] It is an object of the present invention to provide a semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained, and a method for manufacturing the same. Means for Solving the Problems [0013] A semiconductor device according to the present invention includes a silicon carbide substrate having a first conductivity type, a silicon carbide layer provided on a surface at one of sides in a thickness direction of the silicon carbide substrate and having the first conductivity type, a second conductivity type region formed in a part of a vicinal portion of a surface on one of sides in a thickness direction of the silicon carbide layer and having a second conductivity type, and a plurality of junction termination regions formed in a portion on an outer peripheral end side of the silicon carbide substrate from the second conductivity type region in the vicinal portion of the surface at one of the sides in the thickness direction of the silicon carbide layer and having the second conductivity type, and the plurality of junction termination regions are formed adjacently to each other or apart from each other in at least the surface on one of the sides in the thickness direction of the silicon carbide layer, and a first conductivity type region having the first conductivity type and a higher concentration of an impurity having the first conductivity type than that of the silicon carbide layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the junction termination regions are bonded to each other or a portion provided between the junction termination regions which are disposed apart from each other. [0014] Moreover, a method for manufacturing a semiconductor device according to the present invention includes a silicon carbide layer forming step of forming a silicon carbide layer having a first conductivity type over a surface at one of sides in a thickness direction of a silicon carbide substrate having the first conductivity type, a second conductivity type region forming step of forming a second conductivity type region having a second conductivity type in a part of a vicinal portion of a surface on one of sides in a thickness direction of the silicon carbide layer, a termination region forming step of carrying out an ion implantation treatment over a portion on an outer peripheral end side of the silicon carbide substrate from the second conductivity type region in the vicinal portion of the surface at one of the sides in the thickness direction of the silicon carbide layer, thereby forming a plurality of junction termination regions having the second conductivity type adjacently to each other or apart from each other in at least the surface on one of the sides in the thickness direction of the silicon carbide layer, and a first conductivity type region forming step of carrying out an ion implantation treatment in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the junction termination regions are bonded to each other or a portion provided between the junction termination regions which are disposed apart from each other, thereby forming a first conductivity type region having the first conductivity type and a higher concentration of an impurity having the first conductivity type than that of the silicon carbide layer. Effects of the Invention [0015] According to the semiconductor device in accordance with the present invention, in the case in which a comparatively high reverse voltage is applied to the pn junction, the first conductivity type region serves as an electric field shield. Moreover, depletion in the surface at one of the sides in the thickness direction of the junction termination region can be suppressed by the first conductivity type region. Therefore, a portion in the junction termination region in which electric field intensity is the highest can be positioned on the other side in the thickness direction from the surface on one of the sides in the thickness direction of the junction termination region. Consequently, it is possible to reduce a peak value of the electric field intensity which reaches the surface on one of the sides in the thickness direction of the junction termination region or the surface on one of the sides in the thickness direction of the silicon carbide layer including the junction termination region. Therefore, it is possible to suppress creeping discharge on an outside of a substrate constituted by the silicon carbide layer and the silicon carbide substrate. Accordingly, it is possible to prevent a withstand voltage of the semiconductor device from being dropped. Consequently, it is possible to implement a semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained. [0016] According to the method for manufacturing a semiconductor device in accordance with the present invention, moreover, it is possible to provide the semiconductor device having a high withstand voltage according to the present invention in which a stable withstand voltage can be obtained as described above. [0017] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Brief Description of Drawings [0018] Fig. 1 is a sectional view showing a structure of a semiconductor device 1 according to a first embodiment of the present invention. Fig. 2 is a graph showing a relationship between electric field intensities reaching substrate surfaces SO in two types of JTE structures and a distance from a second conductivity type SiC region 13. Fig. 3 is a chart showing a simulation result of a comparative JTE structure B. Fig. 4 is a chart showing a simulation result of the present JTE structure A. Fig. 5 is a chart showing an impurity profile of a comparative JTE structure D. Fig. 6 is a chart showing an impurity profile of the present JTE structure C. Fig. 7 is a graph showing a relationship between electric field intensities reaching substrate surfaces SO in the two types of the JTE structures C and D and a lateral distance of a substrate. Fig. 8 is a sectional view showing a state of a stage in which formation of the second conductivity type SiC region 13 is ended. Fig. 9 is a sectional view showing a state of a stage in which formation of an ohmic contact region 14 is ended. Fig. 10 is a sectional view showing a state of a stage in which formation of a JTE region 15 is ended. Fig. 11 is a sectional view showing a state of a stage in which formation of a first conductivity type SiC region 16 is ended. Fig. 12 is a sectional view showing a state of a stage in which formation of a protective film 17 is ended. Fig. 13 is a sectional view showing a state of a stage in which formation of an opening portion 18 is ended. Fig. 14 is a sectional view showing another example of the first conductivity type SiC region. Fig. 15 is a sectional view showing yet another example of the first conductivity type SiC region. Fig. 16 is a sectional view showing a further example of the first conductivity type SiC region. Fig. 17 is a sectional view showing a structure of a semiconductor device 2 according to a second embodiment of the present invention. Fig. 18 is a sectional view showing a state of a stage in which formation of a JTE region 15 is ended. Fig. 19 is a sectional view showing a state of a stage in which formation of a first conductivity type SiC region 16 is ended. Fig. 20 is a sectional view showing a state of a stage in which formation of a protective film 17 is ended. Fig. 21 is a sectional view showing a state of a stage in which formation of an opening portion 18 is ended. Fig. 22 is a sectional view showing another example of the first conductivity type SiC region. Fig. 23 is a sectional view showing a further example of the first conductivity type SiC region. Embodiment for Carrying Out the Invention [0019] 2 or polyimide. [0087] Fig. 13 is a sectional view showing a state of a stage in which formation of the opening portion 18 is ended. After the protective film 17 is formed, the opening portion 18 is formed on the protective film 17 as shown in Fig. 13. The opening portion 18 is formed in such a manner that the ohmic contact region 14 is exposed from a bottom part of the opening portion 18 as shown in Fig. 13. [0088] After the opening portion 18 is formed, the anode electrode 19 shown in Fig. 1 is formed so as to be electrically connected to the ohmic contact region 14 exposed from the bottom part of the opening portion 18. Moreover, the cathode electrode 20 shown in Fig. 1 is formed on a surface at the other side in the thickness direction of the SiC substrate 11. [0089] Through the steps described above, there is obtained the semiconductor device 1 according to the first embodiment of the present invention shown in Fig. 1. In the present embodiment, it is possible to obtain the semiconductor device 1 in which the first conductivity type SiC region 16 is present in the vicinal portion of the surface on one of the sides in the thickness direction in the portion in which the JTE regions 15 are bonded to each other, and furthermore, the second conductivity type SiC region 13 is present in the deeper position than the first conductivity type SiC region 16 from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12. [0090] The semiconductor device 1 having the structure can reduce the peak value of the electric field intensity which reaches the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 also in the case in which the electric field concentrates on the junction portion of the adjacent JTE regions 15 so that the peak of the electric field intensity is generated when the comparatively high reverse voltage is applied to the pn junction as described above. According to the method for manufacturing a semiconductor device according to the present embodiment, therefore, it is possible to provide the semiconductor device 1 having a high withstand voltage in which a stable withstand voltage can be obtained. [0091] In the present embodiment, moreover, the implantation energy in the ion implantation treatment is regulated to adjust the distribution of the impurity concentration of the JTE region 15. Accordingly, by setting the ion implantation energy into one type, for example, it is possible to easily manufacture the semiconductor device 1 having a high withstand voltage in which a stable withstand voltage can be obtained as described above. [0092] Although the JTE region 15 is formed by the ion implantation treatment, and then, the ion implantation treatment is further carried out to form the first conductivity type SiC region 16 as shown in Figs. 10 and 11 in the present embodiment described above, the first conductivity type SiC region may be formed by another forming method. [0093] Fig. 14 is a sectional view showing another example of the first conductivity type SiC region. Fig. 14 shows a state of a stage in which formation of a first conductivity type SiC region 26 according to another example of the first conductivity type SiC region is ended. As shown in Fig. 14, the first conductivity type SiC region 26 may be formed by using a lateral spreading effect in the ion implantation for forming a JTE region 25. [0094] In this case, in the ion implantation treatment for forming the JTE region 25, the position in which the ion is to be implanted is adjusted to couple the adjacent JTE regions 25 in a deeper position than the surface on one of sides in the thickness direction of the SiC epitaxial layer 12 by using the lateral spreading effect in the ion implantation. Consequently, a portion in which the JTE regions 25 are not coupled to each other is formed in the vicinal portion of the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12. The portion in which the JTE regions 25 are not coupled to each other, that is, the SiC epitaxial layer 12 which is left between the JTE regions 25 provided apart from each other serves as the first conductivity type SiC region 26. [0095] Herein, the JTE region 25 corresponds to a junction termination region. The first conductivity type SiC region 26 corresponds to a first conductivity type region. With the structure shown in Fig. 14, similarly, it is possible to obtain the same effects as those in the present embodiment. [0096] Although the first conductivity type SiC region 26 is shown in different hatching from the SiC epitaxial layer 12 in Fig. 14, they are actually identical to each other. As described above, the SiC epitaxial layer 12 left between the JTE regions 25 after the ion implantation treatment for forming the JTE region 25 serves as the first conductivity type SiC region 26. [0097] By thus forming the first conductivity type SiC region 26 using the lateral spreading effect in the ion implantation for forming the JTE region 25, it is possible to omit the step of the ion implantation treatment for forming the first conductivity type SiC region 26. Accordingly, the semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained as described above can be manufactured further easily and inexpensively as compared with the present embodiment. [0098] Moreover, the adjacent JTE regions 25 may be coupled to each other in the deeper position than the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 to form the first conductivity type SiC region 26 by another method. As another method, for example, it is possible to use a method for tapering a resist serving as an implantation mask or a method for carrying out the ion implantation treatment over the SiC substrate 11 in an oblique direction. Also in the case in which the first conductivity type SiC region 26 is thus formed, it is possible to obtain the same effects as those in the present embodiment. [0099] In the present embodiment, furthermore, the ion implantation treatment is carried out over the SiC epitaxial layer 12 in order to form the JTE region 15. In the ion implantation treatment for forming the JTE region 15, it is desirable to carry out the ion implantation treatment in such a manner that an average value of the implantation surface density over the whole termination implantation region constituted by the adjacent JTE regions 15 to the second conductivity type SiC region 13 is 0.5 x 10 / cm to 3 x 10 / cm2. The implantation surface density is equal to an integral of a volume impurity density over the thickness of the impurity region. In the case in which the volume impurity concentration is constant over the thickness of the impurity region, the implantation surface density is equal to a product of the volume impurity concentration and the thickness of the impurity region. [0100] In the present embodiment, a thickness of each of the JTE regions 15, that is, a depth from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 is approximately 0.6 \xm to 1.0 u.m. Moreover, an implantation width of each of the JTE regions 15 is approximately 30 jun to 300 p.m. An impurity concentration of the first conductivity type SiC region 16 is approximately 1016 / cm3 to 1017 / cm3, and a thickness thereof, that is, a depth from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 is approximately 0.1 \xm to 0.3 \im. [0101] In the present embodiment, furthermore, the description has been given to the case in which the semiconductor device 1 is the pn diode. However, the present invention is not restricted to the pn diode but the structure of the semiconductor device 1 according to the present embodiment can be applied to any termination structure having the JTE region 15. For example, it is also possible to apply the structure of the semiconductor device 1 according to the present embodiment to a Schottky diode using SiC, an MOSFET using SiC, an insulated gate bipolar transistor (abbreviation: IGBT) using SiC or the like. [0102] More specific description will be given. In the present embodiment, an implantation profile for forming the JTE region 15 is taken in such a manner that the impurity concentration in the vicinal portion of the surface on one of the sides in the thickness direction of the JTE region 15 is lower than the implantation peak. The first conductivity type SiC region 16 is present in the vicinal portion of the surface on one of the sides in the thickness direction of the junction portion between the JTE regions 15. Moreover, the second conductivity type SiC region 13 is present from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 to the deeper position than the first conductivity type SiC region 16. Such a structure can also be applied to a semiconductor device using SiC having the JTE region 15, for example, a Schottky diode, an MOSFET, an IGBT or the like. [0103] Although the description has been given to the structure in which the first conductivity type SiC region 16 is positioned in only the vicinal portion of the surface of the junction portion between the adjacent JTE regions 15 in the present embodiment, moreover, the first conductivity type SiC region may have another structure. [0104] Figs. 15 and 16 are sectional views showing another example of the first conductivity type SiC region. Figs. 15 and 16 show a state of a stage in which formation of first conductivity type SiC regions 31 and 32 according to another example of the first conductivity type SiC region is ended. The first conductivity type SiC regions 31 and 32 correspond to the first conductivity type region. [0105] The first conductivity type SiC region may be formed over the whole vicinal portion of the surface on one of the sides in the thickness direction of the termination region constituted by the JTE regions 15 in the same manner as the first conductivity type SiC region 31 shown in Fig. 15. Moreover, the firstconductivity type SiC region may be formed over the whole vicinal portion of the surface on one of the sides in the thickness direction of the device including the second conductivity type SiC region 13 and the ohmic contact region 14 in addition to the termination region in the same manner as the first conductivity type SiC region 32 shown in Fig. 16. With the structures shown in Figs. 15 and 16, similarly, it is possible to obtain the same effects as those in the present embodiment. [0106] 2 or polyimide. [0120] Fig. 21 is a sectional view showing a state of a stage in which formation of an opening portion 18 is ended. After the protective film 17 is formed, the opening portion 18 is formed on the protective film 17 as shown in Fig. 21. The opening portion 18 is formed in such a manner that the ohmic contact region 14 is exposed from a bottom part of the opening portion 18 as shown in Fig. 21. [0121] After the opening portion 18 is formed, the anode electrode 19 shown in Fig. 17 is formed so as to be electrically connected to the ohmic contact region 14 exposed from the bottom part of the opening portion 18 in the same manner as in the first embodiment. Moreover, the cathode electrode 20 shown in Fig. 17 is formed on a surface at the other side in the thickness direction of the SiC substrate 11. [0122] Through the steps described above, there is obtained the semiconductor device 2 according to the second embodiment of the present invention. In the present embodiment, it is possible to obtain the semiconductor device 2 in which the first conductivity type SiC region 16 is present in the vicinal portion of the surface on one of the sides in the thickness direction in the junction portion of the JTE region 15 and the SiC epitaxial layer 12, and furthermore, the second conductivity type SiC region 13 is present in a deeper position than the first conductivity type SiC region 16 from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12. [0123] Also in the semiconductor device 2 according to the present embodiment, accordingly, it is possible to obtain the same effects as those described in the first embodiment. In other words, it is possible to reduce a peak value of an electric field intensity which reaches the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 also in the case in which the electric field concentrates on the portion in which the JTE region 15 and the SiC epitaxial layer 12 are bonded to each other so that the peak of the electric field intensity is generated when a comparatively high reverse voltage is applied to a pn junction. Therefore, it is possible to provide the semiconductor device 2 having a high withstand voltage in which a stable withstand voltage can be obtained. [0124] In the present embodiment, the description has been given to the case in which the semiconductor device 2 is the pn diode. However, the present invention is not restricted to the pn diode but the structure of the semiconductor device 2 according to the present embodiment can be applied to any termination structure having the JTE region 15. For example, it is possible to apply the structure according to the present embodiment to a Schottky diode using SiC, an MOSFET using SiC, an 1GBT using SiC or the like. [0125] In other words, it is also possible to apply, to the Schottky diode using the SiC, the MOSFET using the SiC, the IGBT using the SiC or the like which has the JTE region 15, the structure in which an implantation profile for forming the JTE region 15 is taken in such a manner that the impurity concentration in the vicinal portion of the surface on one of the sides in the thickness direction of the JTE region 15 is lower than the implantation peak, the first conductivity type SiC region 16 is present in the vicinal portion of the surface on one of the sides in the thickness direction of the junction portion of the JTE region 15 and the SiC epitaxial layer 12, and the second conductivity type SiC region 13 is present from the surface on one of the sides in the thickness direction of the SiC epitaxial layer 12 to the deeper position than the first conductivity type SiC region 16. [0126] By thus applying the structure according to the present embodiment, it is possible to obtain the same effects as those in the present embodiment. [0127] Although the description has been given to the structure in which the first conductivity type SiC region 16 is positioned in only the vicinal portion of the surface of the junction portion of the JTE region 15 and the SiC epitaxial layer 12 in the present embodiment, moreover, another structure may be employed. [0128] Figs. 22 and 23 are sectional views showing another example of the first conductivity type SiC region. Figs. 22 and 23 show a state of a stage in which formation of first conductivity type SiC regions 31 and 32 serving as the first conductivity type SiC regions is ended. [0129] The first conductivity type SiC region may be formed over the whole vicinal portion of the surface on one of the sides in the thickness direction of the termination region constituted by the JTE regions 15 in the same manner as the first conductivity type SiC region 31 shown in Fig. 22. Moreover, the first conductivity type SiC region may be formed over the whole vicinal portion of the surface in the device including the second conductivity type SiC region 13 and the ohmic contact region 14 shown in Fig. 23. With the structures shown in Figs. 22 and 23, similarly, it is possible to obtain the same effects as those in the present embodiment. [0130] In the first and second embodiments described above, each of the JTE regions 15 and 25 has the concentration of the second conductivity type impurity which is lower than the second conductivity type SiC region 13. Consequently, it is possible to reduce the electric field intensities in the JTE regions 15 and 25. Therefore, it is possible to suppress creeping discharge on the outside of the substrate more reliably. Accordingly, it is possible to prevent a drop in the withstand voltage of the semiconductor device more reliably. [0131] In the first and second embodiments, furthermore, the JTE regions 15 and 25 are disposed in such a manner that the concentration of the second conductivity type impurity is decreased from the inner side of the substrate toward the outermost edge side in the lateral direction. Consequently, the electric field intensities of the JTE regions 15 and 25 can be reduced gradually toward the outermost edge side of the substrate. Therefore, it is possible to suppress the creeping discharge on the outside of the substrate further reliably. Accordingly, it is possible to prevent the drop in the withstand voltage of the semiconductor device further reliably. [0132] Each of the JTE regions 15 and 25 may be formed in such a manner that the concentration of the second conductivity type impurity is equal to that of the second conductivity type SiC region 13. Consequently, it is possible to form the second conductivity type SiC region 13 and the JTE regions 15 and 25 at the same step. Therefore, it is possible to easily manufacture the semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained as described above. [0133] In the first and second embodiments, moreover, the inner JTE regions 15 and 25 to be formed on the innermost side of the substrate in the lateral direction in the JTE regions 15 and 25 are provided adjacently to the second conductivity type SiC region 13 in the lateral direction. The present invention is not restricted to the structure but the inner JTE regions 15 and 25 may be formed apart from the second conductivity type SiC region 13 in the lateral direction. In other words, the inner JTE regions 15 and 25 and the second conductivity type SiC region 13 may be formed apart from each other in the lateral direction. Also in the case of the structure, it is possible to obtain the same effects as those in the first and second embodiments. [0134] Although the first conductivity type is set to be the n type and the second conductivity type is set to be the p type in the first and second embodiments, moreover, the first conductivity type may be set to be the p type and the second conductivity type may be set to be the n type. In this case, the SiC substrate 11, the SiC epitaxial layer 12 and the first conductivity type SiC region 16 have the p-type conductivity and the second conductivity type SiC region 13, the ohmic contact region 14 and the JTE region 15 have the n-type conductivity. [0135] While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention. Explanation of Designations [0136] 1,2 semiconductor device, 11 silicon carbide (SiC) substrate, 12 SiC epitaxial layer, 13 second conductivity type SiC region, 14 ohmic contact region, 15, 25 JTE region, 16, 26, 31, 32 first conductivity type SiC region, 17 protective film, 18 opening portion, 19 anode electrode, 20 cathode electrode. CLAIMS 1. A semiconductor device comprising: a silicon carbide substrate (11) having a first conductivity type; a silicon carbide layer (12) provided on a surface at one of sides in a thickness direction of said silicon carbide substrate (11) and having the first conductivity type; a second conductivity type region (13) formed in a part of a vicinal portion of a surface on one of sides in a thickness direction of said silicon carbide layer (12) and having a second conductivity type; and a plurality of junction termination regions (15, 25) formed in a portion on an outer peripheral end side of said silicon carbide substrate (11) from said second conductivity type region (13) in the vicinal portion of the surface at one of the sides in the thickness direction of said silicon carbide layer (12) and having the second conductivity type, wherein said plurality of junction termination regions (15, 25) are formed adjacently to each other or apart from each other in at least the surface on one of the sides in the thickness direction of said silicon carbide layer (12),'and a first conductivity type region (16, 26, 31, 32) having the first conductivity type and a higher concentration of an impurity having the first conductivity type than that of said silicon carbide layer (12) is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which said junction termination regions (15) are bonded to each other or a portion provided between said junction termination regions (15, 25) which are disposed apart from each other. 2. The semiconductor device according to claim 1, wherein said junction termination regions (25) are provided apart from each other in the surface on one of the sides in the thickness direction of said silicon carbide layer (12) and are formed to be coupled to each other in the other side in the thickness direction of said silicon carbide layer (12) from said surface. 3. The semiconductor device according to claim 1, wherein each of said junction termination regions (15, 25) has a concentration of an impurity having the second conductivity type which is equal to that of said second conductivity region (13). 4. The semiconductor device according to claim 1, wherein each of said junction termination regions (15, 25) has a concentration of an impurity having said second conductivity type which is lower than that of said second conductivity type region (13). 5. The semiconductor device according to claim 1, wherein said junction termination regions (15, 25) are disposed in such a manner that a concentration of an impurity having said second conductivity type is decreased gradually toward the outer peripheral end side of said silicon carbide substrate (11). 6. The semiconductor device according to claim 1, wherein a concentration of an impurity having said second conductivity type in each of said junction termination regions (15, 25) has a maximum value at the other side in the thickness direction than the surface on one of the sides in the thickness direction. 7. The semiconductor device according to claim 6, wherein each of said junction termination regions (15, 25) has said concentration of the impurity having the second conductivity type in the surface on one of the sides in the thickness direction which is equal to or lower than one-tenth of said maximum value. 8. A method for manufacturing a semiconductor device comprising: a silicon carbide layer forming step of forming a silicon carbide layer (12) having a first conductivity type over a surface at one of sides in a thickness direction of a silicon carbide substrate (11) having the first conductivity type; a second conductivity type region forming step of forming a second conductivity type region (13) having a second conductivity type in a part of a vicinal portion of a surface on one of sides in a thickness direction of said silicon carbide layer (12); a termination region forming step of carrying out an ion implantation treatment over a portion on an outer peripheral end side of said silicon carbide substrate (11) from said second conductivity type region (13) in the vicinal portion of the surface at one of the sides in the thickness direction of said silicon carbide layer (12), thereby forming a plurality of junction termination regions (15, 25) having the second conductivity type adjacently to each other or apart from each other in at least the surface on one of the sides in the thickness direction of said silicon carbide layer (12); and a first conductivity type region forming step of carrying out an ion implantation treatment in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which said junction termination regions (15) are bonded to each other or a portion provided between said junction termination regions (15, 25) which are disposed apart from each other, thereby forming a first conductivity type region (16, 26, 31, 32) having the first conductivity type and a higher concentration of an impurity having the first conductivity type than that of said silicon carbide layer (12). 9. The method for manufacturing a semiconductor device according to claim 8, wherein at said termination region forming step, said junction termination regions (25) are provided apart from each other in the surface on one of the sides in the thickness direction of said silicon carbide layer (12) and are formed to be coupled to each other in the other side in the thickness direction of said silicon carbide layer (12) from said surface. 10. The method for manufacturing a semiconductor device according to claim 8, wherein at said termination region forming step, an ion implantation amount in said ion implantation treatment is regulated to form said junction termination regions (15, 25) in such a manner that a concentration of an impurity having the second conductivity type in said junction termination regions (15, 25) is decreased gradually toward the outer peripheral end side of said silicon carbide substrate (11). 11. The method for manufacturing a semiconductor device according to claim 8, wherein at said termination region forming step, an ion implantation amount in said ion implantation treatment is regulated to form each of said junction termination regions (15, 25) in such a manner that a concentration of an impurity having the second conductivity type in each of said junction termination regions (15, 25) has a maximum value on the other side in the thickness direction of said silicon carbide layer (12) from the surface on one of the sides in the thickness direction of said silicon carbide layer (12).