WO 2018/101957 PCT7US2016/064658
CLAIMS
What is claimed is:
1. A semiconductor structure, comprising:
a semiconductor fin protruding through a trench isolation region above a substrate, the semiconductor fin having a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end;
a gate electrode over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin, the gate electrode between the first end and the second end of the semiconductor fin;
a first dielectric plug at the first end of the semiconductor fin; and
a second dielectric plug at the second end of the semiconductor fin, wherein the first and second dielectric plugs each comprise a first dielectric material laterally surrounding and below a second dielectric material different from the first dielectric material.
2. The semiconductor structure of claim I, wherein the first dielectric material is silicon nitride, and the second semiconductor material is silicon oxide.
3. The semiconductor structure of claim 1, wherein the first dielectric material is further over the second dielectric material.
4. The semiconductor structure of claim 1, wherein the first and second dielectric plugs each further comprise a third dielectric material over the second dielectric material and between portions of the first semiconductor material, the third dielectric material different from the first and second dielectric materials.
5. The semiconductor structure of claim 1, wherein the first and second dielectric plugs are each disposed in a corresponding trench disposed in an inter-layer dielectric layer.
6. The semiconductor structure of claim 5, wherein each corresponding trench comprises a dielectric sidewall spacer.
7. The semiconductor structure of claim 1, further comprising:
a first source/drain region between the gate electrode and the first dielectric plug at the first end of the semiconductor fin, and

WO 2018/101957 PCT7US2016/064658
a second source/drain region between the gate electrode and the second dielectric plug at the second end of the semiconductor fin.
8. The semiconductor structure of claim 7, wherein the first and second source/drain regions are embedded source/drain regions comprising a semiconductor material different than the semiconductor fin.
9. The semiconductor structure of claim 1, wherein both of the first dielectric plug and the second dielectric plug are free of voids.

10. The semiconductor structure of claim 1, wherein one or both of the first dielectric plug and the second dielectric plug is deeper into the substrate than the semiconductor fin.
11. The semiconductor of claim 1, wherein the region of the top surface and the region of the pair of sidewalls of the semiconductor fin define a channel region of an N-type semiconductor device, and wherein the first dielectric plug and the second dielectric plug induce a uniaxial tensile stress on the channel region.
12. The semiconductor of claim 1, wherein the region of the top surface and the region of the pair of sidewalls of the semiconductor fin define a channel region of a P-type semiconductor device, and wherein the first dielectric plug and the second dielectric plug induce a uniaxial compressive stress on the channel region.
13. A semiconductor structure, comprising:
a semiconductor fin protruding through a trench isolation region above a substrate, the
semiconductor fin having a top surface, a first end, a second end, and a pair of sidewalls
between the first end and the second end; a gate electrode over a region of the top surface and laterally adjacent to a region of the pair
of sidewalls of the semiconductor fin, the gate electrode between the first end and the
second end of the semiconductor fin; a first dielectric plug at the first end of the semiconductor fin; and a second dielectric plug at the second end of the semiconductor fin, wherein both of the first
dielectric plug and the second dielectric plug are free of voids.

WO 2018/101957 PCT7US2016/064658
14. The semiconductor structure of claim 13, wherein the first and second dielectric plugs are each disposed in a corresponding trench disposed in an inter-layer dielectric layer.
15. The semiconductor structure of claim 14, wherein each corresponding trench comprises a dielectric sidewall spacer.
16. The semiconductor structure of claim 13, further comprising;
a first source/drain region between the gate electrode and the first dielectric plug at the first
end of the semiconductor fin; and a second source/drain region between the gate electrode and the second dielectric plug at the
second end of the semiconductor fin.
17. The semiconductor structure of claim 16, wherein the first and second source/drain regions are embedded source/drain regions comprising a semiconductor material different than the semiconductor fin.
18. The semiconductor structure of claim 13, wherein one or both of the first dielectric plug and the second dielectric plug is deeper into the substrate than the semiconductor fin.
19. The semiconductor of claim 13, wherein the region of the top surface and the region of the pair of sidewalls of the semiconductor fin define a channel region of an N-type semiconductor device, and wherein the first dielectric plug and the second dielectric plug induce a uniaxial tensile stress on the channel region.
20. The semiconductor of claim 13, wherein the region of the top surface and the region of the pair of sidewalls of the semiconductor fin define a channel region of a P-type semiconductor device, and wherein the first dielectric plug and the second dielectric plug induce a uniaxial compressive stress on the channel region.
21. A method of fabricating a semiconductor structure, the method comprising:
forming a semiconductor fin protruding through a trench isolation region above a substrate, the semiconductor fin having a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end;
forming a plurality of dummy gate structures above the semiconductor fin and separated from one another by an inter-layer dielectric (ILD) layer, a first of the plurality of dummy gate

WO 2018/101957 PCT7US2016/064658
structures at the first end of the semiconductor fin, a second of the plurality of dummy gate structures over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin, and a third of the plurality of dummy gate structures at the second end of the semiconductor fin, removing the first and the third of the plurality of dummy gate structures but not the second of the plurality of dummy gate staictures, the removing forming a first trench in the ILD layer at the first end of the semiconductor fin and forming a second trench in the ILD layer at the second end of the semiconductor fin; and forming a first dielectric plug in the first trench and a second dielectric plug in the second trench, wherein forming the first and second dielectric plugs comprises:
forming a first dielectric material along sidewalls and bottoms of the first and second
trenches; and forming a second dielectric material between the first dielectric material along the sidewalls of the first and second trenches and on the first dielectric layer on the bottoms of the first and second trenches, the second dielectric material different from the first dielectric material.
22. The method of claim 21, wherein the first of the plurality of dummy gate structures is formed over a portion of the first end and a first portion of the top surface of the semiconductor fin, and the third of the plurality of dummy gate structures is formed over a portion of the second end and a second portion of the top surface of the semiconductor fin.
23. The method of claim 21, further comprising:
subsequent to forming the first and second dielectric plugs, removing the second of the
plurality of dummy gate structures to form a third trench between the first end and the
second end of the semiconductor fin, and forming a permanent gate electrode in the third trench, the permanent gate electrode over the
region of the top surface and laterally adjacent to the region of the pair of sidewalls of the
semiconductor fin,
24. The method of claim 21, wherein forming the second dielectric material of the first and
second dielectric plugs comprises:
depositing a flowable silicon dioxide precursor in the first and second trenches and on the
first dielectric layer on the bottoms of the first and second trenches; converting the flowable silicon dioxide precursor to silicon dioxide, and

WO 2018/101957 PCT7US2016/064658
curing the silicon oxide material to reduce a volume of the silicon oxide material,
25. The method of claim 21, wherein forming the first and second dielectric plugs further
comprises:
5 forming a third dielectric material on the second dielectric material.
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