FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
SEMICONDUCTOR MODULE PARALLEL CIRCUIT AND SEMICONDUCTOR
MODULE CONNECTION SUBSTRATE;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANISED
AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3,
MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 100-8310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.
2
DESCRIPTION
SEMICONDUCTOR MODULE PARALLEL CIRCUIT AND SEMICONDUCTOR
MODULE CONNECTION SUBSTRATE
5
Field
[0001] The present invention relates to a semiconductor
module parallel circuit and a semiconductor module
connection substrate.
10
Background
[0002] A technique for driving parallel-connected
semiconductor switching elements is known in, for example,
Patent Literature 1. Patent Literature 1 discloses that
15 twisted cables, which are gate wiring to two IGBTs, are
laid adjacent to connection lines, such that electromotive
forces generated in the twisted cables and polarities
thereof are substantially equal to one another and gateemitter voltages of the individual elements substantially
20 are equal to one another, thereby providing balanced
currents flowing through the individual elements.
Citation List
Patent Literature
25 [0003] Patent Literature 1: Japanese Patent Application
Laid-open No. H9-261948
Summary
Technical Problem
30 [0004] In recent years, susceptibility to the influence
of inductance is increased with an increase in the speed of
switching. Patent Literature 1 does not allow for the
influence of inductance. When a difference in inductance
3
occurs between the semiconductor elements, an imbalance in
the amount of current flowing through individual
semiconductor elements occurs. Upon occurrence of such an
imbalance in the current flowing through the semiconductor
5 elements, a larger amount of current flows in one of the
semiconductor elements, which leads to a shortened lifetime
of the semiconductor.
Solution to Problem
10 [0005] A semiconductor module parallel circuit of a
first invention comprises: a first power semiconductor
module; a second power semiconductor module; and a
multilayer substrate to interconnect a plurality of the
power semiconductor modules, wherein each of the power
15 semiconductor modules includes: a power semiconductor
switching element; a first signal terminal connected to a
gate potential of the power semiconductor switching
element; and a second signal terminal connected to a source
potential of the power semiconductor switching element, the
20 multilayer substrate includes: an external connection
terminal; a first signal terminal connection pattern for
the first power semiconductor module, the first signal
terminal connection pattern for the first power
semiconductor module being connected to the first signal
25 terminal of the first power semiconductor module; a second
signal terminal connection pattern for the first power
semiconductor module, the second signal terminal connection
pattern for the first power semiconductor module being
connected to the second signal terminal of the first power
30 semiconductor module; a first signal terminal connection
pattern for the second power semiconductor module, the
first signal terminal connection pattern for the second
power semiconductor module being connected to the first
4
signal terminal of the second power semiconductor module;
and a second signal terminal connection pattern for the
second power semiconductor module, the second signal
terminal connection pattern for the second power
5 semiconductor module being connected to the second signal
terminal of the second power semiconductor module, and an
inductance of gate wiring for the first power semiconductor
module from the external connection terminal to the first
signal terminal connection pattern for the first power
10 semiconductor module and from the second signal terminal
connection pattern for the first power semiconductor module
to the external connection terminal, and an inductance of
gate wiring for the second power semiconductor module from
the external connection terminal to the first signal
15 terminal connection pattern for the second power
semiconductor module and from the second signal terminal
connection pattern for the second power semiconductor
module to the external connection terminal are equal to
each other.
20 [0006] A semiconductor module parallel circuit of a
second invention comprises: a first power semiconductor
module; a second power semiconductor module; and a
multilayer substrate to interconnect a plurality of the
power semiconductor modules, wherein each of the power
25 semiconductor modules includes: a power semiconductor
switching element; a first signal terminal connected to a
gate potential of the power semiconductor switching
element; and a second signal terminal connected to a source
potential of the power semiconductor switching element, the
30 multilayer substrate includes: an external connection
terminal; a first signal terminal connection pattern for
the first power semiconductor module, the first signal
terminal connection pattern for the first power
5
semiconductor module being connected to the first signal
terminal of the first power semiconductor module; a second
signal terminal connection pattern for the first power
semiconductor module, the second signal terminal connection
5 pattern for the first power semiconductor module being
connected to the second signal terminal of the first power
semiconductor module; a first signal terminal connection
pattern for the second power semiconductor module, the
first signal terminal connection pattern for the second
10 power semiconductor module being connected to the first
signal terminal of the second power semiconductor module;
and a second signal terminal connection pattern for the
second power semiconductor module, the second signal
terminal connection pattern for the second power
15 semiconductor module being connected to the second signal
terminal of the second power semiconductor module, and a
length of gate wiring for the first power semiconductor
module from the external connection terminal to the first
signal terminal connection pattern for the first power
20 semiconductor module and from the second signal terminal
connection pattern for the first power semiconductor module
to the external connection terminal, and a length of gate
wiring for the second power semiconductor module from the
external connection terminal to the first signal terminal
25 connection pattern for the second power semiconductor
module and from the second signal terminal connection
pattern for the second power semiconductor module to the
external connection terminal are equal to each other.
[0007] A semiconductor module connection substrate of a
30 third invention comprises: an external connection terminal;
a first signal terminal connection pattern for a first
power semiconductor module, the first signal terminal
connection pattern for the first power semiconductor module
6
being provided for connection to a first signal terminal of
the first power semiconductor module; a second signal
terminal connection pattern for the first power
semiconductor module, the second signal terminal connection
5 pattern for the first power semiconductor module being
provided for connection to a second signal terminal of the
first power semiconductor module; a first signal terminal
connection pattern for a second power semiconductor module,
the first signal terminal connection pattern for the second
10 power semiconductor module being provided for connection to
a first signal terminal of the second power semiconductor
module; and a second signal terminal connection pattern for
the second power semiconductor module, the second signal
terminal connection pattern for the second power
15 semiconductor module being provided for connection to a
second signal terminal of the second power semiconductor
module, wherein an inductance of gate wiring for the first
power semiconductor module from the external connection
terminal to the first signal terminal connection pattern
20 for the first power semiconductor module and from the
second signal terminal connection pattern for the first
power semiconductor module to the external connection
terminal, and an inductance of gate wiring for the second
power semiconductor module from the external connection
25 terminal to the first signal terminal connection pattern
for the second power semiconductor module and from the
second signal terminal connection pattern for the second
power semiconductor module to the external connection
terminal are equal to each other.
30
Advantageous Effects of Invention
[0008] A semiconductor module parallel circuit according
to the first invention comprises: a first power
7
semiconductor module; a second power semiconductor module;
and a multilayer substrate to interconnect a plurality of
the power semiconductor modules, wherein each of the power
semiconductor modules includes: a power semiconductor
5 switching element; a first signal terminal connected to a
gate potential of the power semiconductor switching
element; and a second signal terminal connected to a source
potential of the power semiconductor switching element, the
multilayer substrate includes: an external connection
10 terminal; a first signal terminal connection pattern for
the first power semiconductor module, the first signal
terminal connection pattern for the first power
semiconductor module being connected to the first signal
terminal of the first power semiconductor module; a second
15 signal terminal connection pattern for the first power
semiconductor module, the second signal terminal connection
pattern for the first power semiconductor module being
connected to the second signal terminal of the first power
semiconductor module; a first signal terminal connection
20 pattern for the second power semiconductor module, the
first signal terminal connection pattern for the second
power semiconductor module being connected to the first
signal terminal of the second power semiconductor module;
and a second signal terminal connection pattern for the
25 second power semiconductor module, the second signal
terminal connection pattern for the second power
semiconductor module being connected to the second signal
terminal of the second power semiconductor module, and an
inductance of gate wiring for the first power semiconductor
30 module from the external connection terminal to the first
signal terminal connection pattern for the first power
semiconductor module and from the second signal terminal
connection pattern for the first power semiconductor module
8
to the external connection terminal, and an inductance of
gate wiring for the second power semiconductor module from
the external connection terminal to the first signal
terminal connection pattern for the second power
5 semiconductor module and from the second signal terminal
connection pattern for the second power semiconductor
module to the external connection terminal are equal to
each other. As a result, it is possible to reduce an
imbalance in current between the semiconductor modules, and
10 to reduce shortening of the lifetime of semiconductor
elements.
[0009] A semiconductor module parallel circuit according
to the second invention comprises: a first power
semiconductor module; a second power semiconductor module;
15 and a multilayer substrate to interconnect a plurality of
the power semiconductor modules, wherein each of the power
semiconductor modules includes: a power semiconductor
switching element; a first signal terminal connected to a
gate potential of the power semiconductor switching
20 element; and a second signal terminal connected to a source
potential of the power semiconductor switching element, the
multilayer substrate includes: an external connection
terminal; a first signal terminal connection pattern for
the first power semiconductor module, the first signal
25 terminal connection pattern for the first power
semiconductor module being connected to the first signal
terminal of the first power semiconductor module; a second
signal terminal connection pattern for the first power
semiconductor module, the second signal terminal connection
30 pattern for the first power semiconductor module being
connected to the second signal terminal of the first power
semiconductor module; a first signal terminal connection
pattern for the second power semiconductor module, the
9
first signal terminal connection pattern for the second
power semiconductor module being connected to the first
signal terminal of the second power semiconductor module;
and a second signal terminal connection pattern for the
5 second power semiconductor module, the second signal
terminal connection pattern for the second power
semiconductor module being connected to the second signal
terminal of the second power semiconductor module, and a
length of gate wiring for the first power semiconductor
10 module from the external connection terminal to the first
signal terminal connection pattern for the first power
semiconductor module and from the second signal terminal
connection pattern for the first power semiconductor module
to the external connection terminal, and a length of gate
15 wiring for the second power semiconductor module from the
external connection terminal to the first signal terminal
connection pattern for the second power semiconductor
module and from the second signal terminal connection
pattern for the second power semiconductor module to the
20 external connection terminal are equal to each other. As a
result, it is possible to reduce an imbalance in current
between the semiconductor modules, and to reduce shortening
of the lifetime of semiconductor elements.
[0010] A semiconductor module connection substrate
25 according to the third invention comprises: an external
connection terminal; a first signal terminal connection
pattern for a first power semiconductor module, the first
signal terminal connection pattern for the first power
semiconductor module being provided for connection to a
30 first signal terminal of the first power semiconductor
module; a second signal terminal connection pattern for the
first power semiconductor module, the second signal
terminal connection pattern for the first power
10
semiconductor module being provided for connection to a
second signal terminal of the first power semiconductor
module; a first signal terminal connection pattern for a
second power semiconductor module, the first signal
5 terminal connection pattern for the second power
semiconductor module being provided for connection to a
first signal terminal of the second power semiconductor
module; and a second signal terminal connection pattern for
the second power semiconductor module, the second signal
10 terminal connection pattern for the second power
semiconductor module being provided for connection to a
second signal terminal of the second power semiconductor
module, wherein an inductance of gate wiring for the first
power semiconductor module from the external connection
15 terminal to the first signal terminal connection pattern
for the first power semiconductor module and from the
second signal terminal connection pattern for the first
power semiconductor module to the external connection
terminal, and an inductance of gate wiring for the second
20 power semiconductor module from the external connection
terminal to the first signal terminal connection pattern
for the second power semiconductor module and from the
second signal terminal connection pattern for the second
power semiconductor module to the external connection
25 terminal are equal to each other. As a result, it is
possible to reduce an imbalance in current between the
semiconductor modules, and to reduce shortening of the
lifetime of semiconductor elements.
30 Brief Description of Drawings
[0011] FIG. 1 is a view illustrating a semiconductor
module parallel circuit according to a first embodiment.
FIG. 2 is a schematic diagram of the semiconductor
11
module parallel circuit according to the first embodiment.
FIG. 3 is a plan view of a package accommodating a
semiconductor module according to the first embodiment.
FIG. 4 is a schematic diagram of the semiconductor
5 module according to the first embodiment.
FIG. 5 is a view illustrating a multilayer substrate
according to the first embodiment.
FIG. 6 is a view illustrating a wiring pattern on the
multilayer substrate according to the first embodiment.
10 FIG. 7 is a view illustrating a wiring pattern on the
multilayer substrate according to the first embodiment.
FIG. 8 is a view illustrating a semiconductor module
parallel circuit in a second embodiment.
FIG. 9 is a view illustrating a multilayer substrate
15 according to the second embodiment.
FIG. 10 is a schematic view of the semiconductor
module parallel circuit according to the second embodiment.
FIG. 11 is a view illustrating a gate drive current in
the semiconductor module parallel circuit according to the
20 second embodiment.
FIG. 12 is a view illustrating a semiconductor module
parallel circuit in a third embodiment.
FIG. 13 is a view illustrating a multilayer substrate
according to the third embodiment.
25 FIG. 14 is a schematic view of the semiconductor
module parallel circuit according to the third embodiment.
FIG. 15 is a view illustrating a semiconductor module
parallel circuit in a fourth embodiment.
FIG. 16 is a view illustrating a multilayer substrate
30 according to the fourth embodiment.
FIG. 17 is a schematic view of the semiconductor
module parallel circuit according to the fourth embodiment.
FIG. 18 is a view illustrating a semiconductor module
12
parallel circuit in a fifth embodiment.
FIG. 19 is a view illustrating a multilayer substrate
according to the fifth embodiment.
FIG. 20 is a schematic view of the semiconductor
5 module parallel circuit according to the fifth embodiment.
FIG. 21 is a view illustrating a gate drive current in
the semiconductor module parallel circuit according to the
fifth embodiment.
10 Description of Embodiments
[0012] First Embodiment
FIG. 1 is a view illustrating a semiconductor module
parallel circuit 1 according to a first embodiment. The
semiconductor module parallel circuit 1 includes a
15 semiconductor module 10-1, a semiconductor module 10-2, and
a multilayer substrate 100. The multilayer substrate 100
is disposed immediately above the semiconductor module 10-1
and the semiconductor module 10-2, and is physically fixed
by a fastening member 50. The semiconductor module 10-1
20 and the semiconductor module 10-2 are electrically
connected in parallel to each other through the multilayer
substrate 100. In the following description, the
semiconductor modules 10-1 and 10-2 are referred to as
semiconductor modules 10 where the semiconductor modules
25 10-1 and 10-2 need not be distinguished from each other.
The semiconductor module 10 is, for example, a power
semiconductor module.
[0013] When used for a three-phase two-level inverter
circuit, the semiconductor module 10-1 and the
30 semiconductor module 10-2 define, for example, a U-phase
leg of the three-phase two-level inverter circuit.
[0014] FIG. 2 is a schematic diagram of the
semiconductor module parallel circuit according to the
13
first embodiment. The semiconductor module 10-1 and the
semiconductor module 10-2 are each enclosed by a broken
line.
[0015] The semiconductor module 10-1 includes a
5 semiconductor element 30-1 and a semiconductor element 40-1
connected in series with each other, and a source terminal
of the semiconductor element 30-1 and a drain terminal of
the semiconductor element 40-1 are connected to each other.
[0016] The semiconductor module 10-2 includes a
10 semiconductor element 30-2 and a semiconductor element 40-2
connected in series with each other, and a source terminal
of the semiconductor element 30-2 and a drain terminal of
the semiconductor element 40-2 are connected to each other.
[0017] A gate terminal 11-1 of the semiconductor element
15 30-1 of the semiconductor module 10-1, a gate terminal 11-2
of the semiconductor element 30-2 of the semiconductor
module 10-2, and a first connection terminal 71-1 of an
external connection terminal 61 of the multilayer substrate
are electrically connected to one another. A sense source
20 terminal 13-1 of the semiconductor element 30-1 of the
semiconductor module 10-1, a sense source terminal 13-2 of
the semiconductor element 30-2 of the semiconductor module
10-2, and a second connection terminal 72-1 of the external
connection terminal 61 of the multilayer substrate are
25 electrically connected to one another. The gate terminal
11-1 of the semiconductor element 30-1 of the semiconductor
module 10-1 may be referred to as a first signal terminal
11-1, and the gate terminal 11-2 of the semiconductor
element 30-2 of the semiconductor module 10-2 may be
30 referred to as a first signal terminal 11-2. The sense
source terminal 13-1 of the semiconductor element 30-1 of
the semiconductor module 10-1 may be referred to as a
second signal terminal 13-1, and the sense source terminal
14
13-2 of the semiconductor element 30-2 of the semiconductor
module 10-2 may be referred to as a second signal terminal
13-2. The first signal terminal 11-1 of the semiconductor
element 30-1 of the semiconductor module 10-1 and the first
5 signal terminal 11-2 of the semiconductor element 30-2 of
the semiconductor module 10-2 each have a gate potential.
The second signal terminal 13-1 of the semiconductor
element 30-1 of the semiconductor module 10-1 and the
second signal terminal 13-2 of the semiconductor element
10 30-2 of the semiconductor module 10-2 each have a source
potential.
[0018] A gate terminal 12-1 of the semiconductor element
40-1 of the semiconductor module 10-1, a gate terminal 12-2
of the semiconductor element 40-2 of the semiconductor
15 module 10-2, and a first connection terminal 71-2 of an
external connection terminal 62 of the multilayer substrate
are electrically connected to each other. A sense source
terminal 14-1 of the semiconductor element 40-1 of the
semiconductor module 10-1, a sense source terminal 14-2 of
20 the semiconductor element 40-2 of the semiconductor module
10-2, and a second connection terminal 72-2 of the external
connection terminal 62 of the multilayer substrate are
electrically connected to each other. The gate terminal
12-1 of the semiconductor element 40-1 of the semiconductor
25 module 10-1 may be referred to as a third signal terminal
12-1, and the gate terminal 12-2 of the semiconductor
element 40-2 of the semiconductor module 10-2 may be
referred to as a third signal terminal 12-2. The sense
source terminal 14-1 of the semiconductor element 40-1 of
30 the semiconductor module 10-1 may be referred to as a
fourth signal terminal 14-1, and the sense source terminal
14-2 of the semiconductor element 40-2 of the semiconductor
module 10-2 may be referred to as a fourth signal terminal
15
14-2. The third signal terminal 12-1 of the semiconductor
element 40-1 of the semiconductor module 10-1 and the third
signal terminal 12-2 of the semiconductor element 40-2 of
the semiconductor module 10-2 each have a gate potential.
5 The fourth signal terminal 14-1 of the semiconductor
element 40-1 of the semiconductor module 10-1 and the
fourth signal terminal 14-2 of the semiconductor element
40-2 of the semiconductor module 10-2 each have a source
potential.
10 [0019] A drain terminal of the semiconductor element 30-
1 of the semiconductor module 10-1 and a drain terminal of
the semiconductor element 30-2 of the semiconductor module
10-2 are connected to each other, and connected to a
direct-current bus on a higher potential side (not
15 illustrated).
[0020] A source terminal of the semiconductor element
40-1 of the semiconductor module 10-1 and a source terminal
of the semiconductor element 40-2 of the semiconductor
module 10-2 are connected to each other, and connected to a
20 direct-current bus on a lower potential side (not
illustrated).
[0021] FIG. 3 is a plan view of a package 20
accommodating the semiconductor module 10 according to the
first embodiment. Although not illustrated in FIG. 3, the
25 package 20 includes the semiconductor element 30-1 and the
semiconductor element 40-1 connected in series with each
other. As illustrated in FIG. 3, main terminals 10P, main
terminals 10N, and main terminals 10AC are provided on one
surface side of the package 20. Two main terminals 10P,
30 which are provided at a longitudinal one end portion of the
package 20, are arranged in a direction orthogonal to the
longitudinal direction. Two main terminals 10N, which are
provided closer to a central portion of the package 20 than
16
the main terminals 10P, are arranged in the direction
orthogonal to the longitudinal direction of the package 20.
Each of the main terminal 10P and the main terminal 10N is
not limited to two in number. Each of the main terminal
5 10P and the main terminal 10N may be one, or three or more.
Three main terminals 10AC, which are provided at the
longitudinal other end portion of the package 20, are
arranged in the direction orthogonal to the longitudinal
direction. The number of main terminals 10AC is not
10 limited to three. The number of main terminals 10AC may be
one or two, or four or more.
[0022] The main terminals 10P each define a directcurrent positive terminal P in the semiconductor module 10,
the main terminals 10N each define a direct-current
15 negative terminal N in the semiconductor module 10, and the
main terminals 10AC each define an alternating-current
terminal AC in the semiconductor module 10.
[0023] A first signal terminal 11, a second signal
terminal 13, a third signal terminal 12, and a fourth
20 signal terminal 14 are provided between the main terminals
10N and the main terminals 10AC. In other words, the first
signal terminal 11, the second signal terminal 13, the
third signal terminal 12, and the fourth signal terminal 14
are provided between the direct-current terminals and the
25 alternating-current terminals. The second signal terminal
13 and the first signal terminal 11 are arranged from a
side of the main terminal 10AC along one side in the
longitudinal direction of the package 20. In addition, the
third signal terminal 12 and the fourth signal terminal 14
30 are provided from the side of the main terminal 10AC along
the other side in the longitudinal direction of the package
20.
[0024] The first signal terminal 11, the second signal
17
terminal 13, the third signal terminal 12, and the fourth
signal terminal 14 are connected to the multilayer
substrate 100.
[0025] FIG. 4 is a schematic diagram of the
5 semiconductor module 10 according to the first embodiment.
The semiconductor module 10 includes a semiconductor
element 30 connected to the main terminal 10P and a
semiconductor element 40 connected to the main terminal 10N.
The semiconductor element 30 and the semiconductor element
10 40 are connected in series with each other, and an
electrical connection point therebetween is connected to
the main terminal 10AC.
[0026] The semiconductor element 30 includes a drain
terminal D1 connected to the main terminal 10P, a source
15 terminal S1 connected to the main terminal 10AC, the first
signal terminal 11, and the second signal terminal 13. The
drain terminal has a drain potential, the source terminal
has a source potential, and the first signal terminal 11
has a gate potential.
20 [0027] The semiconductor element 40 includes a drain
terminal D2 connected to the main terminal 10AC, a source
terminal S2 connected to the main terminal 10N, the third
signal terminal 12, and the fourth signal terminal 14. The
drain terminal has a drain potential, the source terminal
25 has a source potential, and the third signal terminal 12
has a gate potential.
[0028] In each of the semiconductor element 30 and the
semiconductor element 40, a transistor element and a diode
element are connected in parallel to each other. Depending
30 on characteristics of a load, for example, in a case of a
resistive load, the connection of each diode element may be
omitted.
[0029] In the first embodiment, a MOSFET is illustrated
18
as the transistor element, but the transistor element is
not limited to the MOSFET, and any device, which is
switchable between a low resistance state and a high
resistance state in accordance with an electric signal, may
5 be employed. For example, a transistor element such as an
IGBT or a bipolar transistor may be used. In a case where
the transistor element is an IGBT, the “drain terminal” is
replaced with a “collector terminal”, the “source terminal”
is replaced with an “emitter terminal”, and the “sense
10 source terminal” is replaced with a “sense emitter
terminal”. Silicon (Si), silicon carbide (SiC), gallium
nitride (GaN), and the like can be used as materials of
transistor elements and diode elements that define the
semiconductor elements 30 and 40.
15 [0030] FIG. 5 is a plan view of the multilayer substrate
100 used for the semiconductor module parallel circuit 1
according to the first embodiment. In FIG. 5, the
multilayer substrate 100 includes a plurality of layers.
Illustrated in FIG. 5 is a first layer that is a visible
20 layer, and is referred to as a front surface. A layer that
is a visible layer and is located on a side opposite to the
front surface is referred to as a back surface. The first
layer and a second layer may be invisible layers.
[0031] The external connection terminal 61 and the
25 external connection terminal 62 are mounted on the front
surface of the multilayer substrate 100. The external
connection terminal 61 and the external connection terminal
62 are connected to an external control circuit (not
illustrated). The external connection terminals 61 and 62
30 are mounted on the front surface in FIG. 5, but may be
mounted on the back surface. The external connection
terminals 61 and 62 may be integrated with each other.
[0032] First signal terminal connection patterns 111-1
19
and 111-2, second signal terminal connection patterns 113-1
and 113-2, third signal terminal connection patterns 112-1
and 112-2, and fourth signal terminal connection patterns
114-1 and 114-2 are formed as patterns. The third signal
5 terminal connection patterns 112-1 and 112-2 and the fourth
signal terminal connection patterns 114-1 and 114-2 are not
illustrated.
[0033] The first signal terminal connection patterns
111-1 and 111-2, the second signal terminal connection
10 patterns 113-1 and 113-2, the third signal terminal
connection patterns 112-1 and 112-2, and the fourth signal
terminal connection patterns 114-1 and 114-2 are each
electrically connected to a back surface pattern through a
through hole.
15 [0034] The first signal terminal connection pattern 111-
1, the second signal terminal connection pattern 113-1, the
third signal terminal connection pattern 112-1, and the
fourth signal terminal connection pattern 114-1 are
patterns for connection to the first signal terminal 11-1,
20 the second signal terminal 13-1, the third signal terminal
12-1, and the fourth signal terminal 14-1 of the
semiconductor module 10-1, respectively.
[0035] The first signal terminal connection pattern 111-
2, the second signal terminal connection pattern 113-2, the
25 third signal terminal connection pattern 112-2, and the
fourth signal terminal connection pattern 114-2 are
patterns for connection to the first signal terminal 11-2,
the second signal terminal 13-2, the third signal terminal
12-2, and the fourth signal terminal 14-2 of the
30 semiconductor module 10-2, respectively.
[0036] Next, a description will be made as to parallel
connection of the semiconductor module 10-1 and the
semiconductor module 10-2 through the multilayer substrate
20
100 of the semiconductor module parallel circuit 1
according to the first embodiment.
[0037] FIG. 6 is a view illustrating an example in which
the first signal terminal connection patterns 111-1 and
5 111-2 in the multilayer substrate 100 are connected to each
other. In FIG. 6, a direction extending from the external
connection terminal 61 of the multilayer substrate 100 to
each semiconductor module is defined as an X direction, a
direction extending from the back surface to the front
10 surface of the multilayer substrate is defined as a Z
direction (not illustrated), and a direction orthogonal to
the X direction and the Z direction is defined as a Y
direction. In FIG. 6, the first signal terminal connection
patterns 111-1 and 111-2 and the external connection
15 terminal 61 are wired. The first signal terminal
connection patterns 111-1 and 111-2 share common wiring
from the external connection terminal 61 to a point S. The
wiring branches off from the point S into connection to the
first signal terminal connection pattern 111-1 and the
20 first signal terminal connection pattern 111-2. That is,
the point S is a branch point. For two semiconductor
modules, the point S can be a midpoint of the wiring
between the first signal terminal connection patterns 111-1
and 111-2. With the wiring laid as described above, a
25 wiring length from the external connection terminal 61 to
the first signal terminal connection pattern 111-1 and a
wiring length from the external connection terminal 61 to
the first signal terminal connection pattern 111-2 can be
equal to each other. In FIG. 6, the wiring from the
30 external connection terminal 61 to the first signal
terminal connection patterns is formed in the same layer of
the multilayer substrate 100, but may not be formed in the
same layer. Different layers of the multilayer substrate
21
100 may be used. For example, the wiring from the external
connection terminal 61 to the point S and the wiring
between 111-1 and 111-2 may be in different layers.
[0038] Descriptions and illustrations of the third
5 signal terminal connection patterns 112-1 and 112-2 are
similar to those of the first signal terminal connection
patterns 111-1 and 111-2, and thus will be omitted.
[0039] FIG. 7 is a view illustrating an example in which
the second signal terminal connection patterns 113-1 and
10 113-2 in the multilayer substrate 100 are connected to each
other. In FIG. 7, a direction extending from the external
connection terminal 61 of the multilayer substrate 100 to
each semiconductor module is defined as an X direction, a
direction extending from the back surface to the front
15 surface of the multilayer substrate is defined as a Z
direction (not illustrated), and a direction orthogonal to
the X direction and the Z direction is defined as a Y
direction. In FIG. 7, the second signal terminal
connection patterns 113-1 and 113-2 and the external
20 connection terminal 61 are wired. The second signal
terminal connection patterns 113-1 and 113-2 share common
wiring from the external connection terminal 61 to a point
T. The wiring branches off from the point T into
connection to the second signal terminal connection pattern
25 113-1 and the second signal terminal connection pattern
113-2. That is, the point T is a branch point. For two
semiconductor modules, the point T is a midpoint of the
wiring between the second signal terminal connection
patterns 113-1 and 113-2. With the wiring laid as
30 described above, a wiring length from the external
connection terminal 61 to the second signal terminal
connection pattern 113-1 and a wiring length from the
external connection terminal 61 to the second signal
22
terminal connection pattern 113-2 can be equal to each
other. In FIG. 7, the wiring from the external connection
terminal 61 to the second signal terminal connection
patterns is formed in the same layer of the multilayer
5 substrate 100, but may not be formed in the same layer.
Different layers of the multilayer substrate 100 may be
used. For example, the wiring from the external connection
terminal 61 to the point T and the wiring between 113-1 and
113-2 may be in different layers.
10 [0040] Descriptions and illustrations of the fourth
signal terminal connection patterns 114-1 and 114-2 are
similar to those of the first signal terminal connection
patterns 113-1 and 113-2, and thus will be omitted.
[0041] Wiring, which is a combination of wiring from the
15 external connection terminal 61 to the first signal
terminal of the semiconductor module 10-1 and wiring from
the second signal terminal of the semiconductor module 10-1
to the external connection terminal 61, is referred to as
gate wiring.
20 [0042] The gate wiring for the semiconductor element 30-
1 of the semiconductor module 10-1 is a combination of
wiring from the external connection terminal 61 to the
first signal terminal connection pattern 111-1 and wiring
from the second signal terminal connection pattern 113-1 to
25 the external connection terminal 61.
[0043] Similarly, wiring, which is a combination of
wiring from the external connection terminal 61 to the
first signal terminal of the semiconductor module 10-2 and
wiring from the second signal terminal of the semiconductor
30 module 10-2 to the external connection terminal 61, is
referred to as gate wiring. The gate wiring for the
semiconductor element 30-2 of the semiconductor module 10-2
is a combination of wiring from the external connection
23
terminal 61 to the first signal terminal connection pattern
111-2 and wiring from the second signal terminal connection
pattern 113-2 to the external connection terminal 61.
[0044] With the external connection terminal, the first
5 signal terminal connection patterns, and the second signal
terminal connection patterns laid as described above, a
length of the gate wiring for the semiconductor element 30-
1 of the semiconductor module 10-1 and a length of the gate
wiring for the semiconductor element 30-2 of the
10 semiconductor module 10-2 can be the same. Since the
length of the gate wiring for the semiconductor element 30-
1 of the semiconductor module 10-1 and the length of the
gate wiring for the semiconductor element 30-2 of the
semiconductor module 10-2 can be equal to each other, it is
15 possible to reduce an imbalance in current between the
semiconductor element 30-1 and the semiconductor element
30-2.
[0045] A wiring inductance of the gate wiring for the
semiconductor element 30-1 of the semiconductor module 10-1
20 and a wiring inductance of the gate wiring for the
semiconductor element 30-2 of the semiconductor module 10-2
can be equal to each other. Since the wiring inductance of
the gate wiring for the semiconductor element 30-1 of the
semiconductor module 10-1 and the wiring inductance of the
25 gate wiring for the semiconductor element 30-2 of the
semiconductor module 10-2 can be equal to each other, it is
possible to reduce an imbalance in current between the
semiconductor element 30-1 and the semiconductor element
30-2.
30 [0046] Although not described, the gate wiring for the
semiconductor element 40-1 of the semiconductor module 10-1
and the gate wiring for the semiconductor element 40-2 of
the semiconductor module 10-2 are laid in the same manner
24
as discussed above, such that a wiring inductance of the
gate wiring for the semiconductor element 40-1 of the
semiconductor module 10-1 and a wiring inductance of the
gate wiring for the semiconductor element 40-2 of the
5 semiconductor module 10-2 can be equal to each other. As a
result, it is possible to reduce an imbalance in current
between the semiconductor element 40-1 and the
semiconductor element 40-2.
[0047] Inductances of wiring, which are a source of
10 voltage drops, provide the equal amounts of voltage drops
caused by the individual wiring inductances if the
inductances of wiring are equal to each other, so that
flows of current through the wiring can be equal to one
another.
15 [0048] In the first embodiment, the lengths of wiring
are considered to be equal to each other if an imbalance in
current between the semiconductor modules exists to such an
extent as to have substantially no influence. Similarly,
the inductances of wiring are considered to be equal to
20 each other if an imbalance in current between the
semiconductor modules exists to such an extent as to have
substantially no influence.
[0049] The gate wiring, which is formed in the
multilayer substrate 100 as described above to reduce an
25 imbalance in current between the semiconductor modules, can
be achieved in a smaller number of layers.
[0050] It is preferable for wiring patterns to have
substantially the same widths in forming the gate wiring in
the multilayer substrate 100 as described above. In the
30 multilayer substrate 100 according to the first embodiment,
a distance in the Z direction between the external
connection terminal and the first signal terminal
connection patterns is preferably short, and a distance in
25
the Z direction between the external connection terminal
and the second signal terminal connection patterns is
preferably short. That is, the external connection
terminal and the first signal terminal connection patterns,
5 and the external connection terminal and the second signal
terminal connection patterns, wiring are preferably laid
such that wiring patterns overlap when the multilayer
substrate 100 is viewed from the positive direction of the
Z direction. With the wiring laid as described above, it
10 is possible to achieve a configuration that is less
susceptible to noise. The above description is made as to
the example in which two semiconductor modules are arranged
in parallel, but a similar configuration can be applied
even when three or more semiconductor modules are arranged
15 in parallel. In the above description, the wiring lengths
from the branch point (point S) to the first signal
terminal connection patterns of the two semiconductor
modules are equal to each other, and the wiring lengths
from the branch point (point T) to the second signal
20 terminal connection patterns of the two semiconductor
modules are equal to each other. In a case of three
semiconductor modules, similarly, the wiring lengths from
the branch point to the first signal terminal connection
patterns of the three semiconductor modules are equal to
25 one another, and the wiring lengths from the branch point
to the second signal terminal connection patterns of the
three semiconductor modules are equal to one another. As a
result, the individual gate wiring lengths for the three
semiconductor modules can be identical to one another.
30 Since the individual gate wiring lengths for the three
semiconductor modules are equal to one another, it is
possible to reduce an imbalance in current among the three
semiconductor elements. The above description is made as
26
to the example in which the branch points are used for the
wiring from the external connection terminal to the first
signal terminal connection patterns of the semiconductor
modules and the wiring from the external connection
5 terminal to the second signal terminal connection patterns
of the semiconductor modules, but there is no limitation
thereto. The wiring from the external connection terminal
to the first signal terminal connection patterns of the
semiconductor modules and the wiring from the external
10 connection terminal to the second signal terminal
connection patterns of the semiconductor modules may be
configured without using the branch points. Even in that
case, the individual gate wiring lengths are equal to one
another, thereby making it possible to reduce an imbalance
15 in current among the three semiconductor elements.
[0051] The semiconductor module parallel circuit
according to the first embodiment includes: a first power
semiconductor module; a second power semiconductor module;
and a multilayer substrate that interconnects a plurality
20 of the power semiconductor modules, each of the power
semiconductor modules includes: a power semiconductor
switching element; a first signal terminal connected to a
gate potential of the power semiconductor switching
element; and a second signal terminal connected to a source
25 potential of the power semiconductor switching element, the
multilayer substrate includes: an external connection
terminal; a first signal terminal connection pattern for
the first power semiconductor module, the first signal
terminal connection pattern for the first power
30 semiconductor module being connected to the first signal
terminal of the first power semiconductor module; a second
signal terminal connection pattern for the first power
semiconductor module, the second signal terminal connection
27
pattern for the first power semiconductor module being
connected to the second signal terminal of the first power
semiconductor module; a first signal terminal connection
pattern for the second power semiconductor module, the
5 first signal terminal connection pattern for the second
power semiconductor module being connected to the first
signal terminal of the second power semiconductor module;
and a second signal terminal connection pattern for the
second power semiconductor module, the second signal
10 terminal connection pattern for the second power
semiconductor module being connected to the second signal
terminal of the second power semiconductor module, and an
inductance of gate wiring for the first power semiconductor
module from the external connection terminal to the first
15 signal terminal connection pattern for the first power
semiconductor module and from the second signal terminal
connection pattern for the first power semiconductor module
to the external connection terminal, and an inductance of
gate wiring for the second power semiconductor module from
20 the external connection terminal to the first signal
terminal connection pattern for the second power
semiconductor module and from the second signal terminal
connection pattern for the second power semiconductor
module to the external connection terminal are equal to
25 each other, whereby it is possible to reduce an imbalance
in current between the semiconductor modules.
[0052] The semiconductor module parallel circuit
according to the first embodiment includes: a first power
semiconductor module; a second power semiconductor module;
30 and a multilayer substrate that interconnects a plurality
of the power semiconductor modules, each of the power
semiconductor modules includes: a power semiconductor
switching element; a first signal terminal connected to a
28
gate potential of the power semiconductor switching
element; and a second signal terminal connected to a source
potential of the power semiconductor switching element, the
multilayer substrate includes: an external connection
5 terminal; a first signal terminal connection pattern for
the first power semiconductor module, the first signal
terminal connection pattern for the first power
semiconductor module being connected to the first signal
terminal of the first power semiconductor module; a second
10 signal terminal connection pattern for the first power
semiconductor module, the second signal terminal connection
pattern for the first power semiconductor module being
connected to the second signal terminal of the first power
semiconductor module; a first signal terminal connection
15 pattern for the second power semiconductor module, the
first signal terminal connection pattern for the second
power semiconductor module being connected to the first
signal terminal of the second power semiconductor module;
and a second signal terminal connection pattern for the
20 second power semiconductor module, the second signal
terminal connection pattern for the second power
semiconductor module being connected to the second signal
terminal of the second power semiconductor module, and a
length of gate wiring for the first power semiconductor
25 module from the external connection terminal to the first
signal terminal connection pattern for the first power
semiconductor module and from the second signal terminal
connection pattern for the first power semiconductor module
to the external connection terminal, and a length of gate
30 wiring for the second power semiconductor module from the
external connection terminal to the first signal terminal
connection pattern for the second power semiconductor
module and from the second signal terminal connection
29
pattern for the second power semiconductor module to the
external connection terminal are equal to each other,
whereby it is possible to reduce an imbalance in current
between the semiconductor modules, and to reduce shortening
5 of the lifetime of semiconductor elements.
[0053] In the semiconductor module parallel circuit
according to the first embodiment, the gate wiring length
for the first power semiconductor module from the external
connection terminal to the first signal terminal connection
10 pattern for the first power semiconductor module and from
the second signal terminal connection pattern for the first
power semiconductor module to the external connection
terminal, and the gate wiring length for the second power
semiconductor module from the external connection terminal
15 to the first signal terminal connection pattern for the
second power semiconductor module and from the second
signal terminal connection pattern for the second power
semiconductor module to the external connection terminal
are equal to each other, whereby it is possible to reduce
20 the imbalance in current between the semiconductor modules.
[0054] In the semiconductor module parallel circuit
according to the first embodiment, the wiring from the
external connection terminal to the first signal terminal
connection pattern for the first power semiconductor module
25 and the wiring from the external connection terminal to the
first signal terminal connection pattern for the second
power semiconductor module are formed in a first layer of
the multilayer substrate, and the wiring from the second
signal terminal connection pattern for the first power
30 semiconductor module to the external connection terminal
and the wiring from the second signal terminal connection
pattern for the second power semiconductor module to the
external connection terminal are formed in a second layer
30
of the multilayer substrate, whereby it is possible to
reduce an imbalance in current between the semiconductor
modules.
[0055] The semiconductor module connection substrate
5 according to the first embodiment includes: an external
connection terminal; a first signal terminal connection
pattern for a first power semiconductor module, the first
signal terminal connection pattern for the first power
semiconductor module being provided for connection to a
10 first signal terminal of the first power semiconductor
module; a second signal terminal connection pattern for the
first power semiconductor module, the second signal
terminal connection pattern for the first power
semiconductor module being provided for connection to a
15 second signal terminal of the first power semiconductor
module; a first signal terminal connection pattern for a
second power semiconductor module, the first signal
terminal connection pattern for the second power
semiconductor module being provided for connection to a
20 first signal terminal of the second power semiconductor
module; and a second signal terminal connection pattern for
the second power semiconductor module, the second signal
terminal connection pattern for the second power
semiconductor module being provided for connection to a
25 second signal terminal of the second power semiconductor
module, and an inductance of gate wiring for the first
power semiconductor module from the external connection
terminal to the first signal terminal connection pattern
for the first power semiconductor module and from the
30 second signal terminal connection pattern for the first
power semiconductor module to the external connection
terminal, and an inductance of gate wiring for the second
power semiconductor module from the external connection
31
terminal to the first signal terminal connection pattern
for the second power semiconductor module and from the
second signal terminal connection pattern for the second
power semiconductor module to the external connection
5 terminal are equal to each other, whereby it is possible to
reduce an imbalance in current between the semiconductor
modules.
[0056] Second Embodiment
Parallel connection of the semiconductor module 10-1
10 and the semiconductor module 10-2 through a multilayer
substrate 200 of a semiconductor module parallel circuit 2
in a second embodiment will be described.
[0057] FIG. 8 is a view illustrating a configuration of
the semiconductor module parallel circuit 2 in which two
15 semiconductor modules are disposed in parallel to each
other. FIG. 9 is a view illustrating the multilayer
substrate 200 of the semiconductor module parallel circuit
2 in the second embodiment. FIG. 10 is a schematic view of
a cross section of the multilayer substrate 200 of FIG. 9
20 taken along line A-A'. In FIG. 10, a direction extending
from the external connection terminal 61 of the multilayer
substrate 200 to each semiconductor module is defined as an
X direction, a direction extending from a back surface to a
front surface of the multilayer substrate is defined as a Z
25 direction, and a direction orthogonal to the X direction
and the Z direction is defined as a Y direction (not
illustrated). The multilayer substrate 200 is formed of
three layers: a first layer 201; a second layer 202; and a
third layer 203. In the X direction, a coordinate position
30 of the external connection terminal 61 is set to 0. In the
Z direction, a coordinate position of the third layer 203
of the multilayer substrate 200 in contact with the
semiconductor modules 10-1 and 10-2 is set to 0. The first
32
layer is defined as a front surface, and the third layer is
defined as a back surface. The first layer and the third
layer may be invisible layers. The semiconductor module
10-1 and the semiconductor module 10-2 are disposed in
5 parallel to each other in the X direction, and the
semiconductor module 10-1 and the semiconductor module 10-2
are arranged in this order from a side closer to the
external connection terminal 61.
[0058] In FIG. 10, a solid line indicates wiring from
10 the external connection terminal 61 to the first signal
terminal connection pattern, and a broken line indicates
wiring from the second signal terminal connection pattern
to the external connection terminal 61. The first signal
terminal connection patterns 111-1 and 111-2 and the second
15 signal terminal connection patterns 113-1 and 113-2 are
formed in the third layer 203 of the multilayer substrate
200 for the purpose of connection to individual signal
terminals for the individual semiconductor modules.
[0059] Wiring formed in the first layer 201 of the
20 multilayer substrate 200 is referred to as gate return
wiring, wiring formed in the second layer 202 is referred
to as gate forward wiring, and wiring formed in the third
layer 203 is referred to as output wiring. The gate
forward wiring is connected to the external connection
25 terminal 61. The gate forward wiring is connected to the
gate return wiring. The gate return wiring is connected to
the first signal terminal connection patterns 111-1 and
111-2. Wiring from the gate return wiring to the first
signal terminal connection pattern 111-1 is not connected
30 to the gate forward wiring. Similarly, wiring from the
gate return wiring to the first signal terminal connection
pattern 111-2 is not connected to the gate forward wiring.
A position in the X direction where the gate return wiring
33
and the first signal terminal connection pattern 111-2 are
connected to each other is closer to the external
connection terminal 61 with respect to the X direction than
a position in the X direction where the gate forward wiring
5 and the gate return wiring are connected to each other. In
other words, the gate forward wiring formed in the second
layer 202 is connected to the gate return wiring formed in
the first layer 201, and the gate return wiring is
connected to the first signal terminal connection pattern
10 111-2 at the position offset in a direction opposite to the
X direction from the position where the gate forward wiring
formed in the second layer 202 is connected to the gate
return wiring formed in the first layer 201.
[0060] The position in the X direction where the gate
15 return wiring and the first signal terminal connection
pattern 111-2 are connected to each other is referred to as
a branch point Q.
[0061] The second signal terminal connection patterns
113-1 and 113-2 are connected to the output wiring. A
20 position in the X direction where the second signal
terminal connection pattern 113-1 is connected to the
output wiring is closer to the external connection terminal
61 with respect to the X direction than a position in the X
direction where the second signal terminal connection
25 pattern 113-2 is connected to the output wiring. The
output wiring is connected to the external connection
terminal 61.
[0062] The position in the X direction where the second
signal terminal connection pattern 113-1 is connected to
30 the output wiring is referred to as a junction P.
[0063] When a wiring length from the external connection
terminal 61 to the first signal terminal connection pattern
111-1 is denoted by Len1g and a wiring length from the
34
second signal terminal connection pattern 113-1 to the
external connection terminal 61 is denoted by Len1s, a
wiring length Len1 of gate wiring for the semiconductor
module 10-1 is Len1g+Len1s. Similarly, when a wiring
5 length from the external connection terminal 61 to the
first signal terminal connection pattern 111-2 is denoted
by Len2g and a wiring length from the second signal
terminal connection pattern 113-2 to the external
connection terminal 61 is denoted by Len2s, a wiring length
10 Len2 of gate wiring of the semiconductor module 10-2 is
Len2g+Len2s. In the second embodiment, the gate wiring is
formed such that the gate wiring length (wiring length
Len1) for the first power semiconductor module from the
external connection terminal 61 to the first signal
15 terminal connection pattern for the first power
semiconductor module and from the second signal terminal
connection pattern for the first power semiconductor module
to the external connection terminal, and the gate wiring
length (wiring length Len2) for the second power
20 semiconductor module from the external connection terminal
to the first signal terminal connection pattern for the
second power semiconductor module and from the second
signal terminal connection pattern for the second power
semiconductor module to the external connection terminal
25 are equal to each other (Len1=Len2). That is, the gate
wiring is formed such that a wiring inductance generated in
the gate wiring for the semiconductor module 10-1 and a
wiring inductance generated in the gate wiring for the
semiconductor module 10-2 are equal to each other. Note
30 that, for example, the first power semiconductor module is
the semiconductor module 10-1, and the second power
semiconductor module is the semiconductor module 10-2.
[0064] In FIG. 10, Len1g is a wiring length of wiring
35
from the external connection terminal 61 to the first
signal terminal connection pattern 111-1. Len1s is a
wiring length of a combination of wiring from the second
signal terminal connection pattern 113-1 to the junction P
5 and wiring from the junction P to the external connection
terminal 61. Len2g is a wiring length of a combination of
wiring from the external connection terminal 61 to the
branch point Q and wiring from the branch point Q to the
first signal terminal connection pattern 111-2. Len2s is a
10 wiring length of wiring from the second signal terminal
connection pattern 113-2 to the external connection
terminal 61.
[0065] In the second embodiment, the wiring is formed as
described above, such that the wiring length of the gate
15 wiring for the semiconductor module 10-1 and the wiring
length of the gate wiring for the semiconductor module 10-2
can be equal to each other. That is, the gate wiring is
formed such that Len1=Len2 holds true. The wiring
inductance generated in the gate wiring for the
20 semiconductor module 10-1 and the wiring inductance
generated in the gate wiring for the semiconductor module
10-2 can be equal to each other.
[0066] Next, a gate drive current in the semiconductor
module parallel circuit 2 will be described. A current
25 input from the external connection terminal 61 flows
through the gate forward wiring formed in the second layer
202 of the multilayer substrate 200 and then through the
gate return wiring formed in the first layer 201 of the
multilayer substrate 200. Next, the current branches at
30 the branch point Q of the gate return wiring to provide
flows of current into the first signal terminal connection
pattern 111-1 and the first signal terminal connection
pattern 111-2.
36
[0067] One of the branched gate drive currents flows to
the first signal terminal 11-1 of the semiconductor module
10-1 via the first signal terminal connection pattern 111-1,
and similarly, the other flows to the first signal terminal
5 11-2 of the semiconductor module 10-2 via the first signal
terminal connection pattern 111-2.
[0068] Next, a current output from the second signal
terminal 13-1 of the semiconductor module 10-1 flows into
the output wiring of the multilayer substrate 200 via the
10 second signal terminal connection pattern 113-1.
Similarly, a current output from the second signal terminal
13-2 of the semiconductor module 10-2 flows into the output
wiring of the multilayer substrate 200 via the second
signal terminal connection pattern 113-2. The current
15 output from the second signal terminal connection pattern
113-2 merges with the current output from the second signal
terminal connection pattern 113-1 at the junction P on the
output wiring. The merged current is output from the
external connection terminal 61.
20 [0069] FIG. 11 is a view illustrating a gate drive
current flowing through each layer of the multilayer
substrate 200. When a current flowing through the gate
forward wiring is denoted by Ig12, a current flowing from
the branch point Q to the first signal terminal connection
25 pattern 111-1 is denoted by I1g, and a current flowing from
the branch point Q to the first signal terminal connection
pattern 111-2 is denoted by I2g, formula (1) below holds
true.
Ig12=I1g+I2g ··· (1)
30 Currents input to the first signal terminals of the
semiconductor modules 10-1 and 10-2 can be approximated as
in formula (2) below.
I1g=I2g=Ig ··· (2)
37
Formula (3) below is derived from formulas (1) and (2).
Ig12=2Ig ··· (3)
From formulas (2) and (3), the currents I1g and I2g
branched at the branch point Q and flowing therefrom
5 through the gate return wiring are each 1/2 of the current
Ig12 flowing through the gate forward wiring. In other
words, the current Ig12 flowing through the gate forward
wiring is a current (2Ig) that is twice the current Ig (I1g,
I2g) branched at the branch point Q and flowing therefrom.
10 [0070] Next, when a current flowing through the output
wiring is denoted by Is12, a current flowing from the
second signal terminal connection pattern 113-2 is denoted
by I2s, and a current flowing from the second signal
terminal connection pattern 113-1 is denoted by I1s,
15 formula (4) below holds true.
I1s+I2s=Is12 ··· (4)
Currents output from the second signal terminals of
the semiconductor modules 10-1 and 10-2 can be approximated
as in formula (5).
20 I1s=I2s=Is ··· (5)
Formula (6) below is derived from formulas (4) and (5).
Is12=2Is ··· (6)
From formulas (5) and (6), the currents I1s and I2s
flowing through the output wiring before merging at the
25 junction P are each 1/2 of the current Is12 flowing through
the output wiring. In other words, the current Is12 flowing
through the output wiring is a current (2Is) that is twice
the current Is (I1s, I2s) flowing before the merging at the
junction P.
30 [0071] The current (Ig) flowing from the branch point Q
to the first signal terminal of the semiconductor module
10-1 and the current (Is) flowing from the second signal
terminal of the semiconductor module 10-2 to the junction P
38
can be equal to each other. That is, a voltage drop amount
in wiring extending from the branch point Q to the first
signal terminal of the semiconductor module 10-1 and a
voltage drop amount in wiring extending from the second
5 signal terminal of the semiconductor module 10-2 to the
junction P can be equal to each other.
[0072] In the second embodiment, a current, which is the
sum of the gate currents flowing through the first signal
terminals of the semiconductor modules 10-1 and 10-2, flows
10 through the gate forward wiring formed in the multilayer
substrate 200, such that wiring inductances of the gate
wiring for the semiconductor module 10-1 and the gate
wiring for the semiconductor module 10-2 can be equal to
each other.
15 [0073] Since the wiring inductance of the gate wiring
for the semiconductor module 10-1 and the wiring inductance
of the gate wiring for the semiconductor module 10-2 can be
equal to each other, it is possible to reduce an imbalance
in current generated between the semiconductor modules when
20 the semiconductor modules are driven in parallel.
[0074] It is preferable to adjust wiring patterns to
have substantially the same widths in forming the gate
wiring in the multilayer substrate 200.
[0075] In the second embodiment, the wiring to the first
25 signal terminals of the semiconductor modules is formed in
the two layers of the multilayer substrate 200, such that
the gate wiring lengths for the semiconductor modules can
be equal to each other.
[0076] In the second embodiment, the lengths of wiring
30 are considered to be equal to each other if an imbalance in
current between the semiconductor modules exists to such an
extent as to have substantially no influence. Similarly,
the inductances of wiring are considered to be equal to
39
each other if an imbalance in current between the
semiconductor modules exists to such an extent as to have
substantially no influence.
[0077] Although not described, the gate wiring for the
5 semiconductor element 40-1 of the semiconductor module 10-1
and the gate wiring for the semiconductor element 40-2 of
the semiconductor module 10-2 are laid in the same manner
as discussed above, such that a wiring inductance of the
gate wiring for the semiconductor element 40-1 of the
10 semiconductor module 10-1 and a wiring inductance of the
gate wiring for the semiconductor element 40-2 of the
semiconductor module 10-2 can be equal to each other. As a
result, it is possible to reduce an imbalance in current
between the semiconductor element 40-1 and the
15 semiconductor element 40-2.
[0078] In the second embodiment, the gate return wiring
is formed in the first layer 201 of the multilayer
substrate 200, and the output wiring is formed in the third
layer 203 of the multilayer substrate 200. Alternatively,
20 the output wiring may be formed in the first layer 201 of
the multilayer substrate 200, and the gate return wiring
may be formed in the third layer 203 of the multilayer
substrate 200.
[0079] In the semiconductor module parallel circuit
25 according to the second embodiment, the wiring from the
external connection terminal to the first signal terminal
connection pattern for the first power semiconductor module
and the wiring from the external connection terminal to the
first signal terminal connection pattern for the second
30 power semiconductor module are formed in the first layer
201 and the third layer 202 of the multilayer substrate,
whereby it is possible to reduce an imbalance in current
between the semiconductor modules.
40
[0080] Third Embodiment
The first and second embodiments described above give
an example in which two semiconductor modules are disposed
in parallel to each other. A third embodiment described
5 below gives an example in which three semiconductor modules
are disposed in parallel to one another. FIG. 12 is a view
illustrating a configuration of a semiconductor module
parallel circuit 3 in which three semiconductor modules are
disposed in parallel to one another. The semiconductor
10 modules 10-1 and 10-2, and a semiconductor module 10-3 are
arranged in parallel. The third embodiment differs from
the first and second embodiments in that the semiconductor
module 10-3 is added. The semiconductor modules 10-1, 10-2,
and 10-3 are connected to a multilayer substrate 300 and
15 driven in parallel.
[0081] FIG. 13 is a view illustrating the multilayer
substrate 300 of the semiconductor module parallel circuit
3 in the third embodiment. In FIG. 13, the multilayer
substrate 300 differs from the multilayer substrates in the
20 first and second embodiments in that a first signal
terminal connection pattern 111-3, a second signal terminal
connection pattern 113-3, a third signal terminal
connection pattern 112-3, and a fourth signal terminal
connection pattern 114-3 connected to the semiconductor
25 module 10-3 are formed.
[0082] The first signal terminal connection pattern 111-
3, the second signal terminal connection pattern 113-3, the
third signal terminal connection pattern 112-3, and the
fourth signal terminal connection pattern 114-3 are
30 patterns for connection to the first signal terminal 11-1,
the second signal terminal 13-1, the third signal terminal
12-1, and the fourth signal terminal 14-1 of the
semiconductor module 10-3, respectively.
41
[0083] FIG. 14 is a schematic view of a cross section of
the multilayer substrate 300 of FIG. 13 taken along line BB'. In FIG. 14, a direction extending from the external
connection terminal 61 of the multilayer substrate 300 to
5 each semiconductor module is defined as an X direction, a
direction extending from a back surface to a front surface
of the multilayer substrate 300 is defined as a Z direction,
and a direction orthogonal to the X direction and the Z
direction is defined as a Y direction (not illustrated).
10 The multilayer substrate 300 is formed of three layers: a
first layer 301; a second layer 302; and a third layer 303.
An interlayer distance between the first layer 301 and the
second layer 302 and an interlayer distance between the
second layer 302 and the third layer 303 are formed to be
15 equal to each other. In the X direction, a coordinate
position of the external connection terminal 61 is set to 0.
In the Z direction, a coordinate position of the third
layer 303 of the multilayer substrate 300 is set to 0. The
first layer is defined as a front surface, and the third
20 layer is defined as a back surface. The first layer and
the third layer may be invisible layers. The semiconductor
modules 10-1, 10-2, and 10-3 are disposed in parallel to
one another in the X direction, and the semiconductor
module 10-1, the semiconductor module 10-2, and the
25 semiconductor module 103 are arranged in this order from a
side closer to the external connection terminal 61.
[0084] In FIG. 14, a solid line indicates wiring from
the external connection terminal 61 to the first signal
terminal connection pattern, and a broken line indicates
30 wiring from the second signal terminal connection pattern
to the external connection terminal 61. The first signal
terminal connection patterns 111-1, 111-2, and 111-3 and
the second signal terminal connection patterns 113-1, 113-2,
42
and 113-3 are formed in the third layer 303 of the
multilayer substrate 300 for the purpose of connection to
individual signal terminals for the individual
semiconductor modules.
5 [0085] Wiring formed in the first layer 301 of the
multilayer substrate 300 is referred to as gate return
wiring, wiring formed in the second layer 302 is referred
to as gate forward wiring, and wiring formed in the third
layer 303 is referred to as output wiring. The gate
10 forward wiring is connected to the external connection
terminal 61. The gate forward wiring is connected to the
gate return wiring. The gate return wiring is connected to
the first signal terminal connection patterns 111-1, 111-2,
and 111-3. Wiring from the gate return wiring to the first
15 signal terminal connection pattern 111-1 is not connected
to the gate forward wiring. Similarly, wiring from the
gate return wiring to the first signal terminal connection
pattern 111-2 and wiring from the gate return wiring to the
first signal terminal connection pattern 111-3 are not
20 connected to the gate forward wiring. A position in the X
direction where the gate return wiring and the first signal
terminal connection pattern 111-3 are connected to each
other is closer to the external connection terminal 61 with
respect to the X direction than a position in the X
25 direction where the gate forward wiring and the gate return
wiring are connected to each other. In other words, the
gate forward wiring formed in the second layer 302 is
connected to the gate return wiring formed in the first
layer 301, and the gate return wiring is connected to the
30 first signal terminal connection pattern 111-3 at the
position offset in a direction opposite to the X direction
from the position where the gate forward wiring formed in
the second layer 302 is connected to the gate return wiring
43
formed in the first layer 301. A position in the X
direction where the gate return wiring and the first signal
terminal connection pattern 111-2 are connected to each
other is closer to the external connection terminal 61 with
5 respect to the X direction than the position in the X
direction where the gate return wiring and the first signal
terminal connection pattern 111-3 are connected to each
other.
[0086] The position in the X direction where the gate
10 return wiring and the first signal terminal connection
pattern 111-3 are connected to each other is referred to as
a branch point Q1. The position in the X direction where
the gate return wiring and the first signal terminal
connection pattern 111-2 are connected to each other is
15 referred to as a branch point Q2.
[0087] The second signal terminal connection patterns
113-1, 113-2, and 113-3 are connected to the output wiring.
A position in the X direction where the second signal
terminal connection pattern 113-2 is connected to the
20 output wiring is closer to the external connection terminal
61 with respect to the X direction than a position in the X
direction where the second signal terminal connection
pattern 113-3 is connected to the output wiring. A
position in the X direction where the second signal
25 terminal connection pattern 113-1 is connected to the
output wiring is closer to the external connection terminal
61 with respect to the X direction than a position in the X
direction where the second signal terminal connection
pattern 113-2 is connected to the output wiring. The
30 output wiring is connected to the external connection
terminal 61.
[0088] The position in the X direction where the second
signal terminal connection pattern 113-2 is connected to
44
the output wiring is referred to as a junction P1, and the
position in the X direction where the second signal
terminal connection pattern 113-1 is connected to the
output wiring is referred to as a junction P2.
5 [0089] When a wiring length from the external connection
terminal 61 to the first signal terminal connection pattern
111-1 is denoted by Len1g and a wiring length from the
second signal terminal connection pattern 113-1 to the
external connection terminal 61 is denoted by Len1s, a
10 wiring length Len1 of gate wiring for the semiconductor
module 10-1 is Len1g+Len1s. Similarly, when a wiring
length from the external connection terminal 61 to the
first signal terminal connection pattern 111-2 is denoted
by Len2g and a wiring length from the second signal
15 terminal connection pattern 113-2 to the external
connection terminal 61 is denoted by Len2s, a wiring length
Len2 of gate wiring for the semiconductor module 10-2 is
Len2g+Len2s. Similarly, when a wiring length from the
external connection terminal 61 to the first signal
20 terminal connection pattern 111-3 is denoted by Len3g and a
wiring length from the second signal terminal connection
pattern 113-3 to the external connection terminal 61 is
denoted by Len3s, a wiring length Len3 of gate wiring for
the semiconductor module 10-3 is Len3g+Len3s.
25 [0090] In the third embodiment, the gate wiring is
formed such that the gate wiring length (wiring length
Len1) for the first power semiconductor module from the
external connection terminal 61 to the first signal
terminal connection pattern for the first power
30 semiconductor module and from the second signal terminal
connection pattern for the first power semiconductor module
to the external connection terminal 61, the gate wiring
length (wiring length Len2) for the second power
45
semiconductor module from the external connection terminal
61 to the first signal terminal connection pattern for the
second power semiconductor module and from the second
signal terminal connection pattern for the second power
5 semiconductor module to the external connection terminal 61,
and the gate wiring length (wiring length Len3) for a third
power semiconductor module from the external connection
terminal 61 to the first signal terminal connection pattern
for the third power semiconductor module and from the
10 second signal terminal connection pattern for the third
power semiconductor module to the external connection
terminal 61 are equal to one another (Len1=Len2=Len3).
That is, the gate wiring is formed such that wiring
inductances generated in the gate wiring for the
15 semiconductor module 10-1 and the gate wiring for the
semiconductor module 10-2, and a wiring inductance
generated in the gate wiring for the semiconductor module
10-3 are equal to one another.
[0091] It is preferable to adjust wiring patterns to
20 have substantially the same widths in forming the gate
wiring in the multilayer substrate 300.
[0092] In FIG. 14, Len1g is a wiring length of wiring
from the external connection terminal 61 to the first
signal terminal connection pattern 111-1. Len1s is a
25 wiring length of a combination of wiring from the second
signal terminal connection pattern 113-1 to the junction P2
and wiring from the junction P2 to the external connection
terminal 61. Len2g is a wiring length of a combination of
wiring from the external connection terminal 61 to the
30 branch point Q2 and wiring from the branch point Q2 to the
first signal terminal connection pattern 111-2. Len2s is a
wiring length of a combination of wiring from the second
signal terminal connection pattern 113-2 to the junction P1
46
and wiring from the junction P1 to the external connection
terminal 61. Len3g is a wiring length of a combination of
wiring from the external connection terminal 61 to the
branch point Q1 and wiring from the branch point Q1 to the
5 first signal terminal connection pattern 111-3. Len3s is a
wiring length of wiring from the second signal terminal
connection pattern 113-3 to the external connection
terminal 61.
[0093] In the third embodiment, the wiring is formed as
10 described above, such that the wiring length of the gate
wiring for the semiconductor module 10-1, the wiring length
of the gate wiring for the semiconductor module 10-2, and
the wiring length of the gate wiring for the semiconductor
module 10-3 can be equal to one another. That is, the gate
15 wiring is formed such that Len1=Len2=Len3 holds true.
Since the gate wiring lengths of the semiconductor modules
10-1, 10-2, and 10-3 can be equal to one another, it is
possible to reduce an imbalance in current generated among
the semiconductor modules when the semiconductor modules
20 are driven in parallel.
[0094] In the third embodiment, the wiring length of the
gate wiring for the semiconductor module 10-1, the wiring
length of the gate wiring for the semiconductor module 10-2,
and the wiring length of the gate wiring for the
25 semiconductor module 10-3 are equal to one another, such
that the amounts of voltage drop due to the wiring
inductances can be equal to one another, whereby it is
possible to reduce an imbalance in current generated among
the semiconductor modules when the semiconductor modules
30 are driven in parallel.
[0095] In the third embodiment, the wiring to the first
signal terminals of the semiconductor modules is formed in
the two layers of the multilayer substrate 300, such that
47
the gate wiring lengths of the semiconductor modules can be
equal to one another.
[0096] In the third embodiment, the lengths of wiring
are considered to be equal to one another if an imbalance
5 in current among the semiconductor modules exists to such
an extent as to have substantially no influence. Similarly,
the inductances of wiring are considered to be equal to one
another if an imbalance in current among the semiconductor
modules exists to such an extent as to have substantially
10 no influence.
[0097] In the third embodiment, the gate return wiring
is formed in the first layer 301 of the multilayer
substrate 300, and the output wiring is formed in the third
layer 303 of the multilayer substrate 300. Alternatively,
15 the output wiring may be formed in the first layer 301 of
the multilayer substrate 300, and the gate return wiring
may be formed in the third layer 303 of the multilayer
substrate 300.
[0098] The semiconductor module parallel circuit
20 according to the third embodiment includes: a first power
semiconductor module; a second power semiconductor module;
a third power semiconductor module; and a multilayer
substrate that interconnects a plurality of the power
semiconductor modules, each of the power semiconductor
25 modules includes: a power semiconductor switching element;
a first signal terminal connected to a gate potential of
the power semiconductor switching element; and a second
signal terminal connected to a source potential of the
power semiconductor switching element, the multilayer
30 substrate includes: an external connection terminal; a
first signal terminal connection pattern for the first
power semiconductor module, the first signal terminal
connection pattern for the first power semiconductor module
48
being connected to the first signal terminal of the first
power semiconductor module; a second signal terminal
connection pattern for the first power semiconductor module,
the second signal terminal connection pattern for the first
5 power semiconductor module being connected to the second
signal terminal of the first power semiconductor module; a
first signal terminal connection pattern for the second
power semiconductor module, the first signal terminal
connection pattern for the second power semiconductor
10 module being connected to the first signal terminal of the
second power semiconductor module; a second signal terminal
connection pattern for the second power semiconductor
module, the second signal terminal connection pattern for
the second power semiconductor module being connected to
15 the second signal terminal of the second power
semiconductor module; a first signal terminal connection
pattern for the third power semiconductor module, the first
signal terminal connection pattern for the third power
semiconductor module being connected to the first signal
20 terminal of the third power semiconductor module; and a
second signal terminal connection pattern for the third
power semiconductor module, the second signal terminal
connection pattern for the third power semiconductor module
being connected to the second signal terminal of the third
25 power semiconductor module, and an inductance of gate
wiring for the first power semiconductor module from the
external connection terminal to the first signal terminal
connection pattern for the first power semiconductor module
and from the second signal terminal connection pattern for
30 the first power semiconductor module to the external
connection terminal, an inductance of gate wiring for the
second power semiconductor module from the external
connection terminal to the first signal terminal connection
49
pattern for the second power semiconductor module and from
the second signal terminal connection pattern for the
second power semiconductor module to the external
connection terminal, and an inductance of gate wiring for
5 the third power semiconductor module from the external
connection terminal to the first signal terminal connection
pattern for the third power semiconductor module and from
the second signal terminal connection pattern for the third
power semiconductor module to the external connection
10 terminal are equal to one another, whereby it is possible
to reduce an imbalance in current among the semiconductor
modules.
[0099] Fourth Embodiment
A fourth embodiment described below gives an example
15 in which interlayer distances of a multilayer substrate are
equal to each other. A description will be made as to an
example in which two semiconductor modules are disposed in
parallel. FIG. 15 is a view illustrating a semiconductor
module parallel circuit 4 of the fourth embodiment. FIG.
20 16 is a view illustrating a multilayer substrate 400 of the
semiconductor module parallel circuit 4 in the fourth
embodiment. FIG. 17 is a schematic view of a cross section
of the multilayer substrate 400 of FIG. 16 taken along line
C-C'. A basic configuration and each wiring connection are
25 similar to those in the second embodiment. The fourth
embodiment differs from the second embodiment in respects
as will be described. In the multilayer substrate 400 of
FIG. 17, an interlayer distance between a first layer 401
and a second layer 402 and an interlayer distance between
30 the second layer 402 and a third layer 403 are formed to be
equal to each other. That is, an interlayer distance
between the layer having gate return wiring formed therein
and the layer having gate forward wiring formed therein and
50
an interlayer distance between the layer having the gate
forward wiring formed therein and the layer having output
wiring formed therein are formed to be equal to each other.
[0100] The interlayer distance between the layer having
5 the gate return wiring formed therein and the layer having
the gate forward wiring formed therein and the interlayer
distance between the layer having the gate forward wiring
formed therein and the layer having the output wiring
formed therein are formed to be equal to each other, such
10 that the influence of mutual inductances can be reduced.
[0101] A voltage drop due to a wiring inductance of the
first layer 401 can be expressed by formula (7) below.
ΔV1=L1×(diL1/dt)-M12×(diL1/dt)-M13×(diL1/dt) ··· (7)
Similarly, a voltage drop due to a wiring inductance
15 of the third layer 403 can be expressed by formula (8)
below.
ΔV3=L3×(diL3/dt)-M23×(diL3/dt)-M13×(diL3/dt) ··· (8)
L1 represents a self-inductance of the first layer 401,
L3 represents a self-inductance of the third layer 403, M13
20 represents a mutual inductance between the first layer 401
and the second layer 402, M23 represents a mutual
inductance between the second layer 402 and the third layer
403, M13 represents a mutual inductance between the first
layer 401 and the third layer 403, diL1/dt represents a
25 time differential of a current flowing through the first
layer 401, and diL3/dt represents a time differential of a
current flowing through the third layer 403.
[0102] In the fourth embodiment, since the interlayer
distance between the first layer 401 and the second layer
30 402 and the interlayer distance between the second layer
402 and the third layer 403 are formed to be equal to each
other, formula (9) below holds true.
M12=M23=M ··· (9)
51
Since a distance between the first signal connection
pattern 111-1 and the first signal connection pattern 111-2
and a distance between the second signal connection pattern
113-1 and the second signal connection pattern 113-2 are
5 formed to be equal to each other, a wiring length in the
first layer 401 and a wiring length in the third layer 403
are equal to each other, and thus formula (10) below holds
true.
L1=L3=L ··· (10)
10 Since a current flowing through the first layer 401
and a current flowing through the third layer 403 are equal
to each other, formula (11) below holds true.
diL1/dt=diL3/dt=di/dt ··· (11)
From formulas (7) to (11), the voltage drops due to
15 the wiring inductances of the first layer 401 and the third
layer 403 are expressed by formulas (12) and (13) below.
ΔV1=L×(di/dt)-M×(di/dt)-M13×(di/dt) ··· (12)
ΔV3=L×(di/dt)-M×(di/dt)-M13×(di/dt) ··· (13)
It can be seen from formulas (12) and (13) that the
20 voltage drops due to the wiring inductances of the first
layer 401 and the third layer 403 are equal to each other.
[0103] In the fourth embodiment, the interlayer distance
between the first layer 401 and the second layer 402 and
the interlayer distance between the second layer 402 and
25 the third layer 403 are formed to be equal to each other,
such that the influence of the mutual inductances can be
reduced. Since the influence of the mutual inductances can
be reduced, a wiring inductance of gate wiring for the
semiconductor module 10-1 and a wiring inductance of gate
30 wiring for the semiconductor module 10-2 can be equal to
each other. Since the wiring inductance of the gate wiring
for the semiconductor module 10-1 and the wiring inductance
of the gate wiring for the semiconductor module 10-2 can be
52
equal to each other, the amounts of voltage drops due to
the wiring inductances can be equal to each other, and it
is possible to reduce an imbalance in current generated
between the semiconductor modules when the semiconductor
5 modules are driven in parallel.
[0104] Although the fourth embodiment described above
gives an example in which two semiconductor modules are
disposed in parallel to each other, the influence of the
mutual inductances can be similarly reduced even in a case
10 where three semiconductor modules are disposed.
[0105] In the fourth embodiment, the lengths of wiring
are considered to be equal to each other if an imbalance in
current between the semiconductor modules exists to such an
extent as to have substantially no influence. Similarly,
15 the inductances of wiring are considered to be equal to
each other if an imbalance in current between the
semiconductor modules exists to such an extent as to have
substantially no influence.
[0106] Fifth Embodiment
20 A fifth embodiment is an embodiment in which the
influence of a wiring inductance is further reduced. The
fifth embodiment described below gives an example in which
three semiconductor modules are disposed in parallel to
each other. FIG. 18 is a view illustrating a semiconductor
25 module parallel circuit 5 according to the fifth embodiment.
FIG. 19 is a view illustrating a multilayer substrate 500
of the semiconductor module parallel circuit 5 in the fifth
embodiment.
[0107] FIG. 20 is a schematic view of a cross section of
30 the multilayer substrate 500 of FIG. 19 taken along line DD'. A basic configuration and each wiring connection are
similar to those in the third embodiment. The fifth
embodiment differs from the third embodiment in respects as
53
will be described. For ease of description, a position of
gate return wiring in the X direction corresponding to a
position of the first signal terminal connection pattern
111-1 in the X direction is referred to as a branch point
5 Q3. A position of the output wiring in the X direction
corresponding to a position of the second signal terminal
connection pattern 113-3 in the X direction is referred to
as a junction P3.
[0108] In the gate return wiring formed in a first layer
10 501 of the multilayer substrate 500 of the fifth embodiment,
a wiring pattern from the branch point Q1 to the branch
point Q2 is formed to have a width larger than a width of a
wiring pattern from the branch point Q2 to the branch point
Q3. In the output wiring formed in a third layer 503 of
15 the multilayer substrate 500, a wiring pattern from the
junction P1 to the junction P2 is formed to have a width
larger than a width of a wiring pattern from the junction
P3 to the junction P1.
[0109] A gate drive current in the semiconductor module
20 parallel circuit 5 will be described. A current input from
the external connection terminal 61 flows through gate
forward wiring formed in a second layer 502 of the
multilayer substrate 500 and then through the gate return
wiring formed in the first layer 501 of the multilayer
25 substrate 500. Next, the current branches in the gate
return wiring to provide flows of current into the first
signal terminal connection patterns 111-1, 111-2, and 111-3.
[0110] One of the branched gate drive currents flows to
the first signal terminal of the semiconductor module 10-1
30 via the first signal terminal connection pattern 111-1.
Similarly, another of the branched gate drive currents
flows to the first signal terminal of the semiconductor
module 10-2 via the first signal terminal connection
54
pattern 111-2, and the other of the branched gate drive
currents flows to the first signal terminal of the
semiconductor module 10-3 via the first signal terminal
connection pattern 111-3. The gate drive current, which
5 has branched off at the branch point Q1 of the gate return
wiring, flows to the first signal terminal connection
pattern 111-3. The gate drive current, which has branched
off at the branch point Q2 of the gate return wiring, flows
to the first signal terminal connection pattern 111-2.
10 [0111] Next, a current output from the second signal
terminal of the semiconductor module 10-1 flows into the
output wiring of the multilayer substrate 500 via the
second signal terminal connection pattern 113-1. Similarly,
a current output from the second signal terminal of the
15 semiconductor module 10-2 flows into the output wiring of
the multilayer substrate 500 via the second signal terminal
connection pattern 113-2. A current output from the second
signal terminal of the semiconductor module 10-3 flows into
the output wiring of the multilayer substrate 500 via the
20 second signal terminal connection pattern 113-3. The
current output from the second signal terminal connection
pattern 113-3 merges with the current output from the
second signal terminal connection pattern 113-2 at the
junction P1 of the output wiring. The currents output from
25 the second signal terminal connection pattern 113-2 and the
second signal terminal connection pattern 113-3 merge with
the current output from the second signal terminal
connection pattern 113-1 at the junction P2 of the output
wiring. The currents merged together at the junction P2 is
30 output from the external connection terminal 61.
[0112] FIG. 21 is a view illustrating a gate drive
current flowing through each layer of the multilayer
substrate 500. When a current flowing through the gate
55
forward wiring is denoted by Ig123, a current flowing from
the branch point Q2 to the first signal terminal connection
pattern 111-1 is denoted by I1g, a current flowing from the
branch point Q2 to the first signal terminal connection
5 pattern 111-2 is denoted by I2g, and a current flowing from
the branch point Q2 to the first signal terminal connection
pattern 111-3 is denoted by I3g, formula (14) below holds
true.
Ig123=I1g+I2g+Ig3 ··· (14)
10 Currents input to the first signal terminals of the
semiconductor modules 10-1, 10-2, and 10-3 can be
approximated as in formula (15) below.
I1g=I2g=I3g=Ig ··· (15)
Formula (16) below is derived from formulas (14) and
15 (15).
Ig123=3Ig ··· (16)
From formulas (15) and (16) above, the current flowing
in the gate return wiring from the branch point Q2 to the
first signal terminal connection pattern 111-1 is Ig. A
20 current flowing from the branch point Q1 to the branch
point Q2 is 2Ig.
[0113] Next, when a current flowing through the output
wiring is denoted by Is123, a current output from the second
signal terminal connection pattern 113-3 is denoted by I3s,
25 a current output from the second signal terminal connection
pattern 113-2 is denoted by I2s, and a current output from
the second signal terminal connection pattern 113-1 is
denoted by I1s, formula (17) below holds true.
I1s+I2s+I3s=Is123 ··· (17)
30 Currents output from the second signal terminals of
the semiconductor modules 10-1, 10-2, and 10-3 can be
approximated as in formula (18) below.
I1s=I2s=I3s=Is ··· (18)
56
Formula (19) below is derived from formulas (17) and
(18).
Is123=3Is ··· (19)
From formulas (18) and (19), a current flowing in the
5 output wiring from the second signal terminal connection
pattern 113-3 to the junction P1 is Is. A current flowing
from the junction P1 to the junction P2 is 2Is.
[0114] From the above description, a current flowing in
the gate return wiring from the branch point Q2 to the
10 branch point Q3 is Ig. The current flowing from the branch
point Q1 to the branch point Q2 is 2Ig. The current
flowing from the branch point Q1 to the branch point Q2 is
about twice the current flowing from the branch point Q2 to
the branch point Q3. In the gate return wiring, there
15 occurs a difference in time-differentiated amount of
current between the wiring from the branch point Q1 to the
branch point Q2 and the wiring from the branch point Q2 to
the branch point Q3. Similarly, in the output wiring, the
current flowing from the junction P1 to the junction P2 is
20 Is. A current flowing from the junction P3 to the junction
P1 is 2Is. The current flowing from the junction P1 to the
junction P2 is about twice the current flowing from the
junction P3 to the junction P1. In the output wiring,
there occurs a difference in time-differentiated amount of
25 current between the wiring from the junction P1 to the
junction P2 and the wiring from the junction P3 to the
junction P1. There occurs a difference in timedifferentiated amount of current in the wiring.
[0115] As described in the fourth embodiment, a voltage
30 drop amount of wiring is expressed by the product of a
self-inductance of wiring and a time-differentiated amount
of current as in formula (20) below. In order to simplify
the description, the influence of the mutual inductances is
57
not considered here.
ΔV=L×(di/dt) ··· (20)
L represents a self-inductance of wiring, and di/dt
represents a time-differentiated amount of current. As can
5 be seen from formula (20), a different time-differentiated
amount of current results in a different voltage drop
amount.
[0116] In the gate return wiring of the multilayer
substrate 500 of the fifth embodiment, the wiring pattern
10 from the branch point Q1 to the branch point Q2 is formed
to have a width larger than a width of the wiring pattern
from the branch point Q2 to the branch point Q3.
Increasing the wiring pattern width can reduce the selfinductance of wiring. That is, the wiring from the branch
15 point Q1 to the branch point Q2 achieves a smaller selfinductance than the wiring from the branch point Q2 to the
branch point Q3.
[0117] As can be seen from formula (20), the selfinductance of wiring is indicated by a first term of the
20 right side of formula (20), and the time-differentiated
amount of current is indicated by a second term of the
right side of formula (20). The wiring from the branch
point Q1 to the branch point Q2 provides a larger second
term of the right side of formula (20) than the wiring from
25 the branch point Q2 to the branch point Q3. However, since
the width of the wiring pattern from the branch point Q1 to
the branch point Q2 is larger than the width of the wiring
pattern from the branch point Q2 to the branch point Q3,
the first term of the right side of formula (20) can be
30 reduced.
[0118] The above similarly applies to the output wiring.
The wiring from the junction P1 to the junction Q2 provides
a larger second term of the right side of formula (20) than
58
the wiring from the junction P3Q2 to the junction P1.
However, since the width of the wiring pattern from the
junction P1 to the junction P2 is larger than the width of
the wiring pattern from the junction P3 to the junction P1,
5 the first term of the right side of formula (20) can be
reduced.
[0119] In the fifth embodiment, the self-inductance of
wiring and the time-differentiated amount of current are
taken into consideration, thereby making it possible to
10 reduce the difference in the amount of voltage drop due to
the inductance of the wiring.
[0120] In the fifth embodiment, since the voltage drop
amounts of gate wiring of the semiconductor module 10-1 and
gate wiring of the semiconductor module 10-2 can be equal
15 to each other, it is possible to reduce an imbalance in
current generated between the semiconductor modules when
the semiconductor modules are driven in parallel.
[0121] In the fifth embodiment, the wiring inductances
are considered to be equal to each other if an imbalance in
20 current between the semiconductor modules exists to such an
extent as to have substantially no influence.
[0122] Note that, in the present invention, the
respective embodiments can be freely combined, or the
embodiments can be appropriately modified or omitted within
25 the scope of the invention.
Reference Signs List
[0123] 1, 2, 3, 4, 5 semiconductor module parallel
circuit; 10-1 semiconductor module; 10-2 semiconductor
30 module; 10-3 semiconductor module; 10P first main terminal;
10N second main terminal; 10AC third main terminal; 11, 11-
1, 11-2, 12, 12-1, 12-2 first signal terminal; 13, 13-1,
13-2, 14, 14-1, 14-2 second signal terminal; 20 package; 30,
59
30-1, 30-2 first semiconductor element; 40, 40-1, 40-2
second semiconductor element; 50 fastening member; 61, 62
external connection terminal; 71-1, 71-2 first connection
terminal; 72-1, 72-2 second connection terminal; 100, 200,
5 300, 400, 500 multilayer substrate; 111-1, 111-2, 111-3,
112-1, 112-2, 112-3 first signal terminal connection
pattern; 113-1, 113-2, 113-3, 114-1, 114-2, 114-3 second
signal terminal connection pattern; 201, 301, 401, 501
first layer; 202, 302, 402, 502 second layer; 203, 303, 403,
10 503 third layer; D1, D2 drain terminal; S1, S2 source
terminal.
60
We Claim :
1. A semiconductor module parallel circuit comprising:
a first power semiconductor module;
a second power semiconductor module; and
5 a multilayer substrate to interconnect a plurality of
the power semiconductor modules, wherein
each of the power semiconductor modules includes:
a power semiconductor switching element;
a first signal terminal connected to a gate potential
10 of the power semiconductor switching element; and
a second signal terminal connected to a source
potential of the power semiconductor switching element,
the multilayer substrate includes:
an external connection terminal;
15 a first signal terminal connection pattern for the
first power semiconductor module, the first signal terminal
connection pattern for the first power semiconductor module
being connected to the first signal terminal of the first
power semiconductor module;
20 a second signal terminal connection pattern for the
first power semiconductor module, the second signal
terminal connection pattern for the first power
semiconductor module being connected to the second signal
terminal of the first power semiconductor module;
25 a first signal terminal connection pattern for the
second power semiconductor module, the first signal
terminal connection pattern for the second power
semiconductor module being connected to the first signal
terminal of the second power semiconductor module; and
30 a second signal terminal connection pattern for the
second power semiconductor module, the second signal
terminal connection pattern for the second power
semiconductor module being connected to the second signal
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terminal of the second power semiconductor module, and
an inductance of gate wiring for the first power
semiconductor module from the external connection terminal
to the first signal terminal connection pattern for the
5 first power semiconductor module and from the second signal
terminal connection pattern for the first power
semiconductor module to the external connection terminal,
and an inductance of gate wiring for the second power
semiconductor module from the external connection terminal
10 to the first signal terminal connection pattern for the
second power semiconductor module and from the second
signal terminal connection pattern for the second power
semiconductor module to the external connection terminal
are equal to each other.
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2. A semiconductor module parallel circuit comprising:
a first power semiconductor module;
a second power semiconductor module; and
a multilayer substrate to interconnect a plurality of
20 the power semiconductor modules, wherein
each of the power semiconductor modules includes:
a power semiconductor switching element;
a first signal terminal connected to a gate potential
of the power semiconductor switching element; and
25 a second signal terminal connected to a source
potential of the power semiconductor switching element,
the multilayer substrate includes:
an external connection terminal;
a first signal terminal connection pattern for the
30 first power semiconductor module, the first signal terminal
connection pattern for the first power semiconductor module
being connected to the first signal terminal of the first
power semiconductor module;
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a second signal terminal connection pattern for the
first power semiconductor module, the second signal
terminal connection pattern for the first power
semiconductor module being connected to the second signal
5 terminal of the first power semiconductor module;
a first signal terminal connection pattern for the
second power semiconductor module, the first signal
terminal connection pattern for the second power
semiconductor module being connected to the first signal
10 terminal of the second power semiconductor module; and
a second signal terminal connection pattern for the
second power semiconductor module, the second signal
terminal connection pattern for the second power
semiconductor module being connected to the second signal
15 terminal of the second power semiconductor module, and
a length of gate wiring for the first power
semiconductor module from the external connection terminal
to the first signal terminal connection pattern for the
first power semiconductor module and from the second signal
20 terminal connection pattern for the first power
semiconductor module to the external connection terminal,
and a length of gate wiring for the second power
semiconductor module from the external connection terminal
to the first signal terminal connection pattern for the
25 second power semiconductor module and from the second
signal terminal connection pattern for the second power
semiconductor module to the external connection terminal
are equal to each other.
30 3. The semiconductor module parallel circuit according to
claim 1 or 2, wherein
wiring from the external connection terminal to the
first signal terminal connection pattern for the first
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power semiconductor module and wiring from the external
connection terminal to the first signal terminal connection
pattern for the second power semiconductor module are
formed in a first layer of the multilayer substrate, and
5 wiring from the second signal terminal connection pattern
for the first power semiconductor module to the external
connection terminal and wiring from the second signal
terminal connection pattern for the second power
semiconductor module to the external connection terminal
10 are formed in a second layer of the multilayer substrate.
4. The semiconductor module parallel circuit according to
claim 3, wherein
the wiring from the external connection terminal to
15 the first signal terminal connection pattern for the first
power semiconductor module and the wiring from the external
connection terminal to the first signal terminal connection
pattern for the second power semiconductor module are
formed in a third layer of the multilayer substrate.
20
5. A semiconductor module parallel circuit comprising:
a first power semiconductor module;
a second power semiconductor module;
a third power semiconductor module; and
25 a multilayer substrate to interconnect a plurality of
the power semiconductor modules, wherein
each of the power semiconductor modules includes:
a power semiconductor switching element;
a first signal terminal connected to a gate potential
30 of the power semiconductor switching element; and
a second signal terminal connected to a source
potential of the power semiconductor switching element,
the multilayer substrate includes:
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an external connection terminal;
a first signal terminal connection pattern for the
first power semiconductor module, the first signal terminal
connection pattern for the first power semiconductor module
5 being connected to the first signal terminal of the first
power semiconductor module;
a second signal terminal connection pattern for the
first power semiconductor module, the second signal
terminal connection pattern for the first power
10 semiconductor module being connected to the second signal
terminal of the first power semiconductor module;
a first signal terminal connection pattern for the
second power semiconductor module, the first signal
terminal connection pattern for the second power
15 semiconductor module being connected to the first signal
terminal of the second power semiconductor module;
a second signal terminal connection pattern for the
second power semiconductor module, the second signal
terminal connection pattern for the second power
20 semiconductor module being connected to the second signal
terminal of the second power semiconductor module;
a first signal terminal connection pattern for the
third power semiconductor module, the first signal terminal
connection pattern for the third power semiconductor module
25 being connected to the first signal terminal of the third
power semiconductor module; and
a second signal terminal connection pattern for the
third power semiconductor module, the second signal
terminal connection pattern for the third power
30 semiconductor module being connected to the second signal
terminal of the third power semiconductor module, and
an inductance of gate wiring for the first power
semiconductor module from the external connection terminal
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to the first signal terminal connection pattern for the
first power semiconductor module and from the second signal
terminal connection pattern for the first power
semiconductor module to the external connection terminal,
5 an inductance of gate wiring for the second power
semiconductor module from the external connection terminal
to the first signal terminal connection pattern for the
second power semiconductor module and from the second
signal terminal connection pattern for the second power
10 semiconductor module to the external connection terminal,
and an inductance for gate wiring for the third power
semiconductor module from the external connection terminal
to the first signal terminal connection pattern for the
third power semiconductor module and from the second signal
15 terminal connection pattern for the third power
semiconductor module to the external connection terminal
are equal to one another.
6. A semiconductor module parallel circuit comprising:
20 a first power semiconductor module;
a second power semiconductor module;
a third power semiconductor module; and
a multilayer substrate to interconnect a plurality of
the power semiconductor modules, wherein
25 each of the power semiconductor modules includes:
a power semiconductor switching element;
a first signal terminal connected to a gate potential
of the power semiconductor switching element; and
a second signal terminal connected to a source
30 potential of the power semiconductor switching element,
the multilayer substrate includes:
an external connection terminal;
a first signal terminal connection pattern for the
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first power semiconductor module, the first signal terminal
connection pattern for the first power semiconductor module
being connected to the first signal terminal of the first
power semiconductor module;
5 a second signal terminal connection pattern for the
first power semiconductor module, the second signal
terminal connection pattern for the first power
semiconductor module being connected to the second signal
terminal of the first power semiconductor module;
10 a first signal terminal connection pattern for the
second power semiconductor module, the first signal
terminal connection pattern for the second power
semiconductor module being connected to the first signal
terminal of the second power semiconductor module;
15 a second signal terminal connection pattern for the
second power semiconductor module, the second signal
terminal connection pattern for the second power
semiconductor module being connected to the second signal
terminal of the second power semiconductor module;
20 a first signal terminal connection pattern for the
third power semiconductor module, the first signal terminal
connection pattern for the third power semiconductor module
being connected to the first signal terminal of the third
power semiconductor module; and
25 a second signal terminal connection pattern for the
third power semiconductor module, the second signal
terminal connection pattern for the third power
semiconductor module being connected to the second signal
terminal of the third power semiconductor module, and
30 a length of gate wiring for the first power
semiconductor module from the external connection terminal
to the first signal terminal connection pattern for the
first power semiconductor module and from the second signal
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terminal connection pattern for the first power
semiconductor module to the external connection terminal, a
length of gate wiring for the second power semiconductor
module from the external connection terminal to the first
5 signal terminal connection pattern for the second power
semiconductor module and from the second signal terminal
connection pattern for the second power semiconductor
module to the external connection terminal and a length of
gate wiring for the third power semiconductor module from
10 the external connection terminal to the first signal
terminal connection pattern for the third power
semiconductor module and from the second signal terminal
connection pattern for the third power semiconductor module
to the external connection terminal are equal to one
15 another.
7. A semiconductor module connection substrate
comprising:
an external connection terminal;
20 a first signal terminal connection pattern for a first
power semiconductor module, the first signal terminal
connection pattern for the first power semiconductor module
being provided for connection to a first signal terminal of
the first power semiconductor module;
25 a second signal terminal connection pattern for the
first power semiconductor module, the second signal
terminal connection pattern for the first power
semiconductor module being provided for connection to a
second signal terminal of the first power semiconductor
30 module;
a first signal terminal connection pattern for a
second power semiconductor module, the first signal
terminal connection pattern for the second power
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semiconductor module being provided for connection to a
first signal terminal of the second power semiconductor
module; and
a second signal terminal connection pattern for the
5 second power semiconductor module, the second signal
terminal connection pattern for the second power
semiconductor module being provided for connection to a
second signal terminal of the second power semiconductor
module, wherein
10 an inductance of gate wiring for the first power
semiconductor module from the external connection terminal
to the first signal terminal connection pattern for the
first power semiconductor module and from the second signal
terminal connection pattern for the first power
15 semiconductor module to the external connection terminal,
and an inductance of gate wiring for the second power
semiconductor module from the external connection terminal
to the first signal terminal connection pattern for the
second power semiconductor module and from the second
20 signal terminal connection pattern for the second power
semiconductor module to the external connection terminal
are equal to each other.
8. A semiconductor module connection substrate
25 comprising:
an external connection terminal;
a first signal terminal connection pattern for a first
power semiconductor module, the first signal terminal
connection pattern for the first power semiconductor module
30 being provided for connection to a first signal terminal of
the first power semiconductor module;
a second signal terminal connection pattern for the
first power semiconductor module, the second signal
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terminal connection pattern for the first power
semiconductor module being provided for connection to a
second signal terminal of the first power semiconductor
module;
5 a first signal terminal connection pattern for a
second power semiconductor module, the first signal
terminal connection pattern for the second power
semiconductor module being provided for connection to a
first signal terminal of the second power semiconductor
10 module; and
a second signal terminal connection pattern for the
second power semiconductor module, the second signal
terminal connection pattern for the second power
semiconductor module being provided for connection to a
15 second signal terminal of the second power semiconductor
module, wherein

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a length of gate wiring for the first power semiconductor
module from the external connection terminal to the first
signal terminal connection pattern for the first power
semiconductor module and from the second signal terminal
5 connection pattern for the first power semiconductor module
to the external connection terminal, and a length of gate
wiring for the second power semiconductor module from the
external connection terminal to the first signal terminal
connection pattern for the second power semiconductor
10 module and from the second signal terminal connection
pattern for the second power semiconductor module to the
external connection terminal are equal to each other.