Claims:1. A semiconductor device, comprising:
a semiconductor chip mounted to a package body;
an array of locations on the package body having a regular array spacing between locations in the array, the array spacing being substantially the same in an X and Y direction within a plane of the array,
a plurality of contacts located at selected locations in the array, the plurality of contacts electrically connected to the semiconductor chip, the plurality of contacts including:
a first layer of contacts located at locations in the array, wherein the first layer includes a series of regularly spaced gaps in the first layer of contacts, the regularly spaced gaps located at locations in the array;
a second layer of contacts located at locations in the array, the second layer located inside the first layer;
a third layer of contacts located at locations in the array, the third layer located inside the second layer; and
a fourth layer of contacts located at locations in the array, the fourth layer located inside the third layer.
, Description:TECHNICAL FIELD
The present invention relates to a semiconductor package structure, and in particular to a grid array package structure.

BACKGROUND
In the field of semiconductor package technology, common types of semiconductor chip package comprise the ball grid array (BGA) package, the chip scale package (CSP), the flip chip (FC) package and the like. For example, a ball grid array package structure 200 as shown in Figures 1 and 2 mainly comprises a body 210 and solder balls 220 arranged in array on a bottom surface 211 of the body 210, wherein the solder balls 220 can substitute for a conventional metal lead frame to serve as electrical contacts, such that the ball grid array package structure may have the merit of large area and large quantity of transmitted signals. It needs to be specifically noted that the body 210 has semiconductor chip disposed therein, wherein the semiconductor chip may be electrically connected to a underlying printed circuit board 100 through the solder balls 220 located on the bottom surface 211 of the body 210.
However, with the increasing complexity of semiconductor circuits and the increasing number of signal pins, there is generally difficulty during circuit layout for package substrate.

SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, an embodiment of the present invention Provides a semiconductor package structure comprising a body, a plurality of first-layer electrical contacts, a plurality of second-layer electrical contacts, a plurality of third-layer electrical contacts and a plurality of fourth-layer electrical contacts. The body encloses a semiconductor chip and has a bottom surface, and the first-layer, the second-layer , the third-layer and the fourth-layer electrical contacts are electrically connected to the semiconductor chip and are arranged sequentially from outside to inside on the bottom surface in a matrix manner. Wherein, adjacent first-layer electrical contacts have two different spacings therebetween, and adjacent third-layer electrical contacts also have the two different spacings therebetween, wherein said two different spacings comprise a first spacing and a second spacing greater than the first spacing.
In an embodiment of the present invention, the second spacing is twice the first spacing.
In an embodiment of the present invention, the first spacing is a minimum spacing between adjacent first-layer electrical contacts.
In an embodiment of the present invention, the first spacing is a minimum spacing between adjacent third-layer electrical contacts.
In an embodiment of the present invention, the first-layer electrical contacts comprise a first pair of electrical contacts with the first spacing, a second pair of electrical contacts with the first spacing and a third pair of electrical contacts with the first spacing, the first pair of electrical contacts and the second pair of electrical contacts having the second spacing therebetween, the second pair of electrical contacts and the third pair of electrical contacts having the second spacing therebetween, and the second pair of electrical contacts being located between the first pair of electrical contacts and the third pair of electrical contacts.
In an embodiment of the present invention, the third-layer electrical contacts comprise a fourth pair of electrical contacts with the first spacing, a fifth pair of electrical contacts with the first spacing and a sixth pair of electrical contacts with the first spacing, the fourth pair of electrical contacts and the fifth pair of electrical contacts having the second spacing therebetween, the fifth pair of electrical contacts and the sixth pair of electrical contacts having the second spacing therebetween, and the fifth pair of electrical contacts being located between the fourth pair of electrical contacts and the sixth pair of electrical contacts.
In an embodiment of the present invention, the body further has a package substrate with a first circuit layer and a second circuit layer.
In an embodiment of the present invention, the first circuit layer comprises a plurality of conductors and a plurality of conductive portions, the conductive portions being connected to the conductors and at least a portion of the first-layer electrical contacts and second-layer electrical contacts respectively.
In an embodiment of the present invention, the second circuit layer comprises a plurality of conductors and a plurality of conductive portions, the conductive portions being connected to the conductors and at least a portion of the third-layer electrical contacts and fourth-layer electrical contacts respectively.
In a semiconductor package structure embodiment of the present invention, the semiconductor package structure is a ball grid array package structure.
To make the above-mentioned objects, features and advantages of the present invention more comprehensible, a detailed description is given below with preferred embodiments in conjunction with the accompanied drawings.

BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a schematic view of a combination of an existing semiconductor package structure and a circuit board;
Figure 2 is a bottom view of the existing semiconductor package structure of Figure 1;
Figure 3A is a schematic view of a semiconductor package structure of an embodiment of the present invention;
Figure 3B is a bottom view of the semiconductor package structure of Figure 3A;
Figure 3C is a schematic view of adjacent first-layer electrical contacts C1 having two different spacings D and 2D therebetween and adjacent third-layer electrical contacts C3 having the two different spacings D and 2D therebetween;
Figure 4A is a schematic view of a first circuit layer in a package substrate of a body; and
Figure 4B is a schematic view of a second circuit layer in the package substrate of a body.