FORM 2
THE PATENTS ACT, 1970
(39 of& 1970) THE PATENTS RULES, 2003 COMPLETE SPECIFICATION
[See section 10, Rule 13]
SERIES MULTIPLEX INVERTER;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANISED
AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3,
MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 1008310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.
2
DESCRIPTION
Field
[0001] The present invention relates to a series
5 multiplex inverter including a plurality of single-phase
inverters having output terminals connected in series.
Background
[0002] Conventionally known series multiplex inverters
10 includes a plurality of single-phase inverters to output
rectangular wave voltages out of phase with each other,
combine the rectangular wave voltages, and output the
combined voltage. Regarding this type of series multiplex
inverter, Patent Literature 1 discloses a technique of
15 calculating the phase angle of a rectangular wave voltage
output from each single-phase inverter such that the
harmonic of each order included in the output voltage from
the series multiplex inverter has a desired value or less.
The single-phase inverters then individually output a
20 rectangular wave voltage at the calculated phase angle.
Citation List
Patent Literature
[0003] Patent Literature 1: Japanese Patent Application
25 Laid-open No. H6-245532
Summary
Technical Problem
[0004] The conventional series multiplex inverter can
30 perform control such that the harmonic voltage of each
order included in the output voltage from the series
multiplex inverter has a desired value or less, but takes
no account of the harmonic current flowing through the load
3
connected to the series multiplex inverter. Because the
easiness of flow of the harmonic current of each order
varies depending on the characteristics of the load
connected to the series multiplex inverter, even when the
5 harmonic voltage of each order included in the output
voltage from the series multiplex inverter is suppressed,
the magnitude of the harmonic current of each order varies
depending on the characteristics of the load. Therefore,
an attempt to suppress the harmonic current of each order
10 from the series multiplex inverter to the load regardless
of the characteristics of the load requires a large
harmonic filter having a high harmonic reduction effect,
resulting in an increase in the size of the series
multiplex inverter.
15 [0005] The present invention has been made in view of
the above, and an object thereof is to obtain a series
multiplex inverter capable of suppressing the harmonic
current flowing through the load by controlling each
single-phase inverter even when the characteristics of the
20 load vary.
Solution to Problem
[0006] In order to solve the above-described problems
and achieve the object, a series multiplex inverter of the
25 present invention comprises a power conversion unit, a
phase difference selection unit, a drive signal generation
unit, and a drive signal output unit. The power conversion
unit includes a plurality of single-phase inverters having
output terminals connected in series. The phase difference
30 selection unit selects, from among a plurality of phase
difference candidates, a phase difference between
rectangular wave voltages from the plurality of singlephase
inverters. The drive signal generation unit
4
generates a plurality of drive signals that causes
different single-phase inverters to output a plurality of
rectangular wave voltages sequentially out of phase by the
phase difference selected by the phase difference selection
5 unit. The drive signal output unit outputs the plurality
of drive signals generated by the drive signal generation
unit to the plurality of single-phase inverters.
Advantageous Effects of Invention
10 [0007] The present invention can achieve the effect of
suppressing the harmonic current flowing through the load
by controlling each single-phase inverter even when the
characteristics of the load vary.
15 Brief Description of Drawings
[0008] FIG. 1 is a diagram illustrating an exemplary
configuration of a series multiplex inverter according to a
first embodiment of the present invention.
FIG. 2 is a diagram illustrating an exemplary
20 configuration of a single-phase inverter according to the
first embodiment.
FIG. 3 is a diagram illustrating the relationship
between gate signals output from a gate driver and the
waveform of the output voltage from a single-phase inverter
25 according to the first embodiment.
FIG. 4 is a diagram illustrating an exemplary
configuration of a drive signal generation unit according
to the first embodiment.
FIG. 5 is a diagram illustrating an example of output
30 voltages from a plurality of single-phase inverters
according to the first embodiment.
FIG. 6 is a diagram illustrating an example of output
voltages from a plurality of single-phase inverters
5
according to the first embodiment.
FIG. 7 is a diagram illustrating an example of output
voltages from a plurality of single-phase inverters
according to the first embodiment.
5 FIG. 8 is a diagram illustrating an example of the
harmonic voltage of each order according to the first
embodiment.
FIG. 9 is a partially enlarged diagram of FIG. 8.
FIG. 10 is a diagram illustrating frequency
10 characteristics of a plurality of loads according to the
first embodiment.
FIG. 11 is a diagram illustrating the relationship
between the first phase difference and the harmonic current
for the first load according to the first embodiment.
15 FIG. 12 is a diagram illustrating the relationship
between the first phase difference and the harmonic current
for the second load according to the first embodiment.
FIG. 13 is a diagram illustrating the relationship
between the first phase difference and the harmonic current
20 for the third load according to the first embodiment.
FIG. 14 is a flowchart illustrating an exemplary
process that is performed by a control unit according to
the first embodiment.
FIG. 15 is a diagram illustrating an exemplary
25 hardware configuration of the control unit of the series
multiplex inverter according to the first embodiment.
FIG. 16 is a diagram illustrating an exemplary
configuration of a series multiplex inverter according to a
second embodiment.
30 FIG. 17 is a flowchart illustrating an exemplary
process that is performed by a control unit according to
the second embodiment.
6
Description of Embodiments
[0009] Hereinafter, series multiplex inverters according
to embodiments of the present invention will be described
in detail based on the drawings. The present invention is
5 not limited to the embodiments.
[0010] First Embodiment
FIG. 1 is a diagram illustrating an exemplary
configuration of a series multiplex inverter according to
the first embodiment of the present invention. As
10 illustrated in FIG. 1, the series multiplex inverter 1
according to the first embodiment includes a power
conversion unit 10, a voltage detection unit 20, a current
detection unit 30, a control unit 40, an operation unit 50,
and a harmonic filter 70. The control unit 40 controls the
15 power conversion unit 10 such that the output voltage Vo is
output from the power conversion unit 10.
[0011] The power conversion unit 10 can convert AC power
output from a single-phase AC power supply 2 into AC power
having some frequency and amplitude. For example, the
20 power conversion unit 10 can convert AC power output from
the single-phase AC power supply 2 into high-frequency AC
power having a fundamental frequency of 1 kHz or more.
Note that the power conversion unit 10 can also convert AC
power output from the single-phase AC power supply 2 into
25 AC power having a fundamental frequency of less than 1 kHz.
[0012] The power conversion unit 10 includes n power
conversion blocks 111 to 11n. Here, “n” is an integer of
two or more. The power conversion block 111 includes a
transformer 121, a rectifier circuit 131, a capacitor 141,
30 and a single-phase inverter 151. The power conversion
block 112 includes a transformer 122, a rectifier circuit
132, a capacitor 142, and a single-phase inverter 152.
[0013] Similarly to the power conversion blocks 111 and
7
112, each of the power conversion blocks 113 to 11n includes
one of transformers 123 to 12n, one of rectifier circuits
133 to 13n, one of capacitors 143 to 14n, and one of singlephase
inverters 153 to 15n. The power conversion blocks 111
5 to 11n have the same configuration, as stated above.
Hereinafter, therefore, the configuration of the power
conversion block 111 will be described in detail.
[0014] The primary winding of the transformer 121 is
connected to the single-phase AC power supply 2. The
10 transformer 121 converts the AC voltage Vac output from the
single-phase AC power supply 2 into an AC voltage having an
amplitude that depends on the winding ratio of the
transformer 121, and outputs the AC voltage.
[0015] The rectifier circuit 131 is connected to the
15 secondary winding of the transformer 121, and rectifies the
AC voltage output from the transformer 121. The rectifier
circuit 131 is, for example, a full-wave rectifier circuit,
a half-wave rectifier circuit, or a full-bridge circuit.
Note that the rectifier circuit 131 only needs to be able
20 to rectify the AC voltage output from the transformer 121,
and is not necessarily a full-wave rectifier circuit, a
half-wave rectifier circuit, or a full-bridge circuit.
[0016] The capacitor 141 smooths the output voltage from
the rectifier circuit 131. The rectifier circuit 131 and
25 the capacitor 141 convert the AC voltage output from the
transformer 121 into the DC voltage Vdc.
[0017] The single-phase inverter 151 is controlled by
the control unit 40, such that the single-phase inverter
151 can convert the DC voltage Vdc generated by the
30 rectifier circuit 131 and the capacitor 141 into a
rectangular wave voltage and output the rectangular wave
voltage.
[0018] The power conversion blocks 112 to 11n generate
8
and output rectangular wave voltages, similarly to the
power conversion block 111. Hereinafter, the AC voltages
output from the single-phase inverters 151 to 15n will be
respectively referred to as the output voltages VINV1 to
5 VINVn for easy understanding. Note that the output voltages
VINV1 to VINVn may be collectively referred to as the output
voltage VINV.
[0019] Output terminals 161, 171, 162, 172,..., 16n-1, 17n-
1, 16n, and 17n of the single-phase inverters 151 to 15n are
10 connected in series. Consequently, the output voltages
VINV1 to VINVn from the single-phase inverters 151 to 15n are
combined, and a result of the combination is output as the
output voltage Vo from the power conversion unit 10.
[0020] The output voltage Vo from the power conversion
15 unit 10 is supplied to a load 3 via the harmonic filter 70.
The harmonic filter 70 is, for example, an LC filter, but
may be an LCL filter.
[0021] Hereinafter, the transformers 121 to 12n may be
collectively referred to as the transformer 12, and the
20 rectifier circuits 131 to 13n may be collectively referred
to as the rectifier circuit 13. The capacitors 141 to 14n
may be collectively referred to as the capacitor 14, and
the single-phase inverters 151 to 15n may be collectively
referred to as the single-phase inverter 15.
25 [0022] In the exemplary configuration illustrated in FIG.
1, each of the power conversion blocks 111 to 11n includes
the transformer 12, the rectifier circuit 13, and the
capacitor 14. Alternatively, a DC power supply that
outputs the DC voltage Vdc may be provided instead of the
30 transformer 12, the rectifier circuit 13, and the capacitor
14.
[0023] FIG. 2 is a diagram illustrating an exemplary
configuration of a single-phase inverter according to the
9
first embodiment. As illustrated in FIG. 2, the singlephase
inverter 151 includes four switching elements Q1 to
Q4 connected in full bridge configuration, diodes D1 to D4
connected in anti-parallel to the switching elements Q1 to
5 Q4, respectively, and a gate driver 18.
[0024] The gate driver 18 generates gate signals Sg1 to
Sg4 on the basis of a drive signal (described later) output
from the control unit 40, and outputs each of the generated
gate signals Sg1 to Sg4 to the corresponding one of the
10 gates of the switching elements Q1 to Q4. Consequently,
the switching elements Q1 to Q4 are subjected to on/off
control, such that the output voltage VINV1 is generated and
output by the single-phase inverter 151. The switching
elements Q1 to Q4 are semiconductor switching elements
15 represented by metal-oxide-semiconductor field-effect
transistors (MOSFETs) and insulated gate bipolar
transistors (IGBTs).
[0025] FIG. 3 is a diagram illustrating the relationship
between gate signals output from a gate driver and the
20 waveform of the output voltage from a single-phase inverter
according to the first embodiment. As illustrated in FIG.
3, the output voltage VINV1 including a rectangular wave
voltage is generated by the gate signals Sg1 to Sg4. In
FIG. 3, “To” is an output voltage period indicating the
25 fundamental period of the output voltage Vo from the series
multiplex inverter 1. In addition, “+Va” is the voltage
value of a positive rectangular wave voltage output from
the single-phase inverter 151, and “−Va” is the voltage
value of a negative rectangular wave voltage output from
30 the single-phase inverter 151.
[0026] A drive signal output from the control unit 40 to
the single-phase inverter 15 includes four pulse width
modulation (PWM) signals having the same waveform as the
10
respective gate signals Sg1 to Sg4, and is amplified by the
gate driver 18 and output to the switching elements Q1 to
Q4. Note that this is a non-limiting example of a drive
signal, and any drive signal can be used as long as the
5 gate driver 18 can generate the gate signals Sg1 to Sg4 on
the basis of the drive signal from the control unit 40.
For example, a drive signal output from the control unit 40
to each single-phase inverter 15 may include one or two PWM
signals. That is, the gate driver 18 may be configured to
10 generate and output the gate signals Sg1 to Sg4 from a
drive signal including one or two PWM signals.
[0027] The single-phase inverters 152 to 15n have the
same configuration as the single-phase inverter 151. Note
that the single-phase inverters 151 to 15n are not limited
15 to the configuration illustrated in FIG. 2. That is, the
single-phase inverters 151 to 15n only need to be able to
output the output voltages VINV1 to VINVn (described later),
and do not necessarily have the configuration illustrated
in FIG. 2.
20 [0028] Reference is made back to FIG. 1 to continue the
explanation of the series multiplex inverter 1. The
voltage detection unit 20 of the series multiplex inverter
1 repeatedly detects the instantaneous value of the output
voltage Vo from the power conversion unit 10, and outputs
25 the detected voltage value Vdet that is the detected
instantaneous value of the output voltage Vo. The current
detection unit 30 of the series multiplex inverter 1
repeatedly detects the instantaneous value of the output
current Io from the power conversion unit 10, and outputs
30 the detected current value Idet that is the detected
instantaneous value of the output current Io.
[0029] The control unit 40 of the series multiplex
inverter 1 includes a drive signal generation unit 41, a
11
drive signal output unit 42, and a phase difference
selection unit 43. The drive signal output unit 42
generates n drive signals Sp1 to Spn. The drive signal
output unit 42 outputs the n drive signals Sp1 to Spn to
5 the n single-phase inverters 151 to 15n. Hereinafter, the
drive signals Sp1 to Spn may be collectively referred to as
the drive signal Sp.
[0030] The drive signal generation unit 41 generates the
n drive signals Sp by constant output current control on
10 the basis of the detected current value Idet. Each drive
signal Sp includes, for example, a plurality of PWM signals
as described above. Note that the drive signal generation
unit 41 can also generate the n drive signals Sp by
constant output voltage control or constant output power
15 control. For example, the drive signal generation unit 41
can generate the n drive signals Sp by constant output
voltage control on the basis of the detected voltage value
Vdet.
[0031] The drive signal generation unit 41 can generate
20 the n drive signals Sp by constant output power control on
the basis of the detected voltage value Vdet and the
detected current value Idet. In a case where the drive
signal generation unit 41 performs only constant output
current control, the voltage detection unit 20 may not be
25 provided.
[0032] The drive signals Sp1 to Spn are signals that
cause different ones of the n single-phase inverters 15 to
output n rectangular wave voltages sequentially out of
phase by the first phase difference φ1 (described later).
30 Hereinafter, an exemplary configuration of the drive signal
generation unit 41 will be described.
[0033] FIG. 4 is a diagram illustrating an exemplary
configuration of the drive signal generation unit according
12
to the first embodiment. As illustrated in FIG. 4, the
drive signal generation unit 41 includes an effective value
calculation unit 60, a current command output unit 61, a
subtractor 62, a current control unit 63, a carrier wave
5 output unit 64, a comparator 65, and a signal generation
unit 66.
[0034] The effective value calculation unit 60
calculates the output current effective value IoM, which is
the effective value of the output current Io, on the basis
10 of the detected current value Idet output from the current
detection unit 30. The effective value calculation unit 60
calculates the output current effective value IoM, for
example, every half output voltage period To. The output
voltage period To is the fundamental period of the output
15 voltage Vo as described above, and To=1/fo is satisfied.
Note that “fo” is the frequency of the output voltage Vo,
and is hereinafter referred to as the output voltage
frequency fo.
[0035] The current command output unit 61 outputs the
20 current command Iref. The value of the current command
Iref is generated by the current command output unit 61 on
the basis of, for example, information supplied from the
outside to the current command output unit 61.
[0036] The subtractor 62 subtracts the output current
25 effective value IoM from the current command Iref, and
outputs the current difference value ΔI as the result of
the subtraction. The current control unit 63 generates the
voltage command Vref on the basis of the current difference
value ΔI output from the subtractor 62. The current
30 control unit 63 can generate the voltage command Vref by,
for example, proportional integral control or proportional
integral derivative control.
[0037] The carrier wave output unit 64 generates the
13
carrier wave Vcs and outputs the generated carrier wave Vcs.
The carrier wave Vcs is, for example, a voltage having a
triangular waveform or a voltage having a sawtooth waveform.
The output voltage period To is the same as the period of
5 the carrier wave Vcs. When the period of the carrier wave
Vcs changes, the output voltage period To changes.
[0038] The comparator 65 compares the voltage command
Vref with the carrier wave Vcs, and outputs the result of
the comparison. Specifically, the comparator 65 outputs
10 the first voltage V1 when the voltage command Vref is
larger than the carrier wave Vcs, and outputs the second
voltage V2 different from the first voltage V1 when the
voltage command Vref is smaller than the carrier wave Vcs.
[0039] The signal generation unit 66 generates the n
15 drive signals Sp1 to Spn on the basis of the voltage output
from the comparator 65. The signal generation unit 66 has
information indicating the first phase difference φ1 input
from the phase difference selection unit 43. The signal
generation unit 66 also determines the second phase
20 difference φ2 on the basis of the duty ratio of the voltage
output from the comparator 65. For example, the signal
generation unit 66 determines the second phase difference
φ2 such that the shorter the time during which the second
voltage V2 is output from the comparator 65 is, the smaller
25 the second phase difference φ2 is, in half period of the
carrier wave Vcs.
[0040] The signal generation unit 66 generates the n
drive signals Sp1 to Spn on the basis of the first phase
difference φ1 and the second phase difference φ2. The
30 signal generation unit 66 outputs the generated n drive
signals Sp1 to Spn to the drive signal output unit 42
illustrated in FIG. 1.
[0041] The single-phase inverters 151 to 15n output the
14
output voltages VINV1 to VINVn from the output terminals 161,
171, 162, 172,..., 16n-1, 17n-1, 16n, and 17n on the basis of
the drive signals Sp1 to Spn output from the drive signal
output unit 42. The output voltages VINV1 to VINVn from the
5 single-phase inverters 151 to 15n are combined, and the
result of the combination is output as the output voltage
Vo from the power conversion unit 10.
[0042] Here, the output voltages VINV1 to VINVn from the
single-phase inverters 151 to 15n will be described in
10 detail with reference to FIGS. 5 to 7. FIGS. 5 to 7 are
diagrams illustrating examples of output voltages from a
plurality of single-phase inverters according to the first
embodiment. In the examples of FIGS. 5 to 7, n=8 is
satisfied, that is, the number of single-phase inverters 15
15 is eight, and the drive signals Sp1 to Sp8 are sequentially
input in a one-to-one correspondence to the single-phase
inverters 151 to 158 in order of Sp1 to Sp8.
[0043] Specifically, the drive signal Sp1 is input to
the single-phase inverter 151, the drive signal Sp2 is
20 input to the single-phase inverter 152, the drive signal
Sp3 is input to the single-phase inverter 153, and the
drive signal Sp4 is input to the single-phase inverter 154.
Similarly, the drive signal Sp5 is input to the singlephase
inverter 155, the drive signal Sp6 is input to the
25 single-phase inverter 156, the drive signal Sp7 is input to
the single-phase inverter 157, and the drive signal Sp8 is
input to the single-phase inverter 158.
[0044] In FIGS. 5 to 7, “1” means the above-mentioned
“+Va” which is the voltage value of a positive rectangular
30 wave voltage output from the single-phase inverter 15, and
“−1” means the above-mentioned “−Va” which is the voltage
value of a negative rectangular wave voltage output from
the single-phase inverter 15. Also, “2” to “7” mean
15
multiples of “+Va”, and “−2” to “−7” mean multiples of
“−Va”. In FIGS. 5 to 7, the vertical axis represents the
instantaneous value of the output voltage Vo, and the
horizontal axis represents the phase of the output voltage
5 Vo. The interval between vertical dashed lines is 18°.
Hereinafter, the phase of the output voltage Vo is referred
to as the output voltage phase θo.
[0045] As illustrated in FIG. 5, the output voltages
VINV1 to VINV8 are sequentially out of phase by the first
10 phase difference φ1. Specifically, the output voltages
VINV1 to VINVn8 become positive rectangular wave voltages at
timings sequentially out of phase by the first phase
difference φ1, and become negative rectangular wave
voltages at timings sequentially out of phase by the first
15 phase difference φ1. In the example illustrated in FIG. 5,
φ1=18° is satisfied.
[0046] For example, the positive rectangular wave
voltage at the output voltage VINV2 is out of phase with the
positive rectangular wave voltage at the output voltage
20 VINV1 by the first phase difference φ1. The positive
rectangular wave voltage at the output voltage VINV3 is out
of phase with the positive rectangular wave voltage at the
output voltage VINV2 by the first phase difference φ1.
Similarly, the negative rectangular wave voltage at the
25 output voltage VINV2 is out of phase with the negative
rectangular wave voltage at the output voltage VINV1 by the
first phase difference φ1. The negative rectangular wave
voltage at the output voltage VINV3 is out of phase with the
negative rectangular wave voltage at the output voltage
30 VINV2 by the first phase difference φ1.
[0047] The single-phase inverter 15 also outputs, on the
basis of the drive signal Sp, a negative rectangular wave
voltage shifted by the second phase difference φ2 from the
16
end of the output of the positive rectangular wave voltage.
In the example illustrated in FIG. 5, φ2=54° is satisfied.
For the output voltage VINV1 from the single-phase inverter
151, the time period of 0°≤θo≤126° is a time period during
5 which a positive rectangular wave voltage is output, and
the time period of 180°≤θo≤306° is a time period during
which a negative rectangular wave voltage is output.
Therefore, for the output voltage VINV1, the time period of
the negative rectangular wave voltage starts at the timing
10 shifted by 54°, which is the second phase difference φ2,
from the end of the time period of the positive rectangular
wave voltage.
[0048] Similarly, for the output voltages VINV2 to VINV8
from the single-phase inverters 152 to 158, the time period
15 of the negative rectangular wave voltage starts at the
timing shifted by the second phase difference φ2 from the
end of the time period of the positive rectangular wave
voltage. As is clear from the foregoing, the drive signal
Sp is generated such that the output voltage VINV from the
20 single-phase inverter 15 involves the second phase
difference φ2.
[0049] As described above, because the output terminals
161, 171, 162, 172,..., 16n-1, 17n-1, 16n, and 17n of the
single-phase inverters 151 to 158 are connected in series,
25 the output voltages VINV1 to VINV8 from the single-phase
inverters 151 to 158 are combined. Therefore, as
illustrated in FIG. 5, the waveform of the output voltage
Vo from the power conversion unit 10 is a composite
waveform of the output voltages VINV1 to VINV8.
30 [0050] For example, in the case of 0°≤θo<18°, the output
voltage VINV1 is +Va, the output voltages VINV2 to VINV4 are 0
V, and the output voltages VINV5 to VINV8 are −Va. Therefore,
the output voltage Vo is −3×Va. In the case of 18°≤θo<36°,
17
the output voltages VINV1 and VINV2 are +Va, the output
voltages VINV3 to VINV5 are 0 V, and the output voltages VINV6
to VINV8 are −Va. Therefore, the output voltage Vo is −Va.
In the case of 36°≤θo<54°, the output voltages VINV1 to VINV3
5 are +Va, the output voltages VINV4 to VINV6 are 0 V, and the
output voltages VINV7 and VINV8 are −Va. Therefore, the
output voltage Vo is +Va.
[0051] As described above, the rectangular wave voltages
of the single-phase inverters 151 to 15n are output at
10 different timings and combined. Therefore, the output
voltage Vo from the power conversion unit 10 has a pseudo
sinusoidal waveform that changes stepwise, and harmonic
voltage can be suppressed. In the example illustrated in
FIG. 5, the output voltage Vo changes stepwise in the range
15 of 7×Va to −7×Va. Changing the magnitude of the second
phase difference φ2 to increase or decrease the time during
which the single-phase inverter 15 outputs a rectangular
wave voltage controls waveform of the output voltage Vo.
[0052] The second phase difference φ2 illustrated in FIG.
20 6 is set larger than the second phase difference φ2
illustrated in FIG. 5. Specifically, the second phase
difference φ2 illustrated in FIG. 6 is larger than the
second phase difference φ2 illustrated in FIG. 5 by the
time equivalent to 36°. Therefore, in the example
25 illustrated in FIG. 6, the output voltage Vo changes
stepwise in the range of 6×Va to −6×Va, and has a smaller
amplitude than the output voltage Vo illustrated in FIG. 5.
[0053] Similarly, the second phase difference φ2
illustrated in FIG. 7 is set larger than the second phase
30 difference φ2 illustrated in FIG. 6. Specifically, the
second phase difference φ2 illustrated in FIG. 7 is larger
than the second phase difference φ2 illustrated in FIG. 6
by the time equivalent to 36°. Therefore, in the example
18
illustrated in FIG. 7, the output voltage Vo changes
stepwise in the range of 3×Va to −3×Va, and has a smaller
amplitude than the output voltage Vo illustrated in FIG. 6.
[0054] As is clear from the foregoing, the series
5 multiplex inverter 1 can suppress harmonic voltage by
providing the first phase difference φ1, and change the
amplitude of the output voltage Vo by changing the second
phase difference φ2.
[0055] Assume an example in which, as illustrated in FIG.
10 1, the load 3 which can be represented by a resonance
circuit including L, C, and R equivalently is connected to
the series multiplex inverter 1, and the control unit 40
performs constant output current control on the power
conversion unit 10. In the example illustrated in FIG. 1,
15 the load 3 is configured by a series resonance circuit in
which one L, one C, and one R are connected in series, but
the load 3 is not limited to the configuration illustrated
in FIG. 1.
[0056] The output voltage Vo from the series multiplex
20 inverter 1 can be expressed by Formula (1) below. In
Formula (1) below, “m” represents the order, m=1 is the
fundamental frequency, and m>1 is the harmonic frequency.
Hereinafter, the term “harmonic” refers to the ninth or
lower-order harmonic for convenience of description, but
25 the harmonic is not limited to the ninth or lower-order
harmonic. For example, harmonics may include the eleventh
and higher-order harmonics. Because the output voltage Vo
is a symmetrical wave voltage as illustrated in FIGS. 5 to
7, even-order harmonics can be ignored in the output
30 voltage Vo.
[0057] [Formula 1]
19
  


  
  



   



   



   



 



 

 
m 1,3,5,
2 2 1 1 1 1
m 1
2
cos 7m 2
cos 5m 2
cos 3m 2
cos m 2
sin m m
Vo 8Vdc 1
(1)
[0058] In a case where the power conversion unit 10 is
controlled by constant output current control, the output
5 voltage Vo changes depending on the impedance of the load 3.
Therefore, the second phase difference φ2 for adjusting the
output voltage Vo changes in the range of 0°≤φ2≤180°. When
the second phase difference φ2 has the maximum value, the
harmonic voltage of each order reaches the maximum value.
10 Therefore, to calculate the maximum value of the harmonic
voltage of each order on the assumption that Formula (2)
below is satisfied, the harmonic voltage of each order with
respect to the first phase difference φ1 can be expressed
by Formula (3) below.
15 [0059] [Formula 2]
1 2
m sin 2  



 
(2)
 
  
  



   



   



   



 

 2
cos 7m 2
cos 5m 2
cos 3m 2
cos m m
Vrms m 4 2Vdc 1 1 1 1
(3)
[0060] FIG. 8 is a diagram illustrating an example of
20 the harmonic voltage of each order according to the first
embodiment, which shows the calculation result of the
harmonic voltage of each order with respect to the first
phase difference φ1 for the case Vdc=100 V in Formula (3)
above. FIG. 9 is a partially enlarged diagram of FIG. 8.
25 In FIGS. 8 and 9, the horizontal axis represents the
magnitude of the first phase difference φ1, and the
vertical axis represents the magnitude of the harmonic
voltage of each order.
[0061] As illustrated in FIG. 8, the harmonic voltage of
20
each order periodically increases and decreases with
respect to the magnitude of the first phase difference φ1.
Therefore, using such characteristics to select and control
the first phase difference φ1 such that the harmonic
5 voltage of each order has a desired value or less can
suppress the harmonic voltage of each order. For example,
as illustrated in FIG. 9, when the harmonic voltage of each
order should be 50 [Vrms] or less, 12.4°≤φ1≤19.5° or
23.7°≤φ1≤37.4° is employed, so that the harmonic voltage of
10 each order can be set to 50 [Vrms] or less.
[0062] As is clear from the forgoing, determining the
first phase difference φ1 with reference to the calculation
result illustrated in FIG. 8 can set the harmonic voltage
of each order to a desired value or less. Therefore, in a
15 case where the load 3 is a pure resistor whose
characteristics do not change depending on the frequency of
the output voltage Vo, the harmonic current of each order
can be suppressed. Although the effect of suppressing the
harmonic current can be obtained even when the
20 characteristics of the load 3 change depending on the
frequency of the output voltage Vo, it is necessary to
consider the easiness of flow of the harmonic current of
each order through the load 3 in order to set the harmonic
current of each order to a desired value or less. In other
25 words, determination of the first phase difference φ1 with
reference to the calculation result illustrated in FIG. 8
can not suffice.
[0063] In view of this, the series multiplex inverter 1
is configured to switch the first phase difference φ1 in
30 consideration of the easiness of flow of the harmonic
current of each order through the load 3. Here, consider
the first to third loads 3A to 3C having different
frequency characteristics. FIG. 10 is a diagram
21
illustrating frequency characteristics of a plurality of
loads according to the first embodiment. In FIG. 10, the
horizontal axis represents the frequency, and the vertical
axis represents the magnitude of the impedance Z.
5 [0064] As illustrated in FIG. 10, assuming that the
output voltage frequency of the series multiplex inverter 1
is f0, the magnitude of the ninth impedance is small at the
first load 3A, facilitating the flow of the ninth harmonic
current through the first load 3A. Similarly, the seventh
10 harmonic current easily flows through the second load 3B,
and the fifth harmonic current easily flows through the
third load 3C. Namely, the first to third loads 3A to 3C
allow harmonic currents of different orders to easily flow
therethrough.
15 [0065] FIG. 11 is a diagram illustrating the
relationship between the first phase difference and the
harmonic current for the first load according to the first
embodiment. FIG. 12 is a diagram illustrating the
relationship between the first phase difference and the
20 harmonic current for the second load according to the first
embodiment. FIG. 13 is a diagram illustrating the
relationship between the first phase difference and the
harmonic current for the third load according to the first
embodiment. As illustrated in FIGS. 11 to 13, the ninth
25 harmonic current for the first load 3A, the seventh
harmonic current for the second load 3B, and the fifth
harmonic current for the third load 3C are dominant, and
harmonic currents of other orders hardly flow.
[0066] In the case of the first load 3A, as illustrated
30 in FIG. 11, the first phase difference φ1=5.0, 10.0, 15.0,
or 20.0 [deg] at which the ninth harmonic current is close
to 0 [A] is selected for generating a drive signal, whereby
the harmonic current can be greatly reduced. Therefore,
22
the harmonic filter 70 can be simplified or omitted. This
makes it possible to reduce the size and cost of the series
multiplex inverter 1.
[0067] Similarly, in the case of the second load 3B, as
5 illustrated in FIG. 12, the first phase difference φ1=6.4,
12.8, or 19.2 [deg] at which the seventh harmonic current
is close to 0 [A] is selected for generating a drive signal,
whereby the harmonic current can be greatly reduced. In
the case of the third load 3C, as illustrated in FIG. 13,
10 the first phase difference φ1=9.0 or 18.0 [deg] at which
the fifth harmonic current is close to 0 [A] is selected
for generating a drive signal, whereby the harmonic current
can be greatly reduced.
[0068] Reference is made back to FIG. 1 to continue the
15 explanation of the control unit 40 of the series multiplex
inverter 1. The phase difference selection unit 43 of the
control unit 40 acquires information input to the operation
unit 50, and inputs, to the drive signal output unit 42,
the information on the first phase difference φ1
20 corresponding to the input content to the operation unit 50.
[0069] The drive signal generation unit 41 generates the
n drive signals Sp on the basis of the first phase
difference φ1 input from the phase difference selection
unit 43 and the above-described second phase difference φ2.
25 Note that the operation unit 50 is, for example, a DIP
switch, but may be a detachable operation device.
[0070] The operation unit 50 is configured to receive
input of the value of the first phase difference φ1 itself.
In this case, the operation unit 50 can be, for example, a
30 DIP switch including a plurality of switches through which
a plurality of digits of the first phase difference φ1 can
be selected and input. Further, the operation unit 50 can
receive input of indirect information for setting the first
23
phase difference φ1, instead of the value of the first
phase difference φ1 itself. For example, the operation
unit 50 can receive input of information indicating which
of the first to third loads 3A to 3C the load 3 is. In
5 this case, the operation unit 50 can be a DIP switch that
can be switched in three stages, which facilitates input to
the operation unit 50.
[0071] As the first phase difference φ1 increases, the
maximum value of the output voltage Vo that can be output
10 from the power conversion unit 10 decreases. Therefore, it
is desirable that the first phase difference φ1 be set to a
relatively small value. For example, when information
indicating the first load 3A is input to the operation unit
50, the phase difference selection unit 43 selects 5.0
15 [deg] out of 5.0 [deg], 10.0 [deg], 15.0 [deg], and 20.0
[deg] as the first phase difference φ1. In this case, the
maximum value of the output voltage Vo that can be output
from the power conversion unit 10 can be prevented from
decreasing, as compared with the case where the first phase
20 difference φ1 is set to another value.
[0072] Similarly, when information indicating the second
load 3B is input to the operation unit 50, the phase
difference selection unit 43 selects 6.4 [deg] out of 6.4
[deg], 12.8 [deg], and 19.2 [deg] as the first phase
25 difference φ1. When information indicating the third load
3C is input to the operation unit 50, the phase difference
selection unit 43 selects 9.0 [deg] out of 9.0 [deg] and
18.0 [deg] as the first phase difference φ1. In this case,
the maximum value of the output voltage Vo that can be
30 output from the power conversion unit 10 can be prevented
from decreasing, as compared with the case where the first
phase difference φ1 is set to another value.
[0073] In the above-described examples, a single-order
24
harmonic current is dominant and harmonic currents of other
orders hardly flow. However, the series multiplex inverter
1 can suppress harmonic currents of a plurality of orders.
[0074] For suppressing harmonic currents of a plurality
5 of orders, the first phase difference φ1 having a value
that makes the values of the harmonic currents of the
plurality of orders equal to or less than a threshold value
is input to the operation unit 50, so that the harmonic
currents of the plurality of orders can be suppressed. In
10 this case, as described above, the first phase difference
φ1 is set to as small a value as possible, so that the
maximum value of the output voltage Vo that can be output
from the power conversion unit 10 can be prevented from
decreasing. Note that the threshold value can be the same
15 for a plurality of harmonic current orders, or different
for each harmonic current order.
[0075] As described above, the phase difference
selection unit 43 can select the first phase difference φ1
from among a plurality of phase difference candidates on
20 the basis of input to the operation unit 50. A plurality
of phase difference candidates is values that can be
selected by input to the operation unit 50. If information
that is provided to the phase difference selection unit 43
by input to the operation unit 50 is information indicating
25 which of the first to third loads 3A to 3C the loads 3 is,
a plurality of phase difference candidates is, for example,
5.0 [deg], 6.4 [deg], and 9.0 [deg].
[0076] In the example illustrated in FIG. 1, harmonic
currents of a plurality of orders flowing through the load
30 3 are kept below the threshold value through the selection
of the first phase difference φ1 and the harmonic filter 70.
Keeping harmonic currents of a plurality of orders below
the threshold value is advantageous, for example, in
25
reducing the effect of electromagnetic radiation from the
series multiplex inverter 1 on other electronic devices.
Further, because the harmonic current flowing through the
load 3 can be suppressed through the selection of the first
5 phase difference φ1, the harmonic filter 70 can be
simplified or omitted. This makes it possible to reduce
the cost and size of the harmonic filter 70 and eventually
reduce the cost and size of the series multiplex inverter 1.
[0077] In a case where harmonic currents of a plurality
10 of orders flowing through the load 3 can be kept below the
threshold value through the selection of the first phase
difference φ1 alone, the harmonic filter 70 may not be
provided in the series multiplex inverter 1. With no
harmonic filter 70 provided, the cost and size of the
15 series multiplex inverter 1 can be prevented from
increasing.
[0078] In the above-described examples, the phase
difference selection unit 43 selects the first phase
difference φ1 from among a plurality of phase difference
20 candidates on the basis of input to the operation unit 50.
Alternatively, the phase difference selection unit 43 can
select the first phase difference φ1 from among a plurality
of phase difference candidates on the basis of an external
signal. For example, the phase difference selection unit
25 43 can select, as the first phase difference φ1, a phase
difference candidate that varies depending on whether first
information or second information is acquired from the
outside. The first information is, for example,
information that is output from the outside when the state
30 of the load 3 is switched to the characteristics of the
first load 3A, and the second information is, for example,
information that is input from the outside when the state
of the load 3 is switched to the characteristics of the
26
second load 3B. Note that information that is input from
the outside may be the value of the first phase difference
φ1 itself.
[0079] Next, the operation of the control unit 40 will
5 be described using a flowchart. FIG. 14 is a flowchart
illustrating an exemplary process that is performed by the
control unit according to the first embodiment. As
illustrated in FIG. 14, the control unit 40 generates the n
drive signals Sp on the basis of the first phase difference
10 φ1 selected by input to the operation unit 50 (step S11).
Next, the control unit 40 outputs the n drive signals Sp
generated in step S11 to the n single-phase inverters 15
(step S12). The control unit 40 repeatedly performs the
process illustrated in FIG. 14.
15 [0080] Here, a hardware configuration of the control
unit 40 of the series multiplex inverter 1 according to the
first embodiment will be described. FIG. 15 is a diagram
illustrating an exemplary hardware configuration of the
control unit of the series multiplex inverter according to
20 the first embodiment. As illustrated in FIG. 15, the
control unit 40 of the series multiplex inverter 1 includes
a processor 101, a memory 102, and an input/output circuit
103. The processor 101, the memory 102, and the
input/output circuit 103 can exchange data with one another
25 via a bus 104. The memory 102 includes a recording medium
on which a computer-readable program is recorded.
[0081] The processor 101 reads and executes a program
stored in the memory 102 to execute the functions of the
drive signal generation unit 41, the drive signal output
30 unit 42, and the phase difference selection unit 43
described above. The processor 101 is an example of a
processing circuit, and includes, for example, one or more
of a central processing unit (CPU), a digital signal
27
processer (DSP), and a system large scale integration (LSI).
Examples of the memory 102 include a non-volatile or
volatile semiconductor memory, a magnetic disk, a flexible
disk, an optical disc, a compact disc, a mini disc, a
5 digital versatile disc (DVD), and the like. Examples of
the non-volatile or volatile semiconductor memory include a
random access memory (RAM), a read only memory (ROM), a
flash memory, an erasable programmable read only memory
(EPROM), an electrically erasable programmable read-only
10 memory (EEPROM, registered trademark), and the like.
[0082] Note that the control unit 40 described above may
be implemented by dedicated hardware that implements the
same functions as the processor 101 and the memory 102
illustrated in FIG. 15. Dedicated hardware is, for example,
15 a single circuit, a composite circuit, a programmed
processor, a parallel programmed processor, an application
specific integrated circuit (ASIC), a field programmable
gate array (FPGA), or a processing circuit including a
combination thereof. A part of the control unit 40 may be
20 implemented by dedicated hardware, and the rest of the
control unit 40 may be implemented by the processor 101 and
the memory 102 illustrated in FIG. 15.
[0083] As described above, the series multiplex inverter
1 according to the first embodiment includes the power
25 conversion unit 10, the phase difference selection unit 43,
the drive signal generation unit 41, and the drive signal
output unit 42. The power conversion unit 10 includes the
plurality of single-phase inverters 151 to 15n, and the
output terminals 161, 171, 162, 172,..., 16n-1, 17n-1, 16n,
30 and 17n of the plurality of single-phase inverters 151 to
15n are connected in series. The phase difference
selection unit 43 selects, from among a plurality of phase
difference candidates, the first phase difference φ1 which
28
is the phase difference between rectangular wave voltages
from the plurality of single-phase inverters 151 to 15n.
The drive signal generation unit 41 generates the plurality
of drive signals Sp1 to Spn that causes different ones of
5 the different single-phase inverters 151 to 15n to output a
plurality of rectangular wave voltages sequentially out of
phase by the first phase difference φ1 selected by the
phase difference selection unit 43. The drive signal
output unit 42 outputs the plurality of drive signals Sp1
10 to Spn generated by the drive signal generation unit 41, to
the plurality of single-phase inverters 15. Therefore, the
series multiplex inverter 1 selects, from among a plurality
of phase difference candidates, the first phase difference
φ1 that can suppress the harmonic current flowing through
15 the load 3, so that the harmonic current flowing through
the load 3 can be easily suppressed by controlling each
single-phase inverter 15 even when the characteristics of
the load 3 vary. The harmonic current flowing through the
load 3 may not be sufficiently suppressed through the
20 selection of the first phase difference φ1 alone. In this
case, however, the harmonic filter 70 having a small
harmonic reduction effect can be used, as compared with the
case where the first phase difference φ1 cannot be selected.
Consequently, the harmonic filter 70 can be reduced in size
25 or omitted, so that the cost and size of the series
multiplex inverter 1 can be prevented from increasing.
[0084] The series multiplex inverter 1 includes the
operation unit 50 that receives external input. The phase
difference selection unit 43 selects the first phase
30 difference φ1 from among a plurality of phase difference
candidates on the basis of input to the operation unit 50.
Consequently, for example, the first phase difference φ1
suitable for the characteristics of the load 3 connected to
29
the series multiplex inverter 1 can be easily selected by
the installer of the series multiplex inverter 1 operating
the operation unit 50.
[0085] Second Embodiment
5 The second embodiment is different from the first
embodiment in that the impedance of the load 3 is detected
so that the first phase difference φ1 can be selected from
among a plurality of phase difference candidates on the
basis of the detected impedance. In the following
10 description, components having the same functions as those
in the first embodiment are denoted by the same reference
signs, and descriptions thereof are omitted. The
difference from the series multiplex inverter 1 according
to the first embodiment is mainly described.
15 [0086] FIG. 16 is a diagram illustrating an exemplary
configuration of a series multiplex inverter according to
the second embodiment. As illustrated in FIG. 16, the
series multiplex inverter 1A according to the second
embodiment includes the power conversion unit 10, the
20 voltage detection unit 20, the current detection unit 30,
and a control unit 40A.
[0087] The control unit 40A includes the drive signal
generation unit 41, the drive signal output unit 42, a
phase difference selection unit 43A, an impedance detection
25 unit 44, and a harmonic current calculation unit 45.
[0088] The impedance detection unit 44 detects the
impedance Zm (m=3, 5, 7, or 9), for the harmonic of each
order, of the load 3 connected to the power conversion unit
10 on the basis of the output voltage Vo detected by the
30 voltage detection unit 20 and the output current Io
detected by the current detection unit 30. Note that the
impedance Zm is not limited to the impedance for the ninth
or lower-order harmonic, and may include the impedance for
30
the eleventh or higher-order harmonic. That is, the
impedance detection unit 44 can calculate the impedance for
harmonics of a plurality of orders set in advance.
[0089] For example, the impedance detection unit 44
5 acquires the detected voltage value Vdet repeatedly output
from the voltage detection unit 20 and the detected current
value Idet repeatedly output from the current detection
unit 30. Then, the impedance detection unit 44 performs a
discrete Fourier transform on the detected voltage value
10 Vdet and the detected current value Idet, using a sampling
period that is an integral multiple of the output voltage
frequency fo. Through the discrete Fourier transform, the
impedance detection unit 44 extracts the harmonic component
of each order included in the output current Io and the
15 harmonic component of each order included in the output
voltage Vo. Hereinafter, the m-order harmonic component
included in the output voltage Vo is referred to as the
harmonic voltage Vom, and the m-order harmonic component
included in the output current Io is referred to as the
20 harmonic current Iom. Note that “m” is a positive odd
number equal to or greater than three.
[0090] Note that, instead of the discrete Fourier
transform, the impedance detection unit 44 can use a method
and algorithm for extracting a plurality of high-order
25 frequency components included in the output current Io to
extract the harmonic component of each order of the output
current Io and the harmonic component of each order of the
output voltage Vo.
[0091] In a case where the Fourier transform is
30 performed by the impedance detection unit 44, the m-order
harmonic voltage Vom included in the output voltage Vo and
the m-order harmonic current Iom included in the output
current Io are expressed in complex notation by Formulas
31
(4) and (5) below. In Formulas (4) and (5) below, “VomRe”’
indicates the real part of Vom, “IomRe” indicates the real
part of Iom, “VomIm” indicates the imaginary part of Vom,
“IomIm” indicates the imaginary part of Iom, and “j”
5 indicates an imaginary unit.
Vom=VomRe+j×VomIm... (4)
Iom=IomRe+j×IomIm... (5)
[0092] The impedance detection unit 44 can compute the
impedance Zm through calculations of Formulas (6) and (7)
10 below. In Formula (7), Re(Zm) indicates the real part of
the impedance Zm, and Re(Zm) indicates the real part of the
impedance Zm.
Zm=Vom/Iom... (6)
|Zm|=√(Re(Zm)2+Im(Zm)2)... (7)
15 [0093] Note that the impedance detection unit 44 can
also cause the drive signal generation unit 41 to generate
the drive signals Sp1 to Spn for sweeping the output
voltage frequency fo. In this case, the drive signal
output unit 42 outputs, to the single-phase inverters 151
20 to 15n, the drive signals Sp1 to Spn output from the drive
signal generation unit 41, so that the power conversion
unit 10 causes the output voltage Vo whose output voltage
frequency fo sweeps to be output from the series multiplex
inverter 1A to the load 3. The impedance detection unit 44
25 can also calculate the impedance Zm for the harmonic of
each order on the basis of the detected voltage value Vdet
and the detected current value Idet obtained when the
output voltage frequency fo is the frequency of the
harmonic of each order.
30 [0094] On the basis of the impedance Zm of the load 3
detected by the impedance detection unit 44 and the
theoretical formula for harmonic voltage expressed by
Formula (3) above, the harmonic current calculation unit 45
32
calculates the harmonic current of each order flowing
through the load 3. For example, the harmonic current
calculation unit 45 can change the value of the first phase
difference φ1 in Formula (3) above to thereby compute the
5 harmonic voltage Vom for each value of the first phase
difference φ1 on the basis of Formula (3) above.
[0095] The phase difference selection unit 43A selects,
from among a plurality of phase difference candidates, the
first phase difference φ1 that makes the harmonic current
10 Iom of each order detected by the harmonic current
calculation unit 45 equal to or less than the threshold
value Ith. The threshold value Ith can be common to the
harmonic current Iom of each order, or the threshold value
Ith can be different for the harmonic current Iom of each
15 order.
[0096] Next, a process that is performed by the control
unit 40A will be described using a flowchart. FIG. 17 is a
flowchart illustrating an exemplary process that is
performed by the control unit according to the second
20 embodiment. As illustrated in FIG. 17, the control unit
40A detects the impedance Zm for the harmonic of each order
(step S21).
[0097] Next, the control unit 40A calculates the
harmonic current Iom of each order on the basis of the
25 impedance Zm of the load 3 (step S22). The control unit
40A selects the first phase difference φ1 that makes the
harmonic current Iom of each order equal to or less than
the threshold value Ith (step S23). The process
illustrated in FIG. 17 is started by the control unit 40A
30 when, for example, a button (not illustrated) provided on
the series multiplex inverter 1A is pressed. Further, the
control unit 40A can execute the process illustrated in FIG.
17 at a preset timing. A preset timing is a timing that
33
can be freely set, and may be, for example, a timing that
occurs once a preset period such as once a day and once a
month.
[0098] An exemplary hardware configuration of the
5 control unit 40A of the series multiplex inverter 1A
according to the second embodiment is the same as the
exemplary hardware configuration illustrated in FIG. 15.
The processor 101 can read and execute a program stored in
the memory 102 to execute the functions of the drive signal
10 generation unit 41, the drive signal output unit 42, the
phase difference selection unit 43A, the impedance
detection unit 44, and the harmonic current calculation
unit 45.
[0099] As described above, the series multiplex inverter
15 1A according to the second embodiment includes the voltage
detection unit 20, the current detection unit 30, the
impedance detection unit 44, and the harmonic current
calculation unit 45. The voltage detection unit 20 detects
the output voltage Vo from the power conversion unit 10.
20 The current detection unit 30 detects the output current Io
from the power conversion unit 10. The impedance detection
unit 44 detects the impedance Zm of the load 3 connected to
the power conversion unit 10 on the basis of the output
voltage Vo detected by the voltage detection unit 20 and
25 the output current Io detected by the current detection
unit 30. The harmonic current calculation unit 45
calculates the harmonic currents Iom of a plurality of
orders flowing through the load 3 on the basis of the
impedance Zm of the load 3 detected by the impedance
30 detection unit 44. The phase difference selection unit 43A
selects, from among a plurality of phase difference
candidates, the first phase difference φ1 that makes the
harmonic currents Iom of the plurality of orders detected
34
by the harmonic current calculation unit 45 equal to or
less than the threshold value Ith. Consequently, the first
phase difference φ1 having an appropriate value is
automatically selected without manual setting of the first
5 phase difference φ1, so that the harmonic current Iom
flowing through the load 3 can be easily suppressed.
[0100] In a case where two or more of the plurality of
phase difference candidates make the harmonic currents Iom
of the plurality of orders equal to or less than the
10 threshold value Ith, the phase difference selection unit
43A selects, as the first phase difference φ1, the smallest
phase difference candidate of the two or more phase
difference candidates that make the harmonic currents Iom
of the plurality of orders equal to or less than the
15 threshold value Ith. In this case, the maximum value of
the output voltage Vo that can be output from the power
conversion unit 10 can be prevented from decreasing, as
compared with the case where the first phase difference φ1
is set to another value.
20 [0101] Although the above-described series multiplex
inverters 1 and 1A include the n transformers 12, the
series multiplex inverters 1 and 1A may include one multioutput
transformer instead of the n transformers 12. In
this case, the primary side of the multi-output transformer
25 is connected to the single-phase AC power supply 2, and AC
voltage is output from the n secondary sides of the multioutput
transformer to the n rectifier circuits 13.
[0102] In the above-described examples, the single-phase
AC voltage Vac from the single-phase AC power supply 2 is
30 converted into the DC voltage Vdc. However, the power
supply is not limited to the single-phase AC power supply 2.
For example, the series multiplex inverters 1 and 1A may be
configured to convert three-phase AC voltage from a three35
phase AC power supply, in place of the single-phase AC
power supply 2, into the DC voltage Vdc. In this case, a
three-phase transformer is used as the transformer 12, and
a three-phase rectifier circuit is used as the rectifier
5 circuit 13, whereby three-phase AC voltage can be converted
into the DC voltage Vdc.
[0103] In the above-described examples, the DC voltage
Vdc is input to each single-phase inverter 15 from an
independent DC power supply including the transformer 12,
10 the rectifier circuit 13, and the capacitor 14.
Alternatively, the DC voltage Vdc may be input from one DC
power supply to the n single-phase inverters 15. In this
case, the output voltages VINV from the individual singlephase
inverters 15 are input to the primary sides of n
15 transformers provided on a single-phase-inverter-by-singlephase
inverter basis. The secondary sides of the n
transformers are connected in series, whereby the output
voltages VINV from the single-phase inverters 15 are
combined and output to the load 3.
20 [0104] The configurations described in the abovementioned
embodiments indicate examples of the contents of
the present invention. The configurations can be combined
with another well-known technique, and some of the
configurations can be omitted or changed in a range not
25 departing from the gist of the present invention.
Reference Signs List
[0105] 1, 1A series multiplex inverter; 2 single-phase
AC power supply; 3, 3A, 3B, 3C load; 10 power conversion
30 unit; 111 to 11n power conversion block; 12, 121 to 12n
transformer; 13, 131 to 13n rectifier circuit; 14, 141 to
14n capacitor; 15, 151 to 15n single-phase inverter; 161
to 16n, 171 to 17n output terminal; 18 gate driver; 20
36
voltage detection unit; 30 current detection unit; 40, 40A
control unit; 41 drive signal generation unit; 42 drive
signal output unit; 43, 43A phase difference selection
unit; 44 impedance detection unit; 45 harmonic current
5 calculation unit; 50 operation unit; 60 effective value
calculation unit; 61 current command output unit; 62
subtractor; 63 current control unit; 64 carrier wave
output unit; 65 comparator; 66 signal generation unit; 70
harmonic filter; Sp, Sp1 to Spn drive signal.
10
37
We Claim:
1. A series multiplex inverter comprising:
5 a power conversion unit including a plurality of
single-phase inverters having output terminals connected in
series;
a phase difference selection unit to select, from
among a plurality of phase difference candidates, a phase
10 difference between rectangular wave voltages from the
plurality of single-phase inverters;
a drive signal generation unit to generate a plurality
of drive signals that causes different single-phase
inverters to output a plurality of rectangular wave
15 voltages sequentially out of phase by the phase difference
selected by the phase difference selection unit; and
a drive signal output unit to output the plurality of
drive signals generated by the drive signal generation unit
to the plurality of single-phase inverters.
20
2. The series multiplex inverter according to claim 1,
comprising
an operation unit to receive input, wherein
the phase difference selection unit selects the phase
25 difference from among the plurality of phase difference
candidates on a basis of the input to the operation unit.
3. The series multiplex inverter according to claim 1,
comprising:
30 a voltage detection unit to detect an output voltage
from the power conversion unit;
a current detection unit to detect an output current
from the power conversion unit;
38
an impedance detection unit to detect an impedance of
a load connected to the power conversion unit, on the basis
of the output voltage detected by the voltage detection
unit and the output current detected by the current
5 detection unit; and
a harmonic current calculation unit to calculate
harmonic currents of a plurality of orders flowing through
the load on the basis of the impedance of the load detected
by the impedance detection unit, wherein
10 the phase difference selection unit selects, from
among the plurality of phase difference candidates, the
phase difference that makes the harmonic currents of the
plurality of orders detected by the harmonic current
calculation unit equal to or less than a threshold value.
15
4. The series multiplex inverter according to claim 3,
wherein
in a case where two or more of the plurality of phase
difference candidates make the harmonic currents of the
20 plurality of orders equal to or less than the threshold
value, the phase difference selection unit selects, as the
phase difference, a smallest phase difference candidate of
the two or more phase difference candidates that make the
harmonic currents of the plurality of orders equal to or
25 less than the threshold value.