FORM 2
THE PATENTS ACT, 1970
(39 of& 1970) THE PATENTS RULES, 2003 COMPLETE SPECIFICATION
[See section 10, Rule 13]
SERIES MULTIPLEX INVERTER;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANISED
AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3,
MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 1008310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.
2
DESCRIPTION
Field
[0001] The present invention relates to a series
5 multiplex inverter including a plurality of single-phase
inverters having output terminals connected in series.
Background
[0002] Conventionally known series multiplex inverters
10 cause a plurality of single-phase inverters to output
rectangular wave voltages out of phase with each other,
combine the rectangular wave voltages, and output the
combined voltage. Regarding this type of series multiplex
inverter, Patent Literature 1 discloses a technique of
15 exchanging, among a plurality of single-phase inverters,
timings at which a plurality of pulse width modulation
(PWM) signals corresponding one-to-one to the single-phase
inverters changes. As a result, the length of time during
which a rectangular wave voltage is output from each
20 single-phase inverter is equalized.
Citation List
Patent Literature
[0003] Patent Literature 1: Japanese Patent Application
25 Laid-open No. 2006-320103
Summary
Technical Problem
[0004] For the above-described conventional series
30 multiplex inverter, the length of time during which a
rectangular wave voltage is output can be equalized among
the single-phase inverters. However, because the output
power from each single-phase inverter is determined as the
3
product of the instantaneous output voltage and the
instantaneous output current from each single-phase
inverter, the above-described conventional series multiplex
inverter poses the problem of large variations in output
5 power among the single-phase inverters.
[0005] The present invention has been made in view of
the above, and an object thereof is to obtain a series
multiplex inverter capable of equalizing the output power
among single-phase inverters.
10
Solution to Problem
[0006] In order to solve the above-described problems
and achieve the object, a series multiplex inverter of the
present invention includes a power conversion unit, a drive
15 signal generation unit, and a drive signal output unit.
The power conversion unit includes n single-phase inverters,
where n is an integer of three or more, and the n singlephase
inverters have output terminals connected in series.
The drive signal generation unit generates n drive signals
20 that cause different single-phase inverters of the n
single-phase inverters to output n rectangular wave
voltages sequentially out of phase. The drive signal
output unit outputs the n drive signals to the n singlephase
inverters in rotation that shifts, by p every m-fold
25 time of half an output voltage period of the power
conversion unit, the single-phase inverters corresponding
one-to-one to the n drive signals in a combination of the n
drive signals with different single-phase inverters of the
n single-phase inverters, where m is a natural number and p
30 is a natural number relatively prime to n or one.
Advantageous Effects of Invention
[0007] The present invention can achieve the effect of
4
equalizing the output power between single-phase inverters.
Brief Description of Drawings
[0008] FIG. 1 is a diagram illustrating an exemplary
5 configuration of a series multiplex inverter according to a
first embodiment of the present invention.
FIG. 2 is a diagram illustrating an exemplary
configuration of a single-phase inverter according to the
first embodiment.
10 FIG. 3 is a diagram illustrating the relationship
between gate signals output from a gate driver and the
waveform of the output voltage from a single-phase inverter
according to the first embodiment.
FIG. 4 is a diagram illustrating an exemplary
15 configuration of a drive signal generation unit according
to the first embodiment.
FIG. 5 is a diagram illustrating an example of output
voltages from a plurality of single-phase inverters
according to the first embodiment.
20 FIG. 6 is a diagram illustrating an example of output
voltages from a plurality of single-phase inverters
according to the first embodiment.
FIG. 7 is a diagram illustrating an example of output
voltages from a plurality of single-phase inverters
25 according to the first embodiment.
FIG. 8 is a diagram illustrating an example of the
waveform of an output voltage and the waveform of an output
current from the series multiplex inverter according to the
first embodiment.
30 FIG. 9 is a diagram illustrating an example of the
waveform of an output voltage and the waveform of an output
current from the series multiplex inverter according to the
first embodiment.
5
FIG. 10 is a diagram illustrating an example of the
waveform of an output voltage and the waveform of an output
power from each single-phase inverter in the state
illustrated in FIG. 9.
5 FIG. 11 is a diagram illustrating an example of the
waveform of an output voltage and the waveform of an output
current in the case of a current delay phase in the series
multiplex inverter according to the first embodiment.
FIG. 12 is a diagram illustrating an example of the
10 waveform of an output voltage and the waveform of an output
current in the case of a current delay phase in the series
multiplex inverter according to the first embodiment.
FIG. 13 is a diagram illustrating an example of the
waveform of an output voltage and the waveform of an output
15 power from each single-phase inverter in the state
illustrated in FIG. 12.
FIG. 14 is a diagram illustrating an example of the
relationship between output voltage, output current, and
output timings in the case of a current delay phase in the
20 series multiplex inverter according to the first embodiment.
FIG. 15 is a diagram illustrating an example of the
relationship between output power, output current, and
output timings in the case of a current delay phase in the
series multiplex inverter according to the first embodiment.
25 FIG. 16 is a diagram illustrating an example of the
output timing at which each single-phase inverter outputs a
rectangular wave voltage on an update-period-by-updateperiod
basis.
FIG. 17 is a diagram illustrating an example of the
30 relationship between output voltage, output current, and
output timings for the case of a lead phase in the series
multiplex inverter according to the first embodiment.
FIG. 18 is a diagram illustrating an example of the
6
relationship between output power, output current, and
output timings for the case of a lead phase in the series
multiplex inverter according to the first embodiment.
FIG. 19 is a diagram illustrating another example of
5 the output timing at which each single-phase inverter
outputs a rectangular wave voltage on an update-period-byupdate-
period basis.
FIG. 20 is a flowchart illustrating an exemplary
process that is performed by a control unit according to
10 the first embodiment.
FIG. 21 is a diagram illustrating an exemplary
hardware configuration of the control unit of the series
multiplex inverter according to the first embodiment.
FIG. 22 is a diagram illustrating an exemplary
15 configuration of a series multiplex inverter according to a
second embodiment.
FIG. 23 is a flowchart illustrating an exemplary
determination process that is performed by a control unit
according to the second embodiment.
20
Description of Embodiments
[0009] Hereinafter, series multiplex inverters according
to embodiments of the present invention will be described
in detail based on the drawings. The present invention is
25 not limited to the embodiments.
[0010] First Embodiment
FIG. 1 is a diagram illustrating an exemplary
configuration of a series multiplex inverter according to
the first embodiment of the present invention. As
30 illustrated in FIG. 1, the series multiplex inverter 1
according to the first embodiment includes a power
conversion unit 10, a voltage detection unit 20, a current
detection unit 30, a control unit 40, and an operation unit
7
50. The control unit 40 controls the power conversion unit
10 such that the output voltage Vo is output from the power
conversion unit 10.
[0011] The power conversion unit 10 can convert AC power
5 output from a single-phase AC power supply 2 into AC power
having some frequency and amplitude. For example, the
power conversion unit 10 can convert AC power output from
the single-phase AC power supply 2 into high-frequency AC
power of 1 kHz or more. Note that the power conversion
10 unit 10 can also convert AC power output from the singlephase
AC power supply 2 into AC power having a frequency of
less than 1 kHz.
[0012] The power conversion unit 10 includes n power
conversion blocks 111 to 11n. Here, “n” is an integer of
15 three or more. The power conversion block 111 includes a
transformer 121, a rectifier circuit 131, a capacitor 141,
and a single-phase inverter 151. The power conversion
block 112 includes a transformer 122, a rectifier circuit
132, a capacitor 142, and a single-phase inverter 152.
20 [0013] Similarly to the power conversion blocks 111 and
112, each of the power conversion blocks 113 to 11n includes
one of transformers 123 to 12n, one of rectifier circuits
133 to 13n, one of capacitors 143 to 14n, and one of singlephase
inverters 153 to 15n. The power conversion blocks 111
25 to 11n have the same configuration, as stated above.
Hereinafter, therefore, the configuration of the power
conversion block 111 will be described in detail.
[0014] The primary winding of the transformer 121 is
connected to the single-phase AC power supply 2. The
30 transformer 121 converts the AC voltage Vac output from the
single-phase AC power supply 2 into an AC voltage having an
amplitude that depends on the winding ratio of the
transformer 121, and outputs the AC voltage.
8
[0015] The rectifier circuit 131 is connected to the
secondary winding of the transformer 121, and rectifies the
AC voltage output from the transformer 121. The rectifier
circuit 131 is, for example, a full-wave rectifier circuit,
5 a half-wave rectifier circuit, or a full-bridge circuit.
Note that the rectifier circuit 131 only needs to be able
to rectify the AC voltage output from the transformer 121,
and is not necessarily a full-wave rectifier circuit, a
half-wave rectifier circuit, or a full-bridge circuit.
10 [0016] The capacitor 141 smooths the output voltage from
the rectifier circuit 131. The rectifier circuit 131 and
the capacitor 141 convert the AC voltage output from the
transformer 121 into the DC voltage Vdc.
[0017] The single-phase inverter 151 is controlled by
15 the control unit 40, such that the single-phase inverter
151 can convert the DC voltage Vdc generated by the
rectifier circuit 131 and the capacitor 141 into a
rectangular wave voltage and output the rectangular wave
voltage.
20 [0018] The power conversion blocks 112 to 11n generate
and output rectangular wave voltages, similarly to the
power conversion block 111. Hereinafter, the voltages
output from the single-phase inverters 151 to 15n will be
respectively referred to as the output voltages VINV1 to
25 VINVn for easy understanding. Note that the output voltages
VINV1 to VINVn may be collectively referred to as the output
voltage VINV.
[0019] Output terminals 161, 171, 162, 172,..., 16n-1, 17n-
1, 16n, and 17n of the single-phase inverters 151 to 15n are
30 connected in series. Consequently, the output voltages
VINV1 to VINVn from the single-phase inverters 151 to 15n are
combined, and a result of the combination is output as the
output voltage Vo from the power conversion unit 10.
9
[0020] The output voltage Vo from the power conversion
unit 10 is supplied to a load 3. In the series multiplex
inverter 1 illustrated in FIG. 1, the output voltage Vo
from the power conversion unit 10 is directly supplied to
5 the load 3. Alternatively, the series multiplex inverter 1
may include a harmonic filter or harmonic transformer (not
illustrated) between the power conversion unit 10 and the
load 3. The harmonic filter is, for example, an LC filter.
[0021] Hereinafter, the transformers 121 to 12n may be
10 collectively referred to as the transformer 12, and the
rectifier circuits 131 to 13n may be collectively referred
to as the rectifier circuit 13. The capacitors 141 to 14n
may be collectively referred to as the capacitor 14, and
the single-phase inverters 151 to 15n may be collectively
15 referred to as the single-phase inverter 15.
[0022] In the exemplary configuration illustrated in FIG.
1, each of the power conversion blocks 111 to 11n includes
the transformer 12, the rectifier circuit 13, and the
capacitor 14. Alternatively, a DC power supply that
20 outputs the DC voltage Vdc may be provided instead of the
transformer 12, the rectifier circuit 13, and the capacitor
14.
[0023] FIG. 2 is a diagram illustrating an exemplary
configuration of a single-phase inverter according to the
25 first embodiment. As illustrated in FIG. 2, the singlephase
inverter 151 includes four switching elements Q1 to
Q4 connected in full bridge configuration, diodes D1 to D4
connected in anti-parallel to the switching elements Q1 to
Q4, respectively, and a gate driver 18.
30 [0024] The gate driver 18 generates gate signals Sg1 to
Sg4 on the basis of a drive signal (described later) output
from the control unit 40, and outputs each of the generated
gate signals Sg1 to Sg4 to the corresponding one of the
10
gates of the switching elements Q1 to Q4. Consequently,
the switching elements Q1 to Q4 are subjected to on/off
control, such that the output voltage VINV1 is generated and
output by the single-phase inverter 151. The switching
5 elements Q1 to Q4 are semiconductor switching elements
represented by metal-oxide-semiconductor field-effect
transistors (MOSFETs) and insulated gate bipolar
transistors (IGBTs).
[0025] FIG. 3 is a diagram illustrating the relationship
10 between gate signals output from a gate driver and the
waveform of the output voltage from a single-phase inverter
according to the first embodiment. As illustrated in FIG.
3, the output voltage VINV1 including a rectangular wave
voltage is generated by the gate signals Sg1 to Sg4. In
15 FIG. 3, “To” is an output voltage period indicating the
fundamental period of the output voltage Vo from the series
multiplex inverter 1. In addition, “+Va” is the voltage
value of a positive rectangular wave voltage output from
the single-phase inverter 151, and “−Va” is the voltage
20 value of a negative rectangular wave voltage output from
the single-phase inverter 151.
[0026] A drive signal output from the control unit 40 to
the single-phase inverter 15 includes four pulse width
modulation signals having the same waveform as the
25 respective gate signals Sg1 to Sg4, and is amplified by the
gate driver 18 and output to the switching elements Q1 to
Q4. Note that this is a non-limiting example of a drive
signal, and any drive signal can be used as long as the
gate driver 18 can generate the gate signals Sg1 to Sg4 on
30 the basis of the drive signal from the control unit 40.
For example, a drive signal output from the control unit 40
to each single-phase inverter 15 may include one or two PWM
signals. That is, the gate driver 18 may be configured to
11
generate and output the gate signals Sg1 to Sg4 from a
drive signal including one or two PWM signals.
[0027] The single-phase inverters 152 to 15n have the
same configuration as the single-phase inverter 151. Note
5 that the single-phase inverters 151 to 15n are not limited
to the configuration illustrated in FIG. 2. That is, the
single-phase inverters 151 to 15n only need to be able to
output the output voltages VINV1 to VINVn (described later),
and do not necessarily have the configuration illustrated
10 in FIG. 2.
[0028] Reference is made back to FIG. 1 to continue the
explanation of the series multiplex inverter 1. The
voltage detection unit 20 of the series multiplex inverter
1 repeatedly detects the instantaneous value of the output
15 voltage Vo from the power conversion unit 10, and outputs
the detected voltage value Vdet that is the detected
instantaneous value of the output voltage Vo. The current
detection unit 30 of the series multiplex inverter 1
repeatedly detects the instantaneous value of the output
20 current Io from the power conversion unit 10, and outputs
the detected current value Idet that is the detected
instantaneous value of the output current Io.
[0029] The control unit 40 of the series multiplex
inverter 1 includes a drive signal generation unit 41, a
25 drive signal output unit 42, and an operation receiving
unit 43. The drive signal output unit 42 generates n drive
signals Sp1 to Spn. The drive signal output unit 42
outputs the n drive signals Sp1 to Spn to the n singlephase
inverters 151 to 15n. Hereinafter, the drive signals
30 Sp1 to Spn may be collectively referred to as the drive
signal Sp.
[0030] The drive signal generation unit 41 generates the
n drive signals Sp by constant output current control on
12
the basis of the detected current value Idet. Each drive
signal Sp includes, for example, a plurality of PWM signals
as described above. Note that the drive signal generation
unit 41 can also generate the n drive signals Sp by
5 constant output voltage control or constant output power
control. For example, the drive signal generation unit 41
can generate the n drive signals Sp by constant output
voltage control on the basis of the detected voltage value
Vdet.
10 [0031] The drive signal generation unit 41 can generate
the n drive signals Sp by constant output power control on
the basis of the detected voltage value Vdet and the
detected current value Idet. In a case where the drive
signal generation unit 41 performs only constant output
15 current control, the voltage detection unit 20 may not be
provided.
[0032] The drive signals Sp1 to Spn are signals that
cause different single-phase inverters of the n singlephase
inverters 15 to output n rectangular wave voltages
20 sequentially out of phase by the first phase difference φ1
(described later). Hereinafter, an exemplary configuration
of the drive signal generation unit 41 will be described.
[0033] FIG. 4 is a diagram illustrating an exemplary
configuration of the drive signal generation unit according
25 to the first embodiment. As illustrated in FIG. 4, the
drive signal generation unit 41 includes an effective value
calculation unit 60, a current command output unit 61, a
subtractor 62, a current control unit 63, a carrier wave
output unit 64, a comparator 65, and a signal generation
30 unit 66.
[0034] The effective value calculation unit 60
calculates the output current effective value Iom, which is
the effective value of the output current Io, on the basis
13
of the detected current value Idet output from the current
detection unit 30. The effective value calculation unit 60
calculates the output current effective value Iom, for
example, every half output voltage period To. The output
5 voltage period To is the fundamental period of the output
voltage Vo as described above, and To=1/fo is satisfied.
Note that “fo” is the frequency of the output voltage Vo,
and is hereinafter referred to as the output voltage
frequency fo.
10 [0035] The current command output unit 61 outputs the
current command Iref. The value of the current command
Iref is generated by the current command output unit 61 on
the basis of, for example, information supplied from the
outside to the current command output unit 61.
15 [0036] The subtractor 62 subtracts the output current
effective value Iom from the current command Iref, and
outputs the current difference value ΔI as the result of
the subtraction. The current control unit 63 generates the
voltage command Vref on the basis of the current difference
20 value ΔI output from the subtractor 62. The current
control unit 63 can generate the voltage command Vref by,
for example, proportional integral control or proportional
integral derivative control.
[0037] The carrier wave output unit 64 generates the
25 carrier wave Vcs and outputs the generated carrier wave Vcs.
The carrier wave Vcs is, for example, a voltage having a
triangular waveform or a voltage having a sawtooth waveform.
The output voltage period To is the same as the period of
the carrier wave Vcs. When the period of the carrier wave
30 Vcs changes, the output voltage period To changes.
[0038] The comparator 65 compares the voltage command
Vref with the carrier wave Vcs, and outputs the result of
the comparison. Specifically, the comparator 65 outputs
14
the first voltage V1 when the voltage command Vref is
larger than the carrier wave Vcs, and outputs the second
voltage V2 different from the first voltage V1 when the
voltage command Vref is smaller than the carrier wave Vcs.
5 [0039] The signal generation unit 66 generates the n
drive signals Sp1 to Spn on the basis of the voltage output
from the comparator 65. The signal generation unit 66 has
information indicating the first phase difference φ1. The
signal generation unit 66 also determines the second phase
10 difference φ2 on the basis of the duty ratio of the voltage
output from the comparator 65. For example, the signal
generation unit 66 determines the second phase difference
φ2 such that the shorter the time during which the second
voltage V2 is output from the comparator 65 is, the smaller
15 the second phase difference φ2 is, in half period of the
carrier wave Vcs.
[0040] The signal generation unit 66 generates the n
drive signals Sp1 to Spn on the basis of the first phase
difference φ1 and the second phase difference φ2. The
20 signal generation unit 66 outputs the generated n drive
signals Sp1 to Spn to the drive signal output unit 42
illustrated in FIG. 1.
[0041] The drive signal output unit 42 determines a
pattern of a combination of the drive signals Sp1 to Spn
25 with the single-phase inverters 151 to 15n at each update
period Ts set in advance. The drive signal output unit 42
outputs the drive signals Sp1 to Spn to the single-phase
inverters 151 to 15n in accordance with the determined
pattern of the combination of the drive signals Sp1 to Spn
30 with the single-phase inverters 151 to 15n. Note that
Ts=To/2×m is satisfied, where m is a natural number.
[0042] The single-phase inverters 151 to 15n output the
output voltages VINV1 to VINVn from the output terminals 161,
15
171, 162, 172,..., 16n-1, 17n-1, 16n, and 17n on the basis of
the drive signals Sp1 to Spn output from the drive signal
output unit 42. The output voltages VINV1 to VINVn from the
single-phase inverters 151 to 15n are combined, and the
5 result of the combination is output as the output voltage
Vo from the power conversion unit 10.
[0043] Here, the output voltages VINV1 to VINVn from the
single-phase inverters 151 to 15n will be described in
detail with reference to FIGS. 5 to 7. FIGS. 5 to 7 are
10 diagrams illustrating examples of output voltages from a
plurality of single-phase inverters according to the first
embodiment. In the examples of FIGS. 5 to 7, n=8 is
satisfied, that is, the number of single-phase inverters 15
is eight, and the drive signals Sp1 to Sp8 are sequentially
15 input in a one-to-one correspondence to the single-phase
inverters 151 to 158 in order of Sp1 to Sp8.
[0044] Specifically, the drive signal Sp1 is input to
the single-phase inverter 151, the drive signal Sp2 is
input to the single-phase inverter 152, the drive signal
20 Sp3 is input to the single-phase inverter 153, and the
drive signal Sp4 is input to the single-phase inverter 154.
Similarly, the drive signal Sp5 is input to the singlephase
inverter 155, the drive signal Sp6 is input to the
single-phase inverter 156, the drive signal Sp7 is input to
25 the single-phase inverter 157, and the drive signal Sp8 is
input to the single-phase inverter 158.
[0045] In FIGS. 5 to 7, “1” means the above-mentioned
“+Va” which is the voltage value of a positive rectangular
wave voltage output from the single-phase inverter 15, and
30 “−1” means the above-mentioned “−Va” which is the voltage
value of a negative rectangular wave voltage output from
the single-phase inverter 15. Also, “2” to “7” mean
multiples of “+Va”, and “−2” to “−7” mean multiples of
16
“−Va”. In FIGS. 5 to 7, the vertical axis represents the
instantaneous value of the output voltage Vo, and the
horizontal axis represents the phase of the output voltage
Vo. The interval between vertical dashed lines is 18°.
5 Hereinafter, the phase of the output voltage Vo is referred
to as the output voltage phase θo.
[0046] As illustrated in FIG. 5, the output voltages
VINV1 to VINV8 are sequentially out of phase by the first
phase difference φ1. Specifically, the output voltages
10 VINV1 to VINVn8 become positive rectangular wave voltages at
timings sequentially out of phase by the first phase
difference φ1, and become negative rectangular wave
voltages at timings sequentially out of phase by the first
phase difference φ1. In the example illustrated in FIG. 5,
15 φ1=18° is satisfied.
[0047] For example, the positive rectangular wave
voltage at the output voltage VINV2 is out of phase with the
positive rectangular wave voltage at the output voltage
VINV1 by the first phase difference φ1. The positive
20 rectangular wave voltage at the output voltage VINV3 is out
of phase with the positive rectangular wave voltage at the
output voltage VINV2 by the first phase difference φ1.
Similarly, the negative rectangular wave voltage at the
output voltage VINV2 is out of phase with the negative
25 rectangular wave voltage at the output voltage VINV1 by the
first phase difference φ1. The negative rectangular wave
voltage at the output voltage VINV3 is out of phase with the
negative rectangular wave voltage at the output voltage
VINV2 by the first phase difference φ1.
30 [0048] The single-phase inverter 15 also outputs, on the
basis of the drive signal Sp, a negative rectangular wave
voltage shifted by the second phase difference φ2 from the
end of the output of the positive rectangular wave voltage.
17
In the example illustrated in FIG. 5, φ2=54° is satisfied.
For the output voltage VINV1 from the single-phase inverter
151, the time period of 0°≤θo<126° is a time period during
which a positive rectangular wave voltage is output, and
5 the time period of 180°≤θo<306° is a time period during
which a negative rectangular wave voltage is output.
Therefore, for the output voltage VINV1, the time period of
the negative rectangular wave voltage starts at the timing
shifted by 54°, which is the second phase difference φ2,
10 from the end of the time period of the positive rectangular
wave voltage.
[0049] Similarly, for the output voltages VINV2 to VINV8
from the single-phase inverters 152 to 158, the time period
of the negative rectangular wave voltage starts at the
15 timing shifted by the second phase difference φ2 from the
end of the time period of the positive rectangular wave
voltage. As is clear from the foregoing, the drive signal
Sp is generated such that the output voltage VINV from the
single-phase inverter 15 involves the second phase
20 difference φ2.
[0050] As described above, because the output terminals
161, 171, 162, 172,..., 16n-1, 17n-1, 16n, and 17n of the
single-phase inverters 151 to 158 are connected in series,
the output voltages VINV1 to VINV8 from the single-phase
25 inverters 151 to 158 are combined. Therefore, as
illustrated in FIG. 5, the waveform of the output voltage
Vo from the power conversion unit 10 is a composite
waveform of the output voltages VINV1 to VINV8.
[0051] For example, in the case of 0°≤θo<18°, the output
30 voltage VINV1 is +Va, the output voltages VINV2 to VINV4 are 0
V, and the output voltages VINV5 to VINV8 are −Va. Therefore,
the output voltage Vo is −3×Va. In the case of 18°≤θo<36°,
the output voltages VINV1 and VINV2 are +Va, the output
18
voltages VINV3 to VINV5 are 0 V, and the output voltages VINV6
to VINV8 are −Va. Therefore, the output voltage Vo is −Va.
In the case of 36°≤θo<54°, the output voltages VINV1 to VINV3
are +Va, the output voltages VINV4 to VINV6 are 0 V, and the
5 output voltages VINV7 and VINV8 are −Va. Therefore, the
output voltage Vo is +Va.
[0052] Thus, the output voltages VINV1 to VINV8 from the
single-phase inverters 151 to 158 are combined together and
output as the output voltage Vo from the power conversion
10 unit 10. In the example illustrated in FIG. 5, the output
voltage Vo changes stepwise in the range of 7×Va to −7×Va.
Changing the magnitude of the second phase difference φ2 to
increase or decrease the time during which the single-phase
inverter 15 outputs a rectangular wave voltage controls
15 waveform of the output voltage Vo.
[0053] The second phase difference φ2 illustrated in FIG.
6 is set larger than the second phase difference φ2
illustrated in FIG. 5. Specifically, the second phase
difference φ2 illustrated in FIG. 6 is larger than the
20 second phase difference φ2 illustrated in FIG. 5 by the
time equivalent to 36°. Therefore, in the example
illustrated in FIG. 6, the output voltage Vo changes
stepwise in the range of 6×Va to −6×Va, and has a smaller
amplitude than the output voltage Vo illustrated in FIG. 5.
25 [0054] Similarly, the second phase difference φ2
illustrated in FIG. 7 is set larger than the second phase
difference φ2 illustrated in FIG. 6. Specifically, the
second phase difference φ2 illustrated in FIG. 7 is larger
than the second phase difference φ2 illustrated in FIG. 6
30 by the time equivalent to 36°. Therefore, in the example
illustrated in FIG. 7, the output voltage Vo changes
stepwise in the range of 3×Va to −3×Va, and has a smaller
amplitude than the output voltage Vo illustrated in FIG. 6.
19
[0055] As illustrated in FIGS. 5 to 7, because the
output voltages VINV1 to VINV8 are sequentially out of phase
but have the same waveform, the single-phase inverters 151
to 158 output rectangular wave voltages for an equal length
5 of time.
[0056] Further, as described above, because the drive
signal output unit 42 of the control unit 40 determines the
combination pattern of the drive signals Sp1 to Spn with
the single-phase inverters 151 to 15n at each update period
10 Ts, the output power can be equalized among the singlephase
inverters 15. Hereinafter, the reason why the output
power can be equalized among the single-phase inverters 15
will be described.
[0057] If the combination of the drive signals Sp1 to
15 Spn with the single-phase inverters 151 to 15n in one-to-one
correspondence is fixed, two phenomena occur as follows.
Now, suppose that, as illustrated in FIG. 1, the load 3
which can be represented by a resonance circuit including L,
C, and R equivalently is connected to the series multiplex
20 inverter 1. Then, assume that the control unit 40 controls
the power conversion unit 10 by constant output current
control.
[0058] First, the first phenomenon that occurs when the
combination of the drive signals Sp1 to Spn with the
25 single-phase inverters 151 to 15n is fixed will be
described with reference to FIGS. 8 to 10.
[0059] FIGS. 8 and 9 are diagrams each illustrating an
example of the waveform of an output voltage and the
waveform of an output current from the series multiplex
30 inverter according to the first embodiment. For the sake
of simplicity, examples of the waveform of the output
voltage Vo and the waveform of the output current Io
illustrated in FIGS. 8 and 9 are based on the assumption
20
that the output voltage frequency fo of the series
multiplex inverter 1 matches the resonance frequency of the
load 3.
[0060] FIG. 8 shows the waveform of the output voltage
5 Vo and the waveform of the output current Io from the
series multiplex inverter 1 where the load 3 consumes a lot
of power. In the state illustrated in FIG. 8, the
rectangular wave voltages output from the respective
single-phase inverters 15 overlap each other because the
10 time during which the rectangular wave voltage is output
from each single-phase inverter 15 is long. Therefore, as
illustrated in FIG. 8, the output voltage Vo has a pseudo
sinusoidal waveform.
[0061] FIG. 9 shows the waveform of the output voltage
15 Vo and the waveform of the output current Io from the
series multiplex inverter 1 where the load 3 consumes
almost no power. In the state illustrated in FIG. 9, the
rectangular wave voltages output from the respective
single-phase inverters 15 do not overlap each other but are
20 independent of each other because the time during which the
rectangular wave voltage is output from each single-phase
inverter 15 is short.
[0062] FIG. 10 is a diagram illustrating an example of
the waveform of an output voltage and the waveform of an
25 output power from each single-phase inverter in the state
illustrated in FIG. 9. In FIG. 10, n=8 is satisfied, and
the waveforms of the output voltages VINV1 to VINV8 and the
waveforms of the output powers PINV1 to PINV8 from the
single-phase inverters 151 to 158 are illustrated.
30 Hereinafter, the output powers PINV1 to PINV8 may be
collectively referred to as the output power PINV.
[0063] Because the output terminals 16 and 17 of the
single-phase inverters 151 to 158 are connected in series,
21
the output current Io from the series multiplex inverter 1
and the output current from the single-phase inverters 151
to 158 are the same. Further, as described above, the
single-phase inverters 151 to 158 output rectangular wave
5 voltages for the same length of time.
[0064] However, the single-phase inverters 151 to 158
output rectangular wave voltages at different timings. The
output power PINV from each single-phase inverter 15 is
determined as the product of the instantaneous output
10 voltage and the instantaneous output current from each
single-phase inverter 15. The single-phase inverters 15
output rectangular wave voltages for the same length of
time but at different timings, and each single-phase
inverter 15 outputs a rectangular wave voltage at a fixed
15 timing. Therefore, the output powers PINV1 to PINV8 from the
single-phase inverters 151 to 15n are different from one
another.
[0065] For example, the output power PINV from the
single-phase inverter 15 that outputs a rectangular wave
20 voltage at a timing when the instantaneous value of the
output current Io is large is large. Conversely, the
output power PINV from the single-phase inverter 15 that
outputs a rectangular wave voltage at a timing when the
instantaneous value of the output current Io is small is
25 small.
[0066] Because the output powers PINV from the singlephase
inverters 15 differ from one another as discussed
above, losses in the single-phase inverters 15 also differ
from one another. In order to achieve commonality of
30 cooling design for the single-phase inverters 151 to 15n,
cooling design for the single-phase inverter 15 with the
largest loss should be applied to all the remaining singlephase
inverters 15, which leads to an increase in the size
22
and cost of the series multiplex inverter.
[0067] Next, the second phenomenon that occurs when the
combination of the drive signals Sp1 to Spn with the
single-phase inverters 151 to 15n is fixed will be
5 described with reference to FIGS. 11 to 13.
[0068] The characteristics of the load 3 connected to
the series multiplex inverter 1 change due to temperature,
humidity, aging deterioration, and the like, and a
difference may occur between the output voltage frequency
10 fo of the series multiplex inverter 1 and the resonance
frequency of the load 3. In this case, a phase shift
occurs between the output voltage Vo and the output current
Io from the series multiplex inverter 1. Hereinafter, the
phase of the output current Io may be referred to as a
15 current delay phase when the phase of the output current Io
is delayed relative to the phase of the output voltage Vo,
and the phase of the output current Io may be referred to
as a current lead phase when the phase of the output
current Io is advanced relative to the phase of the output
20 voltage Vo.
[0069] FIGS. 11 and 12 are diagrams each illustrating an
example of the waveform of an output voltage and the
waveform of an output current in the case of a current
delay phase in the series multiplex inverter according to
25 the first embodiment. FIG. 11 shows the waveform of the
output voltage Vo and the waveform of the output current Io
from the series multiplex inverter 1 where the load 3
consumes a lot of power, similarly to FIG. 8. FIG. 12
shows the waveform of the output voltage Vo and the
30 waveform of the output current Io from the series multiplex
inverter 1 where the load 3 consumes almost no power,
similarly to FIG. 9.
[0070] FIG. 13 is a diagram illustrating an example of
23
the waveform of an output voltage and the waveform of an
output power from each single-phase inverter in the state
illustrated in FIG. 12. As illustrated in FIG. 13, when
the phase of the output current Io is delayed relative to
5 the phase of the output voltage Vo from the series
multiplex inverter 1, the output voltage VINV and the output
current IINV have opposite polarities at some single-phase
inverters 15.
[0071] The single-phase inverter 15 at which the output
10 voltage VINV and the output current IINV have opposite
polarities performs regenerative operation, whereby the
capacitor 14 connected to the single-phase inverter 15 is
charged by the single-phase inverter 15, and the output
power PINV becomes negative. In the example illustrated in
15 FIG. 13, some single-phase inverters 151 and 152 are
performing regenerative operation, and the capacitors 141
and 142 connected to the single-phase inverters 151 and 152
are charged.
[0072] The charging of the capacitors 141 and 142
20 through the regenerative operation of the single-phase
inverters 151 and 152 is repeated every half output voltage
period To. Therefore, in the absence of discharging means
for discharging the capacitors 141 and 142, the voltage of
the capacitors 141 and 142 continues to increase due to
25 repeated regenerative operation. If the voltage of the
capacitors 141 and 142 exceeds the withstand voltage of the
semiconductor elements of the single-phase inverters 151
and 152 or the withstand voltage of the capacitors 141 and
142, the semiconductor elements of the single-phase
30 inverters 151 and 152 or the capacitors 141 and 142 fail due
to overvoltage.
[0073] In the presence of discharging means for
discharging the capacitors 141 and 142 charged through
24
regenerative operation, the discharging means causes a loss,
which increases the loss in the single-phase inverters 151
and 152. This leads to an increase in the size and cost of
the series multiplex inverter.
5 [0074] As discussed above, when a phase shift occurs
between the output voltage Vo and the output current Io
from the series multiplex inverter 1 due to a difference
between the output voltage frequency fo of the series
multiplex inverter 1 and the resonance frequency of the
10 load 3, some single-phase inverters 15 perform regenerative
operation to thereby charge the capacitors 14.
[0075] The example illustrated in FIG. 11 provides a
single-phase inverter 15 that performs regenerative
operation. In such a case, however, because the single15
phase inverter 15 outputs a rectangular wave voltage for a
long time, the polarity of the output current Io is
inverted and the output power PINV changes to positive.
Where the single-phase inverter 15 performs regenerative
operation but the charging time for the capacitor 14 is
20 shorter than the discharging time for the capacitor 14,
thus, the voltage of the capacitor 14 does not continue to
increase.
[0076] As described above, the first phenomenon in which
the output powers PINV from the single-phase inverters 15
25 differ from one another and the second phenomenon in which
the voltage of the capacitor 14 increases in some of the
single-phase inverters 15 occur.
[0077] In view of this, the drive signal output unit 42
changes the combination pattern of the drive signals Sp1 to
30 Spn with the single-phase inverters 151 to 15n at each
update period Ts set in advance. More specifically, the
drive signal output unit 42 outputs the drive signals Sp1
to Spn to the single-phase inverters 151 to 15n in rotation
25
that shifts, by p every update period Ts, the single-phase
inverters 15 corresponding one-to-one to the drive signals
Sp1 to Spn in the combination of the drive signals Sp1 to
Spn with the single-phase inverters 151 to 15n. Here, p is
5 a natural number relatively prime to n or one. For example,
in the case of n=3, p=1 or 2 is satisfied. In the case of
n=8, p=1, 3, 5, or 7 is satisfied. Note that p may be
limited to a natural number excluding one, that is, a
natural number relatively prime to n.
10 [0078] Here, the timings at which the single-phase
inverters 15 output rectangular wave voltages in accordance
with the drive signals Sp1 to Spn are respectively referred
to as the output timings T1 to Tn. For example, the output
timing at which the single-phase inverter 15 outputs the
15 rectangular wave voltage in accordance with the drive
signal Sp1 is denoted by “T1”, and the output timing at
which the single-phase inverter 15 outputs the rectangular
wave voltage in accordance with the drive signal Sp2 is
denoted by “T2”. Similarly, the output timings at which
20 the single-phase inverters 15 output the rectangular wave
voltages in accordance with the drive signals Sp3 to Spn
are denoted by “T3” to “Tn”.
[0079] First, a case where the phase of the output
current Io from the series multiplex inverter 1 is delayed
25 relative to the phase of the output voltage Vo will be
described. FIG. 14 is a diagram illustrating an example of
the relationship between output voltage, output current,
and output timings in the case of a current delay phase in
the series multiplex inverter according to the first
30 embodiment. FIG. 15 is a diagram illustrating an example
of the relationship between output power, output current,
and output timings in the case of a current delay phase in
the series multiplex inverter according to the first
26
embodiment. In FIG. 14, the horizontal axis represents
time, and the vertical axis represents current values and
voltage values. In FIG. 15, the horizontal axis represents
time, and the vertical axis represents current values and
5 power values.
[0080] FIGS. 14 and 15, which provide the examples in
which n=8 is satisfied, illustrate the waveforms of the
output voltage Vo and the output power Po and the waveform
of the output current Io from the series multiplex inverter
10 1 in the case where the load 3 consumes almost no power are
illustrated, as in FIG. 9. FIG. 14 shows the relationship
between the output voltage Vo and the output timings T1 to
T8, and FIG. 15 shows the relationship between the output
power Po and the output timings T1 to T8.
15 [0081] If the combination of the drive signals Sp1 to
Sp8 and the single-phase inverters 151 to 158 is fixed, each
single-phase inverter 15 outputs a rectangular wave voltage
every half output voltage period To at the same timing. In
this case, as described above, the single-phase inverters
20 151 and 152 repeatedly perform regenerative operation, and
continue to charge the capacitors 141 and 142. Further,
the single-phase inverter 156 continues to output a larger
output power PINV6 than the other single-phase inverters 15,
and thus continues to generate a larger power loss than the
25 other single-phase inverters 15.
[0082] To avoid this, the drive signal output unit 42
outputs the drive signals Sp1 to Spn to the single-phase
inverters 151 to 15n in rotation that shifts, by p every
update period Ts, each of the single-phase inverters 15
30 corresponding one-to-one to the drive signals Sp1 to Spn in
the combination of the drive signals Sp1 to Spn with
different single-phase inverters 151 to 15n. The rotation
that shifts, by p, the single-phase inverters 15
27
corresponding one-to-one to the drive signals Sp1 to Spn in
the combination of the drive signals Sp1 to Spn with
different single-phase inverters 151 to 15n enables the
timing at which a rectangular wave voltage is output from
5 each single-phase inverter 15 to be switched in rotation
among the output timings T1 to Tn. Therefore, repeated
regenerative operation and continuous output of large
output power PINV can be prevented.
[0083] In particular, the rotation that shifts, by p,
10 where p is a natural number relatively prime to n or one,
the single-phase inverters 15 corresponding one-to-one to
the drive signals Sp1 to Spn enables the timing at which a
rectangular wave voltage is output from each single-phase
inverter 15 to be switched in n-period rotation among the
15 output timings T1 to Tn. It therefore become possible to
appropriately equalize the output power PINV among the
single-phase inverters 15 and prevent the capacitor 14 from
being overcharged due to regenerative operation.
[0084] Here, the rotation that shifts the single-phase
20 inverters 15 corresponding one-to-one to the drive signals
Sp1 to Spn in the combination of the drive signals Sp1 to
Spn with different single-phase inverters 151 to 15n will be
described.
[0085] For convenience, the single-phase inverters 151
25 to 15n are referred to as single-phase inverters in the
first stage to n-th stage. In this case, rotation of the
single-phase inverters 15 with respect to the drive signals
Sp is rotation that shifts the single-phase inverters in
the direction from the first stage to the n-th stage, such
30 that the single-phase inverter in the n-th stage is shifted
by one stage to come to the first stage.
[0086] For example, the order of rotation is determined
in a manner that the single-phase inverter 15 to be
28
combined with the drive signal Sp1 is changed in the order
of the single-phase inverter 151 in the first stage, the
second single-phase inverter 152 in the second stage,...,
and the single-phase inverter 15n in the n-th stage, and
5 returns to the single-phase inverter 151 in the first stage
by one shift from the single-phase inverter 15n in the n-th
stage. The drive signal output unit 42 performs such a
change as to shift the single-phase inverter 15
corresponding to each drive signal Sp by p in the order of
10 rotation every update period Ts, instead of shifting the
single-phase inverter 15 corresponding to each drive signal
Sp by one in the order of rotation every update period Ts.
[0087] FIG. 16 is a diagram illustrating an example of
the output timing at which each single-phase inverter
15 outputs a rectangular wave voltage on an update-period-byupdate-
period basis. FIG. 16 illustrates an example in
which n=8 and p=5 are satisfied. As illustrated in FIG. 16,
the single-phase inverter 151 outputs rectangular wave
voltages at the output timing T1 in the first period, at
20 the output timing T6 in the second period, at the output
timing T3 in the third period, and at the output timing T8
in the fourth period.
[0088] Further, the single-phase inverter 151 outputs
rectangular wave voltages at the output timing T5 in the
25 fifth period, at the output timing T2 in the sixth period,
at the output timing T7 in the seventh period, and at the
output timing T4 in the eighth period. Then, the singlephase
inverter 151 outputs a rectangular wave voltage at
the output timing T1 in the ninth period, which is the same
30 as in the first period.
[0089] As discussed above, the single-phase inverter 151
repeats the process of outputting rectangular wave voltages
in order of the output timings T1, T6, T3, T8, T5, T2, T7,
29
and T4 every eight periods. Similarly to the single-phase
inverter 151, the single-phase inverters 152 to 158 also
switch the outputs of rectangular wave voltages in rotation
that shifts by five among the output timings T1 and T8.
5 Therefore, the amount of power generation can be equalized
among the single-phase inverters 15 in the time of eight
output voltage periods To, and the power loss can be
appropriately equalized among the single-phase inverters 15.
[0090] The single-phase inverter 151 can output a
10 rectangular wave voltage at the output timing T6 where the
output power PINV is large in the period next to the period
in which the single-phase inverter 151 outputs a
rectangular wave voltage at the output timing T1 where the
output power PINV is small. Therefore, the capacitor 14
15 charged through regenerative operation can be quickly
discharged, and voltage fluctuations in the capacitor 14
can be minimized. Similarly to the single-phase inverter
151, the single-phase inverters 152 to 158 can also moderate
voltage fluctuations in the capacitors 14.
20 [0091] Although the above description is made as to an
example in which n=8 and p=5 are satisfied, effects similar
to those described above can be obtained in examples other
than the example in which n=8 and p=5 are satisfied.
Specifically, in the case of n=4×k, effects similar to
25 those described above can be obtained using p=n/2+1. Here,
k is a natural number. For example, in the case of n=4,
p=3 is satisfied, and in the case of n=12, p=7 is satisfied.
[0092] Alternatively, in the case of n=2×k+1, effects
similar to those described above can be obtained using
30 p=(n+1)/2. For example, in the case of n=5, p=3 is
satisfied. In the case of n=7, p=4 is satisfied, and in
the case of n=9, p=5 is satisfied.
[0093] Alternatively, in the case of n=4×k+2, effects
30
similar to those described above can be obtained using
p=n/2+2. For example, in the case of n=6, p=5 is satisfied.
In the case of n=10, p=7 is satisfied, and in the case of
n=14, p=9 is satisfied.
5 [0094] The rotation that shifts the inverters by p,
where p is a natural number relatively prime to n or one,
enables the timing at which a rectangular wave voltage is
output from each single-phase inverter 15 to be switched in
n-period rotation among the output timings T1 to Tn.
10 Therefore, in the case of n=4×k, p may be a natural number
other than n/2+1. In the case of n=2×k+1, p may be a
natural number other than (n+1)/2, and in the case of
n=4×k+2, p may be a natural number other than n/2+2.
[0095] Next, a case where the output current Io from the
15 series multiplex inverter 1 is advanced relative to the
output voltage Vo will be described. FIG. 17 is a diagram
illustrating an example of the relationship between output
voltage, output current, and output timings for the case of
a lead phase in the series multiplex inverter according to
20 the first embodiment. FIG. 18 is a diagram illustrating an
example of the relationship between output power, output
current, and output timings for the case of a lead phase in
the series multiplex inverter according to the first
embodiment. In FIG. 17, the horizontal axis represents
25 time, and the vertical axis represents current values and
voltage values. In FIG. 18, the horizontal axis represents
time, and the vertical axis represents current values and
power values.
[0096] FIGS. 17 and 18, which provide examples in which
30 n=8 is satisfied, illustrate the waveform of the output
voltage Vo or the output power Po and the waveform of the
output current Io from the series multiplex inverter 1 in
the case where the load 3 consumes almost no power, as in
31
FIGS. 14 and 15.
[0097] FIG. 19 is a diagram illustrating another example
of the output timing at which each single-phase inverter
outputs a rectangular wave voltage on an update-period-by5
update-period basis. In FIG. 19, n=8 and p=3 are satisfied.
As illustrated in FIG. 19, the single-phase inverter 151
repeats the process of outputting rectangular wave voltages
in order of the output timings T1, T4, T7, T2, T5, T8, T3,
and T6 every eight periods. Similarly to the single-phase
10 inverter 151, the single-phase inverters 152 to 158 also
switch the output of rectangular wave voltages in rotation
that shifts by three among the output timings T1 and T8.
[0098] The single-phase inverter 151 can output a
rectangular wave voltage at the output timing T3 where the
15 output power PINV is large in the period next to the period
in which the single-phase inverter 151 outputs a
rectangular wave voltage at the output timing T8 where the
output power PINV is small. Therefore, the capacitor 14
charged through regenerative operation can be quickly
20 discharged, and voltage fluctuations in the capacitor 14
can be minimized. Similarly to the single-phase inverter
151, the single-phase inverters 152 to 158 can also moderate
voltage fluctuations in the capacitors 14.
[0099] Therefore, the amount of power generation can be
25 equalized among the single-phase inverters 15 in the time
of eight update periods Ts, and the power loss can be
appropriately equalized among the single-phase inverters 15.
[0100] Although the above description is made as to an
example in which n=8 and p=3 are satisfied, effects similar
30 to those described above can be obtained in examples other
than the example in which n=8 and p=3 are satisfied.
Specifically, in the case of n=4×k, effects similar to
those described above can be obtained using p=n/2−1. For
32
example, in the case of n=4, p=1 is satisfied, and in the
case of n=12, p=5 is satisfied.
[0101] Alternatively, in the case of n=2×k+1, effects
similar to those described above can be obtained using
5 p=(n−1)/2. For example, in the case of n=3, p=1 is
satisfied. In the case of n=5, p=2 is satisfied, and in
the case of n=7, p=3 is satisfied.
[0102] Alternatively, in the case of n=4×k+2, effects
similar to those described above can be obtained using
10 p=n/2−2. For example, in the case of n=6, p=1 is satisfied.
In the case of n=10, p=3 is satisfied, and in the case of
n=14, p=5 is satisfied.
[0103] In the case of a current lead phase as well, the
rotation that shifts the inverters by p, where p is a
15 natural number relatively prime to n or one, enables the
timing at which a rectangular wave voltage is output from
each single-phase inverter 15 to be switched in n-period
rotation among the output timings T1 to Tn. Therefore, in
the case of n=4×k, p may be a natural number other than
20 n/2−1. In the case of n=2×k+1, p may be a natural number
other than (n−1)/2, and in the case of n=4×k−2, p may be a
natural number other than n/2−2.
[0104] An exemplary case of a current delay phase and an
exemplary case of a current lead phase have been mainly
25 described so far. However, even when the phase of the
output current Io and the phase of the output voltage Vo
are substantially the same, the power loss can be
appropriately equalized among the single-phase inverters 15.
[0105] Reference is made back to FIG. 1 to continue the
30 explanation of the control unit 40 of the series multiplex
inverter 1. An operation receiving unit 43 of the control
unit 40 receives input of the above-described information
on p through operation performed on the operation unit 50,
33
and inputs the information on p received by the operation
receiving unit 43 to the drive signal output unit 42. On
the basis of p input from the operation receiving unit 43,
the drive signal output unit 42 changes the combination
5 pattern of the n drive signals Sp1 to Spn with the singlephase
inverters 151 to 15n at each update period Ts set in
advance. Note that the operation unit 50 is, for example,
a DIP switch, but may be a detachable operation device.
[0106] The operation unit 50 is configured to receive an
10 operation of inputting the value of p itself. In this case,
the operation unit 50 can be, for example, a DIP switch
through which a natural number can be selected. Further,
the operation unit 50 can receive an operation of inputting
indirect information for setting p, instead of the value of
15 p itself. For example, the operation unit 50 can
selectively set first information indicating that the phase
of the output current Io is delayed relative to the phase
of the output voltage Vo and second information indicating
that the phase of the output current Io is advanced
20 relative to the phase of the output voltage Vo. In a case
where the operation unit 50 is a DIP switch including one
switch, turning on the DIP switch sets the first
information, and turning off the DIP switch sets the second
information.
25 [0107] The operation receiving unit 43 determines p from
the state of the DIP switch. For example, in the case of
n=8, p=n/2+1=5 is set when the DIP switch is on, and
p=n/2−1=3 is set when the DIP switch is off. In the case
of n=9, p=(n+1)/2=5 is set when the DIP switch is on, and
30 p=(n−1)/2=4 is set when the DIP switch is off.
[0108] As described above, the series multiplex inverter
1 includes the operation unit 50 and the operation
receiving unit 43. Therefore, even in a case where the
34
characteristics of the load 3 change depending on the
season or the like and the phase shift of the output
voltage Vo with respect to the output current Io is
switched between a delay and a lead, the power loss can be
5 appropriately equalized among the single-phase inverters 15.
[0109] In a case where the time period of a current
delay phase and the time period of a current lead phase are
determined in advance, p may be set to be switched in each
time period. For example, a combination of a time period
10 and p can be set by the operation unit 50 on a timeperiod-
by-time-period basis. Among the combinations of
time periods and p set in the operation unit 50, the
information on p combined with the time period including
the present time is input by the operation receiving unit
15 43 to the drive signal output unit 42.
[0110] Instead of setting a combination of a time period
and p on a time-period-by-time-period basis, the operation
unit 50 can set a combination of a temperature range and p
on a temperature-range-by-temperature-range basis. In this
20 case, among the combinations of temperature ranges and p
set in the operation unit 50, the information of p combined
with the temperature range including the present
temperature is input by the operation receiving unit 43 to
the drive signal output unit 42.
25 [0111] Next, the operation of the control unit 40 will
be described using a flowchart. FIG. 20 is a flowchart
illustrating an exemplary process that is performed by the
control unit according to the fist embodiment. As
illustrated in FIG. 20, the control unit 40 generates the n
30 drive signals Sp sequentially out of phase by the first
phase difference φ1 (step S11).
[0112] Next, the control unit 40 determines whether the
update timing has come (step S12). The update timing
35
occurs, for example, every update period Ts. In response
to determining that the update timing has come (step S12:
Yes), the control unit 40 shifts the combination of the n
drive signals Sp with the n single-phase inverters 15 by p
5 and outputs the n drive signals Sp to the n single-phase
inverters 15 (step S13).
[0113] In response to determining that the update timing
has not come (step S12: No), the control unit 40 outputs
the n drive signals Sp to the n single-phase inverters 15
10 using the same combination of the n drive signals Sp with
the n single-phase inverters 15 as last time (step S14).
The control unit 40 repeatedly performs the process
illustrated in FIG. 20 every half output voltage period To.
[0114] Here, a hardware configuration of the control
15 unit 40 of the series multiplex inverter 1 according to the
first embodiment will be described. FIG. 21 is a diagram
illustrating an exemplary hardware configuration of the
control unit of the series multiplex inverter according to
the first embodiment. As illustrated in FIG. 21, the
20 control unit 40 of the series multiplex inverter 1 includes
a processor 101, a memory 102, and an input/output circuit
103. The processor 101, the memory 102, and the
input/output circuit 103 can exchange data with one another
via a bus 104. The memory 102 includes a recording medium
25 on which a computer-readable program is recorded.
[0115] The processor 101 reads and executes a program
stored in the memory 102 to execute the functions of the
drive signal generation unit 41, the drive signal output
unit 42, and the operation receiving unit 43 described
30 above. The processor 101 is an example of a processing
circuit, and includes, for example, one or more of a
central processing unit (CPU), a digital signal processer
(DSP), and a system large scale integration (LSI).
36
Examples of the memory 102 include a non-volatile or
volatile semiconductor memory, a magnetic disk, a flexible
disk, an optical disc, a compact disc, a mini disc, a
digital versatile disc (DVD), and the like. Examples of
5 the non-volatile or volatile semiconductor memory include a
random access memory (RAM), a read only memory (ROM), a
flash memory, an erasable programmable read only memory
(EPROM), an electrically erasable programmable read-only
memory (EEPROM, registered trademark), and the like.
10 [0116] Note that the control unit 40 described above may
be implemented by dedicated hardware that implements the
same functions as the processor 101 and the memory 102
illustrated in FIG. 21. Dedicated hardware is, for example,
a single circuit, a composite circuit, a programmed
15 processor, a parallel programmed processor, an application
specific integrated circuit (ASIC), a field programmable
gate array (FPGA), or a processing circuit including a
combination thereof. A part of the control unit 40 may be
implemented by dedicated hardware, and the rest of the
20 control unit 40 may be implemented by the processor 101 and
the memory 102 illustrated in FIG. 21.
[0117] As described above, the series multiplex inverter
1 according to the first embodiment includes the power
conversion unit 10, the drive signal generation unit 41,
25 and the drive signal output unit 42. The power conversion
unit 10 includes the n single-phase inverters 15, where n
is an integer of three or more, and the output terminals 16
and 17 of the n single-phase inverters 15 are connected in
series. The drive signal generation unit 41 generates the
30 n drive signals Sp that cause different single-phase
inverters of the n single-phase inverters 15 to output n
rectangular wave voltages sequentially out of phase by the
first phase difference φ1 set in advance. The drive signal
37
output unit 42 outputs the n drive signals Sp to the n
single-phase inverters 15 in rotation that shifts, by p
every update period Ts, the single-phase inverters 15
corresponding one-to-one to the n drive signals Sp in a
5 combination of the n drive signals Sp with the n singlephase
inverters 15, where m is a natural number, p is a
natural number relatively prime to n or one, and one update
period Ts is the m-fold time of half the output voltage
period To of the power conversion unit 10. Consequently,
10 the timing at which a rectangular wave voltage is output
from each single-phase inverter 15 can be switched in
rotation among the output timings T1 to Tn in the time of n
update periods Ts. Therefore, the amount of power
generation can be equalized among the single-phase
15 inverters 15 in the time of n update periods Ts, and the
power loss can be appropriately equalized among the singlephase
inverters 15.
[0118] The series multiplex inverter 1 includes the
operation receiving unit 43 that receives the operation of
20 setting p. The drive signal output unit 42 outputs the n
drive signals Sp to the n single-phase inverters 15 on the
basis of p received by the operation receiving unit 43.
Thus, even when the load 3 having different characteristics
is connected to the series multiplex inverter 1, the power
25 loss can be appropriately equalized among the single-phase
inverters 15 through operation performed on the operation
receiving unit 43.
[0119] When n is 2×k+1, p is at least one of (n+1)/2 and
(n−1)/2. Consequently, in the case of n=2×k+1, even when
30 the output voltage Vo is out of phase with the output
current Io, the power loss can be appropriately equalized
among the single-phase inverters 15.
[0120] When n is 4×k, p is at least one of n/2+1 and
38
n/2−1. Consequently, in the case of 4×k, even when the
output voltage Vo is out of phase with the output current
Io, the power loss can be appropriately equalized among the
single-phase inverters 15.
5 [0121] When n is 4×k+2, p is at least one of n/2+2 and
n/2−2. Consequently, in the case of 4×k+2, even when the
output voltage Vo is out of phase with the output current
Io, the power loss can be appropriately equalized among the
single-phase inverters 15.
10 [0122] Second Embodiment
The second embodiment is different from the first
embodiment in that a phase shift of the output voltage Vo
with respect to the output current Io can be detected and p
can be automatically switched. In the following
15 description, components having the same functions as those
in the first embodiment are denoted by the same reference
signs, and descriptions thereof are omitted. The
difference from the series multiplex inverter 1 according
to the first embodiment is mainly described.
20 [0123] FIG. 22 is a diagram illustrating an exemplary
configuration of a series multiplex inverter according to
the second embodiment. As illustrated in FIG. 22, the
series multiplex inverter 1A according to the second
embodiment includes the power conversion unit 10, the
25 voltage detection unit 20, the current detection unit 30,
and a control unit 40A.
[0124] A control unit 40A includes the drive signal
generation unit 41, a drive signal output unit 42A, and a
determination unit 44. The determination unit 44
30 determines whether the phase of the output current Io is
advanced or delayed relative to the phase of the output
voltage Vo on the basis of the output voltage Vo detected
by the voltage detection unit 20 and the output current Io
39
detected by the current detection unit 30.
[0125] The determination unit 44 acquires the detected
voltage value Vdet repeatedly output from the voltage
detection unit 20 and the detected current value Idet
5 repeatedly output from the current detection unit 30. The
determination unit 44 performs a discrete Fourier transform
on the detected voltage value Vdet and the detected current
value Idet, using a sampling period that is an integral
multiple of the output voltage frequency fo. Through the
10 discrete Fourier transform, the determination unit 44
extracts the primary component Io1 of the output current Io
and the primary component Vo1 of the output voltage Vo.
Note that, instead of the discrete Fourier transform, the
determination unit 44 can use a method and algorithm for
15 extracting only the primary component from a signal having
a plurality of high-order frequency components, thereby
extracting the primary component Io1 of the output current
Io and the primary component Vo1 of the output voltage Vo.
[0126] In a case where the Fourier transform is
20 performed by the determination unit 44, the primary
component Vo1 of the output voltage Vo and the primary
component Io1 of the output current Io are expressed in
complex notation by Formulas (1) and (2) below. In
Formulas (1) and (2) below, “Vo1Re” indicates the real part
25 of Vo1, “Io1Re” indicates the real part of Io1, “Vo1Im”
indicates the imaginary part of Vo1, “Io1Im” indicates the
imaginary part of Io1, and “j” indicates an imaginary unit.
Vo1=Vo1Re+j×Vo1Im... (1)
Io1=Io1Re+j×Io1Im... (2)
30 [0127] The determination unit 44 can compute the phase θ
through calculations of Formulas (3) and (4) below to
thereby determine whether the phase of the output current
Io is advanced or delayed relative to the phase of the
40
output voltage Vo. The phase θ indicates a phase shift of
the output current Io with respect to the output voltage Vo.
Z=Vo/Io... (3)
θ=arctan(Im(Z)/Re(Z))... (4)
5 [0128] Note that the determination unit 44 can obtain
the waveform of the output current Io from the detected
current value Idet and the waveform of the output voltage
Vo from the detected voltage value Vdet, and compare the
waveform of the output current Io with the waveform of the
10 output voltage Vo. The determination unit 44 can determine,
from a result of the comparison between the waveform of the
output current Io and the waveform of the output voltage Vo,
whether the phase of the output current Io is advanced or
delayed relative to the phase of the output voltage Vo.
15 [0129] The drive signal output unit 42A outputs the
drive signals Sp1 to Spn to the single-phase inverters 151
to 15n every update period Ts on the basis of p determined
from the phase shift determination result provided by the
determination unit 44.
20 [0130] For example, in the case of n=4×k, the drive
signal output unit 42A designates either n/2+1 or n/2−1 as
p on the basis of the determination result provided by the
determination unit 44. Specifically, in response to the
determination unit 44 determining that the phase of the
25 output current Io is delayed relative to the phase of the
output voltage Vo, the drive signal output unit 42A
designates n/2+1 as p. In response to the determination
unit 44 determining that the phase of the output current Io
is advanced relative to the phase of the output voltage Vo,
30 the drive signal output unit 42A designates n/2−1 as p.
[0131] In the case of n=2×k+1, the drive signal output
unit 42A designates either (n+1)/2 or (n−1)/2 as p on the
basis of the determination result provided by the
41
determination unit 44. Specifically, in response to the
determination unit 44 determining that the phase of the
output current Io is delayed relative to the phase of the
output voltage Vo, the drive signal output unit 42A
5 designates (n+1)/2 as p. In response to the determination
unit 44 determining that the phase of the output current Io
is advanced relative to the phase of the output voltage Vo,
the drive signal output unit 42A designates (n−1)/2 as p.
[0132] In the case of n=4×k+2, the drive signal output
10 unit 42A computes either p=n/2+2 or p=n/2−2 to determine p,
on the basis of the determination result provided by the
determination unit 44. Specifically, in response to the
determination unit 44 determining that the phase of the
output current Io is delayed relative to the phase of the
15 output voltage Vo, the drive signal output unit 42A
computes p=n/2+2 to determine p. In response to the
determination unit 44 determining that the phase of the
output current Io is advanced relative to the phase of the
output voltage Vo, the drive signal output unit 42A
20 computes p=n/2−2 to determine p.
[0133] The drive signal output unit 42A switches the
single-phase inverters 15 corresponding one-to-one to the
drive signals Sp1 to Spn in rotation that shifts each of
the single-phase inverters by p determined as described
25 above every update period Ts. Consequently, even in a case
where the state is switched between a current delay phase
and a current lead phase due to a change in the
characteristics of the load 3 or the like, it becomes
possible to appropriately equalize the output power PINV
30 among the single-phase inverters 15 and prevent the
capacitor 14 from being overcharged due to the regenerative
operation.
[0134] In the above-described examples, the
42
determination unit 44 that determines a phase shift of the
output current Io with respect to the output voltage Vo is
provided in the control unit 40A. Alternatively, the
function of the determination unit 44 may be provided in an
5 external device. In this case, the external device can
notify through a wired or wireless communication the
control unit 40A of a result of determination of the phase
shift. The drive signal output unit 42A of the control
unit 40A can output the drive signals Sp1 to Spn to the
10 single-phase inverters 151 to 15n on the basis of p
determined from the phase shift determination result
provided by the external device.
[0135] Next, the process of determining p by the control
unit 40A will be described using a flowchart. FIG. 23 is a
15 flowchart illustrating an exemplary determination process
that is performed by the control unit according to the
second embodiment. As illustrated in FIG. 23, the control
unit 40A performs a current phase shift determination
process (step S21). The phase shift determination process
20 is a process of determining which of a current delay phase
and a current lead phase has occurred. A current delay
phase indicates that the phase of the output current Io is
delayed relative to the phase of the output voltage Vo, as
described above, and a current lead phase indicates that
25 the phase of the output current Io is advanced relative to
the phase of the output voltage Vo, as described above.
[0136] Next, the control unit 40A determines whether the
result of the current phase shift determination process
indicates a current delay phase (step S22). When the
30 result of the current phase shift determination process
indicates a current delay phase (step S22: Yes), the
control unit 40A designates p1 as p (step S23). When the
result of the current phase shift determination process
43
does not indicate a current delay phase (step S22: No), the
control unit 40A designates p2 as p (step S24). The
control unit 40A can perform the process illustrated in FIG.
22 every preset period.
5 [0137] Here, “p1” in step S23 is p=n/2+1 in the case of
n=4×k, p=(n+1)/2 in the case of n=2×k+1, and p=n/2+2 in the
case of n=4×k+2. In addition, “p2” in step S23 is p=n/2−1
in the case of n=4×k, p=(n−1)/2 in the case of n=2×k+1, and
p=n/2−2 in the case of n=4×k+2.
10 [0138] An exemplary hardware configuration of the
control unit 40A of the series multiplex inverter 1A
according to the second embodiment is the same as the
exemplary hardware configuration illustrated in FIG. 21.
The processor 101 can read and execute a program stored in
15 the memory 102 to execute the functions of the drive signal
generation unit 41, the drive signal output unit 42A, and
the determination unit 44.
[0139] As described above, the series multiplex inverter
1A according to the second embodiment includes the voltage
20 detection unit 20 that detects the output voltage Vo from
the power conversion unit 10, the current detection unit 30
that detects the output current Io from the power
conversion unit 10, and the determination unit 44. The
determination unit 44 determines whether the phase of the
25 output current Io is advanced or delayed relative to the
phase of the output voltage Vo on the basis of the output
voltage Vo detected by the voltage detection unit 20 and
the output current Io detected by the current detection
unit 30. In response to the determination unit 44
30 determining that the phase of the output current Io is
delayed relative to the phase of the output voltage Vo, the
drive signal output unit 42A outputs the n drive signals Sp
to the n single-phase inverters 15 in rotation that shifts,
44
by the first number, namely p1 described above, each of the
single-phase inverters 15 corresponding one-to-one to the n
drive signals Sp in a combination of the n drive signals Sp
with different single-phase inverters of the n single-phase
5 inverters 15. In response to the determination unit 44
determining that the phase of the output current Io is
advanced relative to the phase of the output voltage Vo,
the drive signal output unit 42A outputs the n drive
signals Sp to the n single-phase inverters 15 in rotation
10 that shifts, by the second number, namely p2 described
above, each of the single-phase inverters 15 corresponding
one-to-one to the n drive signals Sp in a combination of
the n drive signals Sp with different single-phase
inverters of the n single-phase inverters 15. Consequently,
15 even in a case where the state is switched between a
current delay phase and a current lead phase due to a
change in the characteristics of the load 3 or the like, it
becomes possible to appropriately equalize the output power
PINV among the single-phase inverters 15 and prevent the
20 capacitor 14 from being overcharged due to regenerative
operation. Note that p1 and p2 may be limited to a natural
number excluding one, that is, a natural number relatively
prime to n.
[0140] Although the above-described series multiplex
25 inverters 1 and 1A include the n transformers 12, the
series multiplex inverters 1 and 1A may include one multioutput
transformer instead of the n transformers 12. In
this case, the primary side of the multi-output transformer
is connected to the single-phase AC power supply 2, and AC
30 voltage is output from the n secondary sides of the multioutput
transformer to the n rectifier circuits 13.
[0141] In the above-described examples, the single-phase
AC voltage Vac from the single-phase AC power supply 2 is
45
converted into the DC voltage Vdc. However, the power
supply is not limited to the single-phase AC power supply 2.
For example, the series multiplex inverters 1 and 1A may be
configured to convert three-phase AC voltage from a three5
phase AC power supply, in place of the single-phase AC
power supply 2, into the DC voltage Vdc. In this case, a
three-phase transformer is used as the transformer 12, and
a three-phase rectifier circuit is used as the rectifier
circuit 13, whereby three-phase AC voltage can be converted
10 into the DC voltage Vdc.
[0142] In the above-described examples, the DC voltage
Vdc is input to each single-phase inverter 15 from an
independent DC power supply including the transformer 12,
the rectifier circuit 13, and the capacitor 14.
15 Alternatively, the DC voltage Vdc may be input from one DC
power supply to the n single-phase inverters 15. In this
case, the output voltages VINV from the individual singlephase
inverters 15 are input to the primary sides of n
transformers provided on a single-phase-inverter-by-single20
phase inverter basis. The secondary sides of the n
transformers are connected in series, whereby the output
voltages VINV from the single-phase inverters 15 are
combined and output to the load 3.
[0143] The configurations described in the above25
mentioned embodiments indicate examples of the contents of
the present invention. The configurations can be combined
with another well-known technique, and some of the
configurations can be omitted or changed in a range not
departing from the gist of the present invention.
30
Reference Signs List
[0144] 1, 1A series multiplex inverter; 2 single-phase
AC power supply; 3 load; 10 power conversion unit; 111 to
46
11n power conversion block; 12, 121 to 12n transformer; 13,
131 to 13n rectifier circuit; 14, 141 to 14n capacitor; 15,
151 to 15n single-phase inverter; 16, 161 to 16n, 17, 171
to 17n output terminal; 18 gate driver; 20 voltage
5 detection unit; 30 current detection unit; 40, 40A
control unit; 41 drive signal generation unit; 42, 42A
drive signal output unit; 43 operation receiving unit; 44
determination unit; 50 operation unit; 60 effective value
calculation unit; 61 current command output unit; 62
10 subtractor; 63 current control unit; 64 carrier wave
output unit; 65 comparator; 66 signal generation unit.
47
We Claim:
1. A series multiplex inverter comprising:
5 a power conversion unit including n single-phase
inverters, where n is an integer of three or more, the n
single-phase inverters having output terminals connected in
series;
a drive signal generation unit to generate n drive
10 signals that cause different single-phase inverters of the
n single-phase inverters to output n rectangular wave
voltages sequentially out of phase; and
a drive signal output unit to output the n drive
signals to the n single-phase inverters in rotation that
15 shifts, by p every m-fold time of half an output voltage
period of the power conversion unit, the single-phase
inverters corresponding one-to-one to the n drive signals
in a combination of the n drive signals with different
single-phase inverters of the n single-phase inverters,
20 where m is a natural number and p is a natural number
relatively prime to n or one.
2. The series multiplex inverter according to claim 1,
comprising
25 an operation receiving unit to receive an operation of
setting the p, wherein
the drive signal output unit outputs the n drive
signals to the n single-phase inverters on a basis of the p
received by the operation receiving unit.
30
3. The series multiplex inverter according to claim 1,
wherein
the p includes a first number and a second number that
48
are different from each other,
the series multiplex inverter includes:
a voltage detection unit to detect an output voltage
from the power conversion unit;
5 a current detection unit to detect an output current
from the power conversion unit; and
a determination unit to determine whether a phase of
the output current is advanced or delayed relative to a
phase of the output voltage on the basis of the output
10 voltage detected by the voltage detection unit and the
output current detected by the current detection unit,
in response to the determination unit determining that
the phase of the output current is delayed relative to the
phase of the output voltage, the drive signal output unit
15 outputs the n drive signals to the n single-phase inverters
in rotation that shifts, by the first number, the singlephase
inverters corresponding one-to-one to the n drive
signals in the combination, and
in response to the determination unit determining that
20 the phase of the output current is advanced relative to the
phase of the output voltage, the drive signal output unit
outputs the n drive signals to the n single-phase inverters
in rotation that shifts, by the second number, the singlephase
inverters corresponding one-to-one to the n drive
25 signals in the combination.
4. The series multiplex inverter according to claim 2 or
3, wherein
the n is 2×k+1, where k is a natural number, and
30 the p is at least one of n/2+1/2 and n/2−1/2.
5. The series multiplex inverter according to claim 2 or
3, wherein
49
the n is 4×k, where k is a natural number, and
the p is at least one of n/2+1 and n/2−1.
6. The series multiplex inverter according to claim 2 or
5 3, wherein
the n is 4×k+2, where k is a natural number, and
the p is at least one of n/2+2 and n/2−2.