l.A Precision Timing Protocol (PTP) based Small Factor Pluggable (SFP) module (106), wherein said PTP based SFP module (106) is configured to function without an internal oscillator by referring to an interface recovered clock, said PTP based SFP module (106) having a PTP master/slave/boundary clock integrated therein, said PTP based SFP module (106) further configured to cooperate with the physical interface transceivers (PHYs) of network elements (104, 105 and 107), and receive the data transmitted from the PHYs, said SFP module (106) further configured to seamlessly recover reference clock(s) from the received data.
2. The network element as claimed in claim 1, wherein said network element comprises a centralized Digital Phase Locked Loop (DPLL) (406) configured to be operated in at least a free run mode and a network locked mode, wherein said centralized DPLL (406) is configured to provide predetermined reference clock(s) to a plurality of physical interface transceivers (PHYs).
3. The PTP based SFP module (106) as claimed in claim 1, wherein said PTP based SFP module (106) is configured to be controlled by an I2C interface
(202).
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4. The PTP based SFP module (106) as claimed in claim 1, wherein said PTP based SFP module (106) is configured to be connected to a switch fabric of the network element via an SFP SERDES interface (201), the PTP based SFP module (106) further configured to draw electric power via a SFP port located on a network connector.
5. The PTP based SFP module (106) as claimed in claim 1, wherein said PTP based SFP module (106) is configured to enable the network element to function without an internal oscillator, subsequent to the electronic coupling of the PTP based SFP module (106) with the network element (104, 105 and 107).
6. The PTP based SFP module (106) as claimed in claim 1 or 2, wherein quality of an output reference clock of the centralized DPLL (406) reflects quality of an oscillator coupled to the centralized DPLL (406), in an event the centralized DPLL (406) is implemented in the free run mode.
7. The PTP based SFP module (106) as claimed in claim 1 or 2, wherein quality of an output reference clock of the centralized DPLL (406) reflects quality of a network recovered clock coupled to the DPLL (406), in an event the centralized DPLL (406) is implemented in the network locked mode.
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8. A method for enabling a PTP based SFP module to function without an
internal oscillator, said method comprising the following steps:
configuring said PTP based SFP module having a PTP master/slave/Boundary Clock module integrated therein (501);
configuring a centralized Digital Phase Locked Loop (DPLL) to be operated in a mode selected from the group consisting of free run mode and network locked mode (502);
enabling the centralized DPLL to provide reference clock(s) to a plurality of interface transceivers (PHYs) of the network element (503);
receiving the data transmitted by the PHYs using the PTP based SFP module (504); and
recovering, at the SFP module, the reference clock(s) from the data transmitted by the PHYs, thereby eliminating the need for the internal oscillator (505).
9. The method as claimed in claim 8, wherein the step of configuring a
centralized Digital Phase Locked Loop (DPLL) to be operated in a mode
selected from the group consisting of free run mode and network locked mode,
further includes the step of implementing the DPLL in the free run mode, and
enabling the DPLL to depict the quality of the output oscillator clock and the
quality of the oscillator.
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10. The method as claimed in claim 8, wherein the step of configuring a centralized Digital Phase Locked Loop (DPLL) to be operated in a mode selected from the group consisting of free run mode and network locked mode, further includes the step of implementing the DPLL in the network locked mode, and enabling the DPLL to depict the quality of the network recovered clock coupled to the DPLL.