CLIAMS:1. A method for sharing a single root I/O virtualization (SR-IOV) device (106) amongst a plurality of roots (104), the method comprising:
identifying a physical function (PF) and a plurality of virtual functions (VFs) associated with the SR-IOV device (106);
generating at least one set of VFs from amongst the plurality of identified VFs, wherein each set of VFs include one or more VFs;
generating a pseudo PF (PPF) for each of the at least one set of VFs, wherein the PPF is based on the PF and virtualizes the SR-IOV device (106), and wherein a set of VFs and a corresponding PPF forms a projected SR-IOV device (106); and
associating the projected SR-IOV device (106) with a root (104) from amongst the plurality of roots (104) to allow sharing of the SR-IOV device (106).

2. The method as claimed in claim 1, wherein the method further comprises generating routing information and configuration registers (RICR) (206) for each of the projected SR-IOV device (106), wherein the associating is based on the RICR (206).

3. The method as claimed in claim 2, wherein the RICR (206) comprises at least one of configuration registers (206-1), base address registers (BARs) (206-4), mapping tables (206-2), and assignment tables (206-3) for each of the projected SR-IOV device (106).

4. The method as claimed in claim 1, wherein the identifying is based on a connect event, and wherein the connect event is one of a hotplug insertion and a reset event.

5. The method as claimed in claim 2, wherein the method further comprises:
receiving a PCIe transaction layer packet (TLP) from at least one root (104);
identifying at least one of the configuration registers (206-1), base address registers (BARs) (206-4), mapping tables (206-2), and assignment tables (206-3) associated with the projected SR-IOV device (106) associated to the at least one root (104);
modifying the PCIe TLP based on the identified configuration registers (206-1), base address registers (BARs) (206-4), mapping tables (206-2), and assignment tables (206-3) to generate a modified PCIe TLP; and
providing the modified PCIe TLP to the SR-IOV device (106).

6. The method as claimed in claim 5, wherein the modifying is based on address of PCIe TLPs, and wherein the PCIe TLP is at least one of a memory and an I/O request.

7. The method as claimed in claim 5, wherein the modifying is based on ID of the PCIe TLP, and wherein the PCIe TLP is at least one of configuration request, completion message, and an ID routed message.

8. The method as claimed in claim 5, wherein the method comprises:
updating the configuration registers (206-1), the base address registers (BARs) (206-4), the mapping tables (206-2), and the assignment tables (206-3), wherein the PCIe TLP is a VF configuration PCIe TLP; and
generating a new VF configuration PCIe TLP for the SR-IOV device (106) based on the received VF configuration PCIe TLP.

9. The method as claimed in claim 1 further comprising:
receiving a PCIe TLP from the SR-IOV device (106);
intercepting the PCIe TLP from the SR-IOV device (106) to determine nature of the PCIe TLP, wherein the nature of the PCIe TLP is one of a VF PCIe TLP, and a PF PCIe TLP;
modifying the PCIe TLP based on configuration registers (206-1), base address registers (BARs) (206-4), mapping tables (206-2), and assignment tables (206-3) associated with a VF of the SR-IOV device (106), wherein the PCIe TLP is a VF PCIe TLP; and
providing the modified PCIe TLP to at least one root (104).

10. A single root-multi root (SR-MR) sharing system (102) for sharing a single root I/O virtualization (SR-IOV) device (106) amongst a plurality of roots (104), the SR-MR sharing system (102) comprising:
a virtual central processing unit (VCPU) (202) to:
identify a physical function (PF) and a plurality of virtual functions (VFs) associated with the SR-IOV device (106);
generate at least one set of VFs from amongst the plurality of identified VFs, wherein each set of VFs include one or more VFs;
generate a pseudo PF (PPF) for each of the at least one set of VFs, wherein the PPF is based on the PF and supports single root I/O virtualization and sharing, and wherein each PPF and a set of VFs associated with the PPF forms a projected SR-IOV device (106); and
send the connect event to the plurality of roots (104) to associate each of the projected SR-IOV device (106) with a root (104) from amongst the plurality of roots (104) to allow sharing of the SR-IOV device (106).

11. The SR-MR sharing system (102) as claimed in claim 10, wherein the SR-MR sharing system (102) further comprises a routing information and configuration register (RICR) (206), wherein the RICR (206) includes configuration registers and routing information tables for each of the projected SR-IOV device (106), and wherein the sending of the connect event is based on the configuration registers and routing information of the RICR (206).

12. The SR-MR sharing system (102) as claimed in claim 11, wherein the RICR (206) comprises at least one of configuration registers (206-1), base address registers (BARs) (206-4), mapping tables (206-2), and assignment tables (206-3).

13. The SR-MR sharing system (102) as claimed in claim 10, wherein the RICR (206) comprises a routing logic (214) to modify a PCIe TLP received from at least one root (104), based on address of the PCIe TLP, and wherein the PCIe TLP is at least one of a memory and an I/O request.

14. The SR-MR sharing system (102) as claimed in claim 11, wherein the RICR (206):
intercepts a PCIe TLP from the SR-IOV device (106) to determine nature of the PCIe TLP, wherein the nature of the PCIe TLP is one of a VF PCIe TLP, and a PF PCIe TLP;
modifies the PCIe TLP, on determining the PCIe TLP to be a VF PCIe TLP, based on configuration registers (206-1), base address registers (BARs) (206-4), mapping tables (206-2), and assignment tables (206-3) associated with a VF of the SR-IOV device (106); and
provides the modified PCIe TLP to at least one root (104).

15. The SR-MR sharing system (102) as claimed in claim 14, wherein the RICR (206) modifies the PCIe TLP based on an ID of the PCIe TLP, and wherein the PCIe TLP is at least one of completion message, and an ID routed message.

16. The SR-MR sharing system (102) as claimed in claim 10, wherein the SR-MR sharing system (102) comprises:
at least one upstream peer to peer (US P2P) (216) bridge to receive a PCIe TLP from at least one root (104); and
at least one virtual downstream peer to peer (DS P2P) (214) bridge to provide the PCIe TLP received by the US P2P (216), to the VCPU (202).

17. The SR-MR sharing system (102) as claimed in claim 16, wherein the VCPU (202) comprises a PF managing module (252) to:
intercept the PCIe TLP to identify status of the SR-IOV device (106) based on at least one of configuration registers (206-1), base address registers (BARs) (206-4), mapping tables (206-2), and assignment tables (206-3) associated with the projected SR-IOV device (106) corresponding to the at least one root (104);
generate a new PCIe TLP based on the identified status of the SR-IOV device (106); and
provide the new PCIe TLP to the SR-IOV device (106) through a V root port (212).

18. The SR-MR sharing system (102) as claimed in claim 16, wherein the VCPU (202) comprises a PF managing module (252) to:
determine the PCIe TLP to be a power management PCIe TLP; and
intercept the power management PCIe TLP to identify status of the SR-IOV device (106) based on at least one of configuration registers (206-1), base address registers (BARs) (206-4), mapping tables (206-2), and assignment tables (206-3) associated with the projected SR-IOV device (106) corresponding to the at least one root (104).

19. The SR-MR sharing system (102) as claimed in claim 18, wherein the PF managing module (252) further provides a new power management PCIe TLP to the SR-IOV device (106) based on the identified status of the SR-IOV device (106).

20. The SR-MR sharing system (102) as claimed in claim 16, wherein the VCPU (202) comprises a PF managing module (252) to:
determine the PCIe TLP to be a port state change PCIe TLP; and
intercept the port state change PCIe TLP to identify status of the SR-IOV device (106) based on at least one of configuration registers (206-1), base address registers (BARs) (206-4), mapping tables (206-2), and assignment tables (206-3) associated with the projected SR-IOV device (106) corresponding to the at least one root (104).

21. The SR-MR sharing system (102) as claimed in claim 20, wherein the PF managing module (252) further provides a new port state change PCIe TLP to the SR-IOV device (106) based on the identified status of the SR-IOV device (106).

22. The SR-MR sharing system (102) as claimed in claim 10, wherein the SR-MR sharing system (102) comprises a V root port (212) to receive a PCIe TLP from the SR-IOV device (106).

23. The SR-MR sharing system (102) as claimed in claim 22, wherein the VCPU (202) comprises a PF managing module (252) to:
intercept the PCIe TLP from the SR-IOV device (106) to determine nature of the PCIe TLP, wherein the nature of the PCIe TLP is one of a VF PCIe TLP, and a PF PCIe TLP;
modify the PCIe TLP based on configuration registers (206-1), base address registers (BARs) (206-4), mapping tables (206-2), and assignment tables (206-3) associated with a VF of the SR-IOV device (106), wherein the PCIe TLP is a VF PCIe TLP; and
provide the modified PCIe TLP to at least one root (104).

24. The SR-MR sharing system (102) as claimed in claim 22, wherein the PF managing module (252):
intercepts the PCIe TLP from the SR-IOV device (106);
generates a new PCIe TLP for the at least one root (104), wherein the PCIe TLP received from the SR-IOV device (106) is a PF PCIe TLP; and
provides the new PCIe TLP to the at least one root (104). ,TagSPECI:As Attached