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Side Channel Attack Protection For Arithmetic And Logic Unit Using Pipeline Randomization And Genetic Algorithm.

Abstract: It has even been shown that Side Channel Attack techniques can be used to obtain the secret key from the popular AES encryption standard. Given such vulnerabilities, several techniques exist to minimize the threat of potential sidechannel attacks.Randomized pipeline is a simple and efficient approach to counter side-channel attacks, but previous methods do not have the ideal protective effect. In this article, based on randomized pipeline, an effective processor architecture resistant to side-channel attacks was proposed. It used a combination of randomized scheduling, randomized instruction insertion and randomized pipeline-delay to resist side-channel attacks.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
30 October 2019
Publication Number
19/2021
Publication Type
INA
Invention Field
COMMUNICATION
Status
Email
mohuyacb@iemcal.com
Parent Application

Applicants

Institute of Engineering and Management
Gurukul, Y-12, Block -EP, Sector-V, Salt Lake Electronics Complex Kolkata – 700 091, West Bengal, India.

Inventors

1. Indranil Roy
Gurukul, Y-12, Block -EP, Sector-V, Salt Lake Electronics Complex Kolkata – 700 091, West Bengal, India.
2. Shekhar Sonthalia
Gurukul, Y-12, Block -EP, Sector-V, Salt Lake Electronics Complex Kolkata – 700 091, West Bengal, India.
3. Trideep Mandal
Gurukul, Y-12, Block -EP, Sector-V, Salt Lake Electronics Complex Kolkata – 700 091, West Bengal, India.
4. Mohuya Chakraborty
Gurukul, Y-12, Block -EP, Sector-V, Salt Lake Electronics Complex Kolkata – 700 091, West Bengal, India.

Specification

Claims:

1. Secure Arithmetic and Logic Unit (ALU) for Central Processing Unit (CPU) of Microprocessors having better pipeline randomization for improving DES and other cryptographic protocols against external monitoring attacks by reducing the amount (and signal-to-noise ratio) of useful information leaked during processing.
2: Usage of Proportional Integral Derivative Value Generated by parameter optimization using Genetic Algorithm for Randomisation of Instruction Pipeline.
3:Dynamically configurable logic gates for Chaotic computing including a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the processed summed signal from the chaotic updater. , Description:In this invention we promote the use of GAs for evolving pipeline randomization with improved side-channel resistance. Our approach shows potential in both creation of S-boxes as well as in the evaluation. However, we are aware of the difficulties that lookup table approach could pose. Nevertheless, we do believe that our results have practical values. In general, one can consider the results as a proof of existence of S-boxes with desired properties. We expect that the results can be optimized further but the main goal was to find S-boxes with high nonlinearity and low transparency order. In this research we used generic GA but the results can be improved by employing custom made GAs, some other evolutionary algorithms like Estimation of Distribution Algorithm, or even to go outside EA area using Swarm Intelligence algorithms and use algorithms like Particle Swarm Optimization. Above all, this paper promotes evolutionary computation as a serious tool for tackling some hard problems in cryptography i.e. evolving S-boxes and their transparency order. In near future, we expect many more attempts in using those mature optimization techniques on cryptographic and other security-related problems.

Documents

Application Documents

# Name Date
1 201931043974-FER.pdf 2024-10-21
1 201931043974-FORM 1 [30-10-2019(online)].pdf 2019-10-30
2 201931043974-DRAWINGS [30-10-2019(online)].pdf 2019-10-30
2 201931043974-FORM 18 [04-10-2023(online)].pdf 2023-10-04
3 201931043974-COMPLETE SPECIFICATION [30-10-2019(online)].pdf 2019-10-30
4 201931043974-DRAWINGS [30-10-2019(online)].pdf 2019-10-30
4 201931043974-FORM 18 [04-10-2023(online)].pdf 2023-10-04
5 201931043974-FER.pdf 2024-10-21
5 201931043974-FORM 1 [30-10-2019(online)].pdf 2019-10-30

Search Strategy

1 Search_Strategy_201931043974E_18-10-2024.pdf