DESCRIPTION SIGNAL PROCESSING APPARATUS TECHNICAL FIELD [0001]The present invention relates to a signal processing apparatus. The present invention particularly relates to a signal processing apparatus suitable for image processing. BACKGROUND ART [0002]For example, Japanese Patent Publication (A) No. 06-4690 discloses an image processing apparatus for processing image capture information of a moving picture or still picture input from a CCD (Charge Coupled Device) or CMOS (Complementary Metal Oxide Semiconductor) or other image capturing device and displaying or storing the same. This image processing apparatus achieves a reduction of the processing time by for example processing the pixel data composing the image capture information in parallel. Further, this image processing apparatus performs read and write processing (memory access) of the pixel data with respect to the memory and processing using the pixel data in synchronization based on the same thread. DISCLOSURE OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION [0003]There is a demand for further improving the processing ability of an image processing apparatus. The same demand also exists in processing other than image processing. [0004]An object of the present invention is to provide a signal processing apparatus improving the access to a storing means to improve the signal processing ability. MEANS FOR SOLVING THE INVENTION [0005]According to the present invention, there is provided a signal processing apparatus comprising storage units, an input/output data control unit (SCU) for controlling reading and/or writing of data to/from a predetermined storage unit in at least one of said storage units, and a signal processing unit (PU array or PU_SIMD) for performing predetermined signal processing on the data read out by said input/output data processing unit, wherein said input/output data control unit and said signal processing unit operate based on different threads. EFFECT OF THE INVENTION [0006]According to the present invention, in the processing accompanied by access to the storing means, by using different threads, a signal processing apparatus able to further raise the image processing ability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS [0007][FIG. 1]FIG. 1 is an overall configuration diagram of an image processing apparatus according to an embodiment of a signal processing apparatus of the present invention. [FIG. 2]FIG. 2 is a view of the configuration of an image processing engine shown in FIG. 1. [FIG. 3]FIG. 3 is a view of the configuration of a processor unit (PU) array shown in FIG. 2. [FIG. 4]FIG. 4 is a view of the configuration of a PU shown in FIG. 3. [FIG. 5]FIG. 5 is a diagram for explaining image regions assigned to PU arrays. [FIG. 6]FIG. 6 is a diagram for explaining pixel data assigning processing to a plurality of processor elements (PE). [FIG. 7]FIG. 7 is a first partial diagram for explaining the assignment of a plurality of PEs in filtering. [FIG. 8]FIG. 8 is a second partial diagram for explaining the assignment of a plurality of PEs in filtering. [FIG. 9]FIG. 9 is a third partial diagram for explaining the assignment of a plurality of PEs in filtering. [FIG. 10]FIG. 10 is a fourth partial diagram for explaining the assignment of a plurality of PEs in filtering. [FIG. 11]FIG. 11 is a view of the configuration of the PE shown in FIG. 4. [FIG. 12]FIG. 12 is a first partial diagram for explaining the filtering performed in a plurality of PEs. [FIG. 13]FIG. 13 is a second partial diagram for explaining the filtering performed in a plurality of PEs. [FIG. 14]FIG. 14 is a first partial diagram for explaining an operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 15]FIG. 15 is a second partial diagram for explaining the operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 16]FIG. 16 is a third partial diagram for explaining the operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 17]FIG. 17 is a fourth partial diagram for explaining the operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 18]FIG. 18 is a fifth partial diagram for explaining the operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 19]FIG. 19 is a sixth partial diagram for explaining the operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 20]FIG. 20 is a seventh partial diagram for explaining the operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 21]FIG. 21 is an eighth partial diagram for explaining the operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 22]FIG. 22 is a ninth partial diagram for explaining the operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 23]FIG. 23 is a 10th partial diagram for explaining the operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 24]FIG. 24 is an llth partial diagram for explaining the operation of a stream register of each PE in the filtering shown in FIG. 13. [FIG. 25]FIG. 25 is a diagram for explaining a shared function unit in a PU. [FIG. 26]FIG. 26 is a first partial diagram for explaining a method of management of a storage region by a stream control unit (SCU) shown in FIG. 3 etc. [FIG. 27]FIG. 27 is a second partial diagram for explaining a method of management of the storage region by an SCU shown in FIG. 3 etc. [FIG. 28]FIG. 28 is a third partial diagram for explaining a method of management of the storage region by an SCU shown in FIG. 3 etc. [FIG. 29]FIG. 29 is a fourth partial diagram for explaining a method of management of the storage region by an SCU shown in FIG. 3 etc. [FIG. 30]FIG. 30 is a fifth partial diagram for explaining a method of management of the storage region by an SCU shown in FIG. 3 etc. [FIG. 31]FIG. 31 is a sixth partial diagram for explaining a method of management of the storage region by an SCU shown in FIG. 3 etc. [FIG. 32]FIG. 32 is a seventh partial diagram for explaining a method of management of the storage region by an SCU shown in FIG. 3 etc. [FIG. 33]FIG. 33 is an eighth partial diagram for explaining a method of management of the storage region by an SCU shown in FIG. 3 etc. [FIG. 34]FIG. 34 is a diagram for explaining processing for execution of a command wset_BR_lof4x4_sam" by an SCU shown in FIG. 3 etc. [FIG. 35]FIG. 35 is a diagram for explaining processing for execution of a command "Set_bxy" by an SCU shown in FIG. 3 etc. [FIG. 36]FIG. 36 is a diagram for explaining processing for execution of a command wset_BR_8xl#to#bxy" by an SCU shown in FIG. 3 etc. [FIG. 37]FIG. 37 is a diagram for explaining processing for execution of a command "set_BR4567#lof4x4" by an SCU shown in FIG. 3 etc. [FIG. 38]FIG. 38 is a diagram for explaining processing for execution of a command "set_in#buf#straight" by an SCU shown in FIG. 3 etc. [FIG. 39]FIG. 39 is a diagram for explaining processing for execution of a command wset_in#buf#with#BR#2xl" by an SCU shown in FIG. 3 etc. [FIG. 40]FIG. 40 is a diagram for explaining processing for execution of a command "set_in#buf# with#BR#4xl" by an SCU shown in FIG. 3 etc. [FIG. 41]FIG. 41 is a diagram for explaining processing for execution of a command "set_BR#16xl" by an SCU shown in FIG. 3 etc. [FIG. 42]FIG. 42 is a diagram for explaining processing for execution of a command "set_BR#32xl" by an SCU shown in FIG. 3 etc. [FIG. 43]FIG. 43 is a diagram for explaining processing for execution of a command "set_BR#64xl" by an SCU shown in FIG. 3 etc. [FIG. 44]FIG. 44 is a diagram for explaining processing for execution of a command wset_BR#64x2" by an SCU shown in FIG. 3 etc. [FIG. 45]FIG. 45 is a diagram for explaining processing for execution of a command "set_BR#64x2x2" by an SCU shown in FIG. 3 etc. [FIG. 46]FIG. 46 is a diagram for explaining processing for execution of a command "set_BR#64x3" by an SCU shown in FIG. 3 etc. [FIG. 47]FIG. 47 is a diagram for explaining processing for execution of a command "set_BR#64x3x3" by an SCU shown in FIG. 3 etc. [FIG. 48]FIG. 48 is a diagram for explaining processing for execution of a command "set_BR#64x4" by an SCU shown in FIG. 3 etc. [FIG. 49]FIG. 49 is a diagram for explaining processing for execution of a command "set_BR#64x4x4" by an SCU shown in FIG. 3 etc. [FIG. 50]FIG. 50 is a diagram for explaining processing for execution of a command wset_BR#64x9" by an SCU shown in FIG. 3 etc. [FIG. 51]FIG. 51 is a diagram for explaining processing for execution of a command "set_BR#64x9x3" by an SCU shown in FIG. 3 etc. [FIG. 52]FIG. 52 is a diagram for explaining a method of management of a storage region by an SCU shown in FIG. 3 etc. [FIG. 53]FIG. 53 is a diagram for explaining a method of management of a storage region by an SCU shown in FIG. 3 etc. [FIG. 54]FIG. 54 is a diagram for explaining a method of management of a storage region by an SCU shown in FIG. 3 etc. [FIG. 55]FIG. 55 is a diagram for explaining processing for execution of a command "set#DR#mask#64xl" by an SCU shown in FIG. 3 etc. [FIG. 56]FIG. 56 is a diagram for explaining processing for execution of a command "set#DR#packed#64xl" by an SCU shown in FIG. 3 etc. [FIG. 57]FIG. 57 is a diagram for explaining processing for execution of a command "set#DR#64xl" by an SCU shown in FIG. 3 etc. [FIG. 58]FIG. 58 is a diagram for explaining processing for execution of a command "set#DR#128xl" by an SCU shown in FIG. 3 etc. [FIG. 59]FIG. 59 is a diagram for explaining processing for execution of a command "set#DR#192xl" by an SCU shown in FIG. 3 etc. [FIG. 60]FIG. 60 is a diagram for explaining processing for execution of a command "set#DR#256xl" by an SCU shown in FIG. 3 etc. [FIG. 61]FIG. 61 is a diagram for explaining a command "exec" executed by an SCU. [FIG. 62]FIG. 62 is a diagram for explaining a command "Branch" executed by an SCU. [FIG. 63]FIG. 63 is a diagram for explaining a command "set" executed by an SCU. [FIG. 64]FIG. 64 is a diagram for explaining a command "addition" executed by an SCU. [FIG. 65]FIG. 65 is a diagram for explaining a specific command executed by an SCU and parameters. [FIG. 66]FIG. 66 is a diagram for explaining relationships of processing between an SCU and a processor unit. [FIG. 67]FIG. 67 is a diagram for explaining queuing of commands and data in an SCU. [FIG. 68]FIG. 68 is another diagram of the configuration of the image processing engine shown in FIG. 2. [FIG. 69]FIG. 69 is a diagram of the overall configuration of an image processing engine 102 of a second embodiment. [FIG. 70]FIG. 70 is a view of the configuration of a PU array 202_0 shown in FIG. 69. [FIG. 71]FIG. 71 is a view of the configuration of a PEn in the second embodiment. [FIG. 72]FIG. 72 is a block diagram showing a structure of an SCU #10. [FIG. 73]FIG. 73 is a partial diagram for explaining a method of management of a storage region by a stream control unit (SCU) in a second embodiment. [FIG. 74]FIG. 74 is a diagram for explaining a function for processing multiplex rectangular image regions set inside the SCU #10. [FIG. 75]FIG. 75 is a diagram showing an example of a method of definition of a rectangular image region BR in a rectangular image region WIR in a storage region in the second embodiment. [FIG. 76]FIG. 76 is a diagram showing an example of a method of definition of a rectangular image region DR in a rectangular image region WOR in a storage region in the second embodiment. DESCRIPTION OF REFERTENCES [0008]100... image processing apparatus, 101... host processor, 102... image processing engine, 103... codec engine, 104... memory I/F, 105... memory system, 106... sensor I/F, 107... camera module, 108... storage medium I/F, 109... storage medium, 110... internal display device I/F, 111... built-in display device, 112... video I/F, 201... control processor, 202_0 to 3... processor unit (PU) array, 203_0 to 3... SCU, 204_0 to 3... local memory, PU... processor unit, 401... in line buffer, 403... shared function unit, 404... out line buffer, PE... processor element, SRO to 2... stream register, ALU... arithmetic and logic unit BEST MODE FOR CARRYING OUT THE INVENTION [0009]End)idxw =Start+(idx-End-1)%(End-Start+1); else if (idx=aw)|(y+by>ah))pixel(x, y)=COL else pixel(x, y)=AR(x+bx, y+by) ...(7) [0103](Rectangular image region) BR mode 2: When set in the BR mode 2, the SOU 203_0 can set the rectangular image region BR outside of the rectangular image region AR. As shown in FIG. 31, when the rectangular image region BR is outside the rectangular image region AR in the X-direction, the SCU 203_0 controls the outside region to be folded back inside the rectangular image region AR. As shown in FIG. 31, when the rectangular image region BR is outside the rectangular image region AR in the X-direction and the Y-direction, the SCU 203_0 does not fold it back in the rectangular image region AR and sets the value of the pixel data Pixel as (COL). The SCU 203_0 determines the pixel data Pixel (x, y) in the rectangular image region BR as in the following Equation (8) by using the pixel data AR() in the rectangular image region AR. [0104][Equation 8] if(aw<=x+bx)&(y+by<=ah-bh)pixel(x, y)=AR(x+bx-aw, y+by+bh) else if (aw<=x+bx)&(ah-bh=cw)|(y+dy>ch)) pixel(x, y) is not WRitten into CR else CR(x+dx, y+dy)=pixel(x, y) ...(10) [0134JDR mode 2: The SCU 203_0 can set the rectangular image region DR outside from the rectangular image region CR where it is set in the DR mode 2. As shown in FIG. 54, when the rectangular image region DR is outside the rectangular image region CR in the x-direction, the SCU 203_0 controls the outside region to be folded back inside the rectangular image region CR. Further, as shown in FIG. 54, when the rectangular image region DR is outside the rectangular image region CR in the x-direction and the y-direction, the SCU 203_0 does not write the pixel data in the rectangular image region DR into the rectangular image region CR. The pixel data in the rectangular image region DR is defined as in the following Equation (11) in the rectangular image region CR. [0135][Equation 11] if(cw <=x+dx)&(y+dy <=ch-dh) CR(x+dx-cw, y+dy+dh)=pixel(x, y) else if (cw <=x+dx)&(ch-dh The image processing apparatus 100 of the second embodiment has the same configuration as that of the first embodiment as shown in FIG. I, but differs in the configuration of the image processing engine 102 from that of the first embodiment. The configuration of the image processing apparatus 100 other than the image processing engine 102 is the same as that of the first embodiment, therefore the explanation is omitted here. Below, an explanation will be given of the configuration of the image processing engine 102 of the second embodiment. [0165][Image Processing Engine 102] In the same way as the first embodiment, the image processing engine 102 is the programmable image processor, and executes the image processing instructed by the host processor 101 in accordance with the application program executed in the image processing apparatus 100. The image data covered by the image processing includes data captured by the camera module 107 input via the sensor I/F 106, data stored in the memory system 105 input via the memory I/F 104, data stored in the storage medium 109 input via the storage medium I/F 108, data given from the codec engine 103, and data processed at the codec engine 103. The image processing engine 102 stores its own processing results via the memory I/F 104 in the memory system 105, stores the same via the storage medium I/F 108 in the storage medium 109, outputs them to the codec engine 103, displays the same in the built-in display device 111 via the built-in display device I/F 110, and outputs the same via the video I/F 112 to an outside apparatus. [0166]FIG. 69 is a diagram of the overall configuration of the image processing engine 102 of the second embodiment. As shown in FIG. 69, the image processing engine 102 has a control processor (CPU) 201, PU (processor unit) arrays 202_0 to 202_3, and local memories 204_0 to 204_3. [0167]The control processor 201 is a processor for controlling the entire image processing engine 102 and handles the setup and activation of the components of the image processing engine 102 and processing at SIMD (Single Instruction Multiple Data) type processor arrays constituting the PU arrays 202 - for which parallel processing is difficult. [0168]The PU arrays 202_0 to 202_3 are programmable processors configured by a plurality of SIMD type processor arrays as will be explained later. Further, the PU arrays 202_0 to 203_3 of the present embodiment differ from the first embodiment in the point that the SCUs (Stream Control Units) are provided inside them as will be explained later. [0169]The local memories 204_0 to 204_3 are working memories of the image processing engine 102 which hold part of the pixel data stored in the memory system 105, store the intermediate results processed at the PU arrays 202_0 to 202_3 and programs executed at the PU arrays 202_0 to 202_3, store various types of parameters, etc. [0170]The image processing engine 102 operates for example the PU arrays 202_0 to 202_3 shown in FIG. 69 by a shared thread under the control of the host processor 101. The "shared thread" means that the processing is advanced based on for example a shared program. [0171] [PU Arrays 202_0 to 202_3] An explanation will be given of the PU array 202_0. The PU arrays 202_1 to 202_3 have the same configuration as that of the PU array 202_0. FIG. 70 is a view of the configuration of the PU array 202_0 shown in FIG. 69. As shown in FIG. 70, the PU array 202_0 has four PU_SIMD (Single Instruction Multiple Data) processing circuits #0 to #3 and SCUs #10 to #13 connected corresponding to the PU_SIMDs. [0172]The PU_SIMD processing circuit #0 has a control unit 303_0 and four processor units PU#00 to PU#03. The four processor units PU #00 to #03 configure a SIMD type processor operating by the same command. Four processor units PU #00 to #03 are laterally connected one-dimensionally. By limiting the connection among the processor units PU #00 to #03 to between adjacent processor units and sharing the I#BUS used for the supply of data from the SCU among four processor units, the interconnects can be reduced and, at the same time, the bus control can be made easy. By serially connecting the processor units PU #00 to #03, in image processing frequently using the adjacent pixel data, the pixel data can be directly output to the adjacent processor units without going the local memory, so the processing time can be shortened. The PU_SIMD processing circuits #1 to #3 have the same configuration as that of the PU_SIMD processing circuit #0. [0173][Processor Unit PU#00] The configuration of the processor unit PU#00 is the same as the explanation given relating to FIG. 4 in the first embodiment, therefore the explanation is omitted here. [0174]The data input from the SCU (Stream Control Unit) #10 to the processor unit PU#00 via the input data bus I_BUSO is written into the in line buffer 401 in the PU#00. Each of the processor elements PEO to PE15 performs the processing by using the data read out from the in line buffer 401 and writes the processing result into the out line buffer 404. The SCU #10 reads out the processing result from the out line buffer 404. [0175]As shown in FIG. 70, the PU array 202_0 can independently operate four PU_SIMD processing circuits #0 to #3 in parallel or can directly operate these. When these operate in series, they are connected by utilizing the connection among SCUs. [0176]The control unit 303_0 shown in FIG. 70 has a not shown command storage use memory and outputs a control signal obtained by decoding the command read out from the command storage use memory to all PEs in the PU_SIMD #0. The control unit 303_0 includes a program flow control use loop register not shown here and a pointer register for accessing the stream register in the PE. The loop register is a register for controlling the number of loops in the program and can be set by the control processor 201 or can be set by a command at the time of the execution of the program. When the loop register is set by the command, the register value in the PE can be designated as the source operand. At that time, use is made of the register value of the previously determined PE among a plurality of PEs, for example, the PE on the left end in the figure, for example, the PEO of the processor unit PU#00. For the pointer register as well, the register value in PE can be designated as the source operand, but use is made of the register value of a specific PE in the same way as the case of the loop register. The same is also true for the control units 303_1 to 303_3. [0177]An explanation will be given of the processing routine and processing distribution in the image processing apparatus 100 using as an example the case of storing the still image captured by using the camera module 107. [0178]The data captured by the image capturing device in the camera module 107 is read out via the sensor I/F 106 for each horizontal scan line, is output to the image processing engine 102, and is stored in the memory system 105. At this time, the image processing engine 102 executes part of the wave detection processing. When 1 frame's worth of the data is stored in the memory system 105, the image processing engine 102 executes the remaining wave detection processing and various types of camera signal processing and various types of image processing while reading the required rectangular image region in the 1 frame's worth of image data in order to make the internal PU SIMD processing circuits operate in parallel efficiently. The processing results of the image processing engine 102 are stored in the memory system 105. The image processing engine 102 also converts the resolution. The resolution-converted image data is displayed via the built-in display device I/F 110 in the built-in display device 111. The codec engine 103 performs image compression by using the image data of a plurality of frames processed by the image processing engine 102 and stored in the memory system 105. The compressed image data is stored via the storage medium I/F 108 in the storage medium 109. [0179]The image processing engine 102 is configured by a plurality of PU arrays 202_0 to 202_3. The PU arrays 202_0 to 202_3 process different regions in the frame. When the image processing engine is configured by the four PU arrays 202_0 to 202_3 as in the present embodiment, for example as explained with reference to FIG. 5 in the first embodiment, regions can be assigned to the PU arrays 202_0 to 202_3. Each of the PU arrays 202_0 to 202_3 has a plurality of PU_SIMD processing circuits configured by 64 PEs as explained before. For example, as explained with reference to FIG. 6 in the first embodiment, the region assigned to each of the PU arrays 202 0 to 202 3 is further divided to rectangular image regions each having lateral 64-pixel width. Each pixel can be assigned to one PE. At this time, each PE sequentially processes a pixel train in a vertical direction assigned to itself as explained with reference to FIG. 7 in the first embodiment. [0180]For example, a case where the PU array 202_0 performs filtering of 5 x 5 pixels as shown in FIG. 8 of the first embodiment will be considered. At this time, each PE in the PU array 202_0 uses the pixel data at the 5x5 pixel positions around a pixel position Pixel in order to perform the filtering of pixel data at the pixel position Pixel for processing as shown in FIG. 8 of the first embodiment. Each PE in the PU array 202_0 sequentially moves the pixel position to be processed as instructed by the arrow shown in FIG. 8 (downward direction in the figure). When each PE in the PU array 202_0 ends the filtering of 5x5 pixels described above at the pixel position Pixel, the SCU 203_0, as shown in FIG. 9 of the first embodiment, reads out the pixel data at the pixel position of the next 1 line from the local memory 204_0 or memory system 105 and writes it into the in line buffer 401 of the processor unit PU in the PU array 202_0 shown in FIG. 4. Then, each PU in the PU array 202_0 performs the filtering of 5 x 5 pixels of the pixel data at the next pixel position Pixel_next as shown in FIG. 10 of the first embodiment. [0181]Note that, in the above explanation, the PU_SIMD #0 shown in FIG. 70 was focused on for the explanation, but the PU_SIMD #1 to #3 are the same as the PU_SIMD #0. The PU arrays 202_1 to 202_3 are the same as the PU array 202_0. [0182][Processor Element PE] Next, an explanation will be given of PEn (n =1 to 14) . Note that PEO is the same as the PEn except for the point that, between PEs, it inputs/outputs data only with the PE1, and the PE15 is the same except that it inputs/outputs data only with the PE14. FIG. 71 is a view of the configuration of the PEn in the second embodiment. As shown in FIG. 71, the PEn has the multiplexers MUX1000 and 1001, various types of registers such as the stream registers SRO to SR3, and an arithmetic and logical unit ALU. [0183]The in line buffer 401 is a buffer receiving the input data sent from an SCU (Stream Control Unit). It can hold one stage's worth of 16-bit data per PE. The out line buffer 404 is a buffer sending the processing results in a PE to the SCU. It can hold one stage's worth of 16-bit data per PE. [0184]The stream registers SRO to SR3 are register files each having a 16-bit width and 16 entries, and each PE has four SRs in total. The stream registers SRO to SR3 are registers for storage of the data required for the processing mainly supplied from the SCU and temporary backup of the processing results and can perform the access by access by direct address designation. Four pointers at the maximum can be defined for each stream register. Each pointer has the following three values. Namely, these are "Start" as the start point of the pointer definition region, "End" as the end point of the pointer definition region, and "Current" as the current pointer position. Note, End must be equal to or larger than Start. By making the Starts and Ends of the two pointers the same and using one as the read pointer and using the other as the Wwrite pointer, this can be made to function as an FIFO. Further, the Start and End may be changed for each pointer. Further, overlapping of regions designated by Start and End on each other is not prohibited for completely independent pointers in the same stream register. [0185]Below, the functions related to the stream registers SRO to SR3 will be explained. 1) Access to the stream registers SRO to SR3 There are two types of access methods when performing writing or reading with respect to the stream registers SRO to SR3, i.e., pointer access and direct access. Pointer access is access by offset from Current of the designated pointer. The offset value is a positive integer within a range from 0 to 15 in the case of reading, while a positive integer within a range from 0 to 3 in the case of writing. Direct access designates entry in the stream registers SRO to SR3 by an immediate value. The immediate value is a positive integer within the range from 0 to 15. [0186]2) Pointer Operation Commands for realizing the pointer operation as shown below are prepared. a) Immediate designation of value held by the pointer Values of Start and End are designated by the immediate value. b) Immediate addition with respect to Current value The added immediate value is an integer within a range from -8 to 7. c) Initialization of value held by pointer Values of Start, End, and Current are initialized to 0, 15, and 0 after reset. Further, a command for initializing the Current value to the Start value is prepared. [0187]3) Wraparound When performing the pointer access or pointer operation with respect to the stream registers SRO to SR3, this sometimes exceeds the region defined by . In this case, the following wraparound is carried out. Here, when the indexes before and after Wraparound to the entry of the stream registers SRO to SR3 are dxbw and idxaw, the following stand. idxaw=(idxbw>End)? Start*(idxbw-End-1)%(End-Start+1): idxbw idxaw=(idxbw