FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION [See section 10, Rule 13]
SIGNAL PROCESSING DEVICE AND TESTING METHOD;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANISED
AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3,
MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 1008310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.

DESCRIPTION
Technical Field [0001] The present disclosure relates to a signal processing device and a testing method.
Background Art [0002] A system that includes both analog circuits and digital circuits employs converters such as an A/D converter and a D/A converter for conversion of an analog signal from/to a digital signal. A failure of converters in such a system prevents the system from achieving normal conversion processing of an analog signal and a digital signal so that normal operation of the system becomes difficult. Thus, accurate detection of the failure of the converter is desirable.
[0003] Various test methods for detecting the failure of the converter are proposed. For example, Patent Literature 1 proposes a technique for detecting a failure by inputting an analog test signal into an A/D converter and determining whether data output from the A/D converter is within a range of predetermined conversion standard values. This test method, however, has difficulty in detecting a failure in a case where lower bits of data output from the A/D converter are unchanged, fixed to 1 or 0, and the data contains a small amount of noise.
[0004] On the other hand, Patent Literature 2 discloses a technique of inputting a plurality of reference voltages into an A/D converter and determining whether an actual output value and a normal output value coincide. This technique enables detection of even an error in which certain bits of data output from the A/D converter are fixed to 0 or 1.
Citation List Patent Literature [0005] Patent Literature 1: Unexamined Japanese Patent Application Kokai

Publication No. 2007-285764
Patent Literature 2: Unexamined Japanese Patent Application Kokai Publication No. H8-56160
Summary of Invention Technical Problem [0006] As described above, the technique of Patent Literature 1 has difficulty in detecting a failure in which certain bits of a digital data item are fixed to 1 or 0. [0007] Furthermore, the technique of Patent Literature 2 detects an error by determining whether the actual output value from the A/D converter and the normal output value coincide, and thus, although able to detect the error, is unable to identify a type of the error. In the case of occurrence of an error in which certain bits of data are fixed to 0 or 1, for example, although the technique enables detection of the error, further analysis of output values is required for identifying that the error is an error in which certain bits of data are fixed.
[0008] Similar problems occur in testing a D/A converter. [0009] The present disclosure is made in light of the aforementioned problems, and an objective of the present disclosure is to enable easy detection of a failure in which values of certain bits are fixed. Solution to Problem
[0010] In order to solve the aforementioned problems, a signal processing device of the present disclosure includes:
A/D conversion means for converting an analog signal into a digital signal and outputting the digital signal;
supplying means for supplying, to the A/D conversion means, an analog test signal corresponding to a test bit pattern;
determination means for determining, when a level of the analog test signal supplied to the A/D conversion means switches, whether a value of a bit to be tested of

the digital signal output by the A/D conversion means switches after switching of the level of the analog test signal; and
output means for outputting a result of the determination by the determination means.
Advantageous Effects of Invention [0011] According to the present disclosure, a determination is made as to whether a value of a bit to be tested of the digital signal obtained through conversion of an analog test signal and output by the A/D conversion means switches after the level of the analog test signal switches. This configuration enables detection of occurrence of a failure in which a value of a bit is fixed based on an output value from the A/D conversion means without comparing an input value and the output value from the A/D conversion means, thereby enabling easy detection of a failure in which a value of a bit is fixed.
Brief Description of Drawings [0012] FIG. 1 is a block diagram of a signal processing device according to Embodiment 1 of the present disclosure;
FIG. 2 is a diagram showing an example of a pattern table stored in a storage of FIG. 1;
FIG. 3 is a flowchart of test processing performed by the signal processing device according to Embodiment 1;
FIG. 4A shows the flag and a change in values in the flag immediately after initialization;
FIG. 4B shows the flag and a change in values in the flag, in which all bit values of data output from an A/D converter are switched;
FIG. 4C shows the flag and a change in values in the flag, in which the least significant bit of data output from the A/D converter is fixed to zero;
FIG. 4D shows the flag and a change in values in the flag, in which the least significant bit is fixed to 1;

FIG. 5A is a first diagram showing another example of the pattern table according to Embodiment 1;
FIG. 5B is a second diagram showing still another example of the pattern table according to Embodiment 1;
FIG. 5C is a third diagram showing still another example of the pattern table according to Embodiment 1;
FIG. 6 is a block diagram of a signal processing device according to Embodiment
2 of the present disclosure;
FIG. 7 is a flowchart of test processing performed by the signal processing device according to Embodiment 2;
FIG. 8 is a block diagram of a signal processing device according to Embodiment
3 of the present disclosure;
FIG. 9 is a flowchart of test processing performed by the signal processing device according to Embodiment 3;
FIG. 10 is a block diagram of a signal processing device according to Embodiment
4 of the present disclosure;
FIG. 11 is a flowchart of operation test processing performed by the signal processing device according to Embodiment 4;
FIG. 12 is a flowchart of test processing performed by a signal processing device according to Embodiment 5 of the present disclosure;
FIG. 13 is a block diagram of a signal processing device according to Embodiment 6 of the present disclosure;
FIG. 14 is a diagram showing an example of a pattern table according to Embodiment 7 of the present disclosure;
FIG. 15 is a flowchart of test processing performed by a signal processing device according to Embodiment 7;
FIG. 16 is a block diagram of a signal processing device according to Embodiment

8 of the present disclosure;
FIG. 17 is a block diagram of a signal processing device according to Modification
1 of the present disclosure; and
FIG. 18 is a block diagram of a signal processing device according to Modification
2 of the present disclosure.
Description of Embodiments [0013] Hereinafter embodiments of the present disclosure are described in detail with reference to the drawings. [0014] Embodiment 1
A signal processing device 10 according to the present embodiment has an A/D conversion function for converting an analog signal into a digital signal and outputting the digital signal by an A/D converter and a test function for performing an operation test of an A/D converter by supplying test signals to the A/D converter and monitoring changes in a value of each bit of data output from the A/D converter. [0015] Hereinafter an operation by the A/D converter of converting an input analog signal into a digital signal and outputting the digital signal is referred to as a normal operation, and an operation of testing the A/D converter is referred to as a test operation. In the following description, the signal may be either a voltage signal or a current signal. [0016] As illustrated in FIG. 1, the signal processing device 10 includes an input terminal 101 into which an analog signal is input, an output terminal 102 for outputting a converted digital signal, a storage 11 that stores data, a test signal supplier 12 that generates an analog test signal used for the operation test, a selector 13 that selects a signal to be input into an A/D converter 14, the A/D converter 14 that serves as an A/D conversion unit, a determiner 15 that determines whether the A/D converter 14 fails, and an outputter 16 that outputs information indicating that the A/D converter 14 fails. [0017] The input terminal 101 is a terminal for inputting from the exterior an analog signal to be converted by the signal processing device 10 into a digital signal. A

temperature sensor, an illuminance sensor, a speed sensor and other sensors, or a device that outputs an analog signal, for example, are connected to the input terminal 101. A direct current voltage that falls within a range from -10V to +10V or a direct current that falls within a range from 0 mA to 20 mA, for example, is input into the input terminal 101.
[0018] The output terminal 102 is a terminal for outputting values of bits of the digital signal in parallel converted by the signal processing device 10. A device that utilizes signals output by the signal processing device 10 is connected to the output terminal 102. The output terminal 102 outputs, for example, a 16-bit digital signal indicating an integer that falls within the range from -32,768 to +32,767, or a 15-bit digital signal indicating an integer that falls within the range from 0 to 32,767. [0019] The storage 11 includes a nonvolatile memory such as an Electrically Erasable Programmable Read-Only Memory (EEPROM) and a flash memory. The storage 11 stores various data utilized by the signal processing device 10. The data includes a pattern table 111 used in generating an analog test signal for testing the A/D converter 14. Although not limiting the present disclosure, the storage 11 functions as the storage means in the claims.
[0020] The pattern table 111 is a list including two predetermined test bit patterns. Each of the test bit patterns is used for determining whether values of bits of the digital signal output from the A/D converter 14 change without being fixed. As shown in the example of FIG. 2, the pattern table 111 according to the present embodiment is a list including two test bit patterns. These test bit patterns are determined such that each bit of all bits to be tested has a value complementary to a value of the corresponding bit. That is to say, a value of one test bit pattern is set to be one's complement of the value of the other test bit pattern.
[0021] In performing the test operation, the test signal supplier 12 generates analog test signals corresponding to the test bit patterns and supplies the analog test signals to the

A/D converter 14 via the selector 13. Although not limiting the present disclosure, the test signal supplier 12 functions as the supplying means in the claims. [0022] More specifically, the test signal supplier 12 includes a test signal generation module 121. The test signal generation module 121 includes a D/A converter circuit to generate analog test signals from the test bit patterns of the pattern table 111. The test signal generation module 121 has conversion characteristics that enable a conversion opposite to a conversion achieved by conversion characteristics of the A/D converter 14. Such conversion characteristics allow the test signal generation module 121 to generate an analog test signal having a signal level that causes the A/D converter 14 to output digital signals equal to the test bit patterns read from the storage 11. The test signal supplier 12 sequentially reads from the pattern table 111 the test bit patterns to generate the analog test signals. In such a manner, the test signal supplier 12 changes a signal level of the analog test signal, thereby switching a value of each bit of the digital signal output from the A/D converter 14. The test signal supplier 12 outputs the generated analog test signal to the selector 13.
[0023] During normal operation, the selector 13 selects an analog signal to be A/D-converted that is supplied from the exterior via the input terminal 101 and supplies the analog signal to the A/D converter 14. In performing the test operation, the selector 13 selects the analog test signal supplied from test signal supplier 12 and supplies the analog signal to the A/D converter 14. In the following description, for unambiguous distinction from the analog test signal, the analog signal supplied to the input terminal 101 is also expressed as a non-test signal.
[0024] The A/D converter 14 serves as an A/D converter circuit. The A/D converter 14 discretizes and quantizes a supplied analog signal at a predetermined sampling period and resolution, converts the discretized and quantized analog signal into a digital signal, and outputs the digital signal to the output terminal 102 and the determiner 15. During normal operation, the A/D converter 14 converts a non-test

signal supplied from the selector 13, that is, a to-be-converted analog signal supplied from the exterior via the input terminal 101, into a digital signal and outputs the digital signal. In performing the test operation, the A/D converter 14 converts the analog test signal supplied from the selector 13 into a digital signal and outputs the digital signal. The digital signal output from the A/D converter 14 in performing the test operation is to have, provided that the A/D converter 14 operates normally, a value equal to the value of the test bit pattern from which the supplied analog test signal is generated by the test signal supplier 12. Although not limiting the present disclosure, the A/D converter 14 functions as the A/D conversion means in the claims.
[0025] The determiner 15 includes a Micro Processer Unit (MPU). The determiner 15 determines whether values of bits included in the digital signal obtained through conversion of the analog test signal and output by the A/D converter 14 switch when a level of the analog test signal switches. Specifically, to determine whether a failure in which a value of a bit is fixed occurs, the determiner 15 determines, for each bit of a plurality of to-be-tested bits of the digital data item, whether a value of the bit differs before versus after the level of the analog test signal switches. The level of the analog test signal corresponds to the test bit patterns, and thus the determiner 15 determines whether a bit value of the digital signal switches when the test bit pattern corresponding to the analog test signal switches. A method for performing the determination is described below. To perform the determination, the determiner 15 is provided with a flag that includes data showing whether the value of each bit included in the digital signal has switched. The flag is described in detail below. Although not limiting the present disclosure, the determiner 15 functions as the determination means in the claims. [0026] The outputter 16 includes, for example, an Network Interface Controller (NIC) that enables communication with external devices via a network, and a Light Emitting Diode (LED) or a buzzer. The outputter 16 outputs a result of the determination by the determiner 15. Specifically, when the determiner 15 determines

that a failure in which a value of a bit is fixed occurs, the outputter 16 outputs information
indicating a failure of the A/D converter 14. This information may be data indicating
details of the failure and may be output as illumination of the LED or a warning sound of
the buzzer. Although not limiting the present disclosure, the outputter 16 functions as
the output means in the claims.
[0027] The controller 17 includes an MPU, a Read Only Memory (ROM), and a
Random Access Memory (RAM). The controller 17 centrally controls each component
of the signal processing device 10 by the MPU thereof, utilizing the RAM as work area to
execute a program stored in the ROM or the storage 11. The controller 17 may also
serves as the determiner 15 and the outputter 16.
[0028] Next, processing performed by the signal processing device 10 is described
with reference to FIGS. 3 and 4. During normal operation of the signal processing
device 10, the controller 17 causes the selector 13 to select the analog signal supplied to
the input terminal 101. This allows the signal processing device 10 to perform normal
conversion operation of converting, by the A/D converter 14, the analog signal supplied
to the input terminal 101 into a digital signal, and outputting, from the output terminal
102, the digital signal.
[0029] On the other hand, to test an operation of the A/D converter 14, the
controller 17 performs test processing illustrated in FIG. 3. This test processing starts at
a predetermined timing.
[0030] Although all of the following operations are to be performed under control
of the controller 17, to facilitate understanding, such control is not mentioned each time.
In the test processing, the signal processing device 10 selects the analog test signal as a
signal to be input into the A/D converter 14 (step S1). Specifically, the selector 13 is
made to select the analog test signal output from the test signal supplier 12.
[0031] Next, the signal processing device 10 initializes the flag equipped with the
determiner 15 (step S2). The flag is data indicating whether a value of each bit included

in the digital signal output from the A/D converter 14 has switched. A flag according to the present embodiment is formed as hardware by including two latch arrays. The method for achieving the flag is not limited to this method, and the flag may be achieved as a flag field by software.
[0032] A flag initialization process includes assigning a value of "FFFFh" to a first latch and a value of "0000h" to a second latch. FIG. 4A shows a state of the flag immediately after completion of initialization. The value of "FFFFh" indicates a 16-bit pattern in which all bit values are 1, and the last "h" of this value indicates that the value is expressed in hexadecimal.
[0033] Next, the signal processing device 10 selects a first test bit pattern of the pattern table 111(step S3). Specifically, the test signal supplier 12 reads from the storage 11 a first test bit pattern included in the pattern table 111. The test signal supplier 12 reads, for example, a test bit pattern of "11...11" from the pattern table 111 shown in FIG. 2.
[0034] Next, the signal processing device 10 generates an analog test signal having a level corresponding to the selected test bit pattern and supplies the analog test signal to the A/D converter 14 (step S4). Specifically, the test signal generation module 121 of the test signal supplier 12 generates, by performing a D/A conversion, an analog signal that causes the A/D converter 14 to output a digital signal equal to the selected test bit pattern. For example, in step S4 following step S3 in which the first test bit pattern of FIG. 2 is selected, the test signal generation module 121 generates an analog test signal that causes the A/D converter 14 to output a digital signal of "11...11". [0035] Next, the signal processing device 10 updates the flag according to a bit value of the digital signal output from the A/D converter 14(step S5). Specifically, the determiner 15 updates a value of the first latch array using a result of an AND operation between an output value from the A/D converter 14 and the value of the first latch array, and updates a value of the second latch array using a result of an OR operation between

the output value from the A/D converter 14 and the value of the second latch array. When, for example, an analog test signal having a level corresponding to the first test bit pattern of FIG. 2 is generated and the A/D converter 14 operates normally, the value of the first latch array is updated to "FFFFh" as a result of the AND operation and the value of the second latch array is updated to "FFFFh" as a result of the OR operation. On the other hand, when, for example, the A/D converter 14 operates abnormally and causes a value of the least significant bit of data output from the A/D converter 14 to be fixed to zero, the value of the first latch array is updated to "FFFEh" as a result of the AND operation and the value of the second latch array is updated to "FFFEh" as a result of the OR operation.
[0036] Next, the signal processing device 10 determines whether the currently selected test bit pattern is the last test bit pattern (step S6). Specifically, the determiner 15 determines whether a test bit pattern assigned the last number in the pattern table 111 is selected.
[0037] Upon determination that the currently selected test bit pattern is not the last bit pattern, (No in step S6), the signal processing device 10 selects the next test bit pattern (step S7). Specifically, the test signal supplier 12 reads a test bit pattern assigned the next number from the pattern table 111 of the storage 11. For example, the test signal supplier 12 reads a test bit pattern of "00...00" as a second bit pattern after reading the first test bit pattern shown in FIG. 2,.
[0038] Following step S7, the signal processing device 10 repeats the processes in and after step S4. This repetition allows subsequent generation of analog test signals, each corresponding to either one of the test bit patterns included in the pattern table 111, thereby enabling update of the flag at each time the level of the analog test signal is changed. When, for example, an analog test signal having a level corresponding to the second test bit pattern of FIG. 2 is generated and the A/D converter 14 operates normally, the value of the first latch array is updated to "0000h" as a result of the AND operation

and the value of the second latch array is updated to "FFFFh" as a result of the OR operation, as shown in FIG. 4B.
[0039] When, for example, the A/D converter 14 operates abnormally and causes a value of the least significant bit (LSB) of data output from the A/D converter 14 to be fixed to zero, the value of the first latch array is updated to "0000h" as a result of the AND operation and the value of the second latch array is updated to "FFFEh" as a result of the OR operation, as shown in FIG. 4C. When the value of the least significant bit is fixed to 1, the value of the first latch array is updated to "0001h" as a result of the AND operation and the value of the second latch array is updated to "FFFFh" as a result of the OR operation, as shown in FIG. 4D. Comparing the value of the first latch array and the value of the second latch array in such a manner enables determination of, for each bit, a case in which a value of the bit is fixed to 1 and a case in which a value of the bit is fixed to zero.
[0040] Upon determination in step S6 that the currently selected test bit pattern is the last test bit pattern (Yes in step S6), the signal processing device 10 determines, for each bit to be tested, whether a value of the bit switches after the level of the analog test signal changes (step S8). In other words, the signal processing device 10 determines, for each bit to be tested, whether a value of the bit has become both 1 and 0. Specifically, by determining whether the value of the first latch array is "0000h" and the value of the second latch array is "FFFFh" as illustrated in FIG. 4B, the determiner 15 determines whether each value of the bit to be tested of the bits included in the digital signal output from the A/D converter 14 has become a value different from that before the change of the level of the analog test signal. For example, when the flag is in a state illustrated in FIG. 4B, a determination is made that all values of bits have switched. When the flag is in a state illustrated in FIG. 4C or 4D, a determination is made that the value of the least significant bit has not switched. [0041] Upon determination that all values of the bits have switched (Yes in step S8),

the signal processing device 10 selects the non-test signal as a signal to be input into the A/D converter 14(step S9). Specifically, the selector 13 selects the non-test signal by controlling a switching device to switch a transmission line of a signal and to connect the input terminal 101 with the A/D converter 14. At this time, the outputter 16 may output information indicating that the A/D converter 14 operates normally. Then, the signal processing device 10 ends the test processing.
[0042] On the other hand, upon determination that values of certain bits to be tested have not switched (No in step S8), the signal processing device 10 outputs an error signal (step S10). Specifically, the outputter 16 outputs a result of the determination by the determiner 15. Information output from the outputter 16 may include information indicating that the A/D converter 14 fails, information indicating a position of a bit included in the digital signal and whose value is fixed, and information indicating whether the fixed value is 1 or zero. Then, the signal processing device 10 ends the test processing. The signal processing device 10 may select, following step S10, the non-test signal as a signal to be input into the A/D converter 14. [0043] As described above, the signal processing device 10 determines, for each bit included in the digital signal output from the A/D converter 14, whether a value of the bit switches after a level of the analog test signal switches. This configuration enables detection of occurrence of a failure in which a bit value of the A/D converter 14 is fixed without comparing an input value and an output value of the A/D converter 14, thereby enabling easily detection of a failure in which the value of the bit is fixed. [0044] Furthermore, the determiner 15 uses a first latch array to which an AND operation is performed and a second latch array to which an OR operation is performed as a flag indicating whether each bit is fixed. A value of the flag differs depending on whether the bit value is switched or the bit value is fixed. Thus, the signal processing device 10 outputs an error signal only when the value of the bit is fixed. Therefore, a failure in which a bit value is fixed leads to an output of an error signal regardless of

whether an actual output value of the A/D converter 14 is normal or not. Such
configuration enables improvement of detection accuracy of a failure in which a bit value
is fixed.
[0045] Furthermore, the storage 11 stores predetermined test bit patterns, and the
test signal supplier 12 generates analog test signals, each having a level corresponding to
the corresponding test bit pattern. Such configuration enables, merely by storing in the
storage 11 appropriate test bit patterns in advance, generation of appropriate analog test
signals, thereby enabling performance of the test processing.
[0046] Various techniques may be employed for storing the pattern table 111 in the
storage 11. For example, a pre-designed analog circuit may serve as the storage 11.
Achieving the function of the storage 11 with the analog circuit is relatively easy
particularly when the width of the test bit pattern is small or the number of the test bit
patterns is small. Such configuration enables saving capacity of storage elements
included in the signal processing device 10 or omission of the storage elements.
[0047] Furthermore, the pattern table 111 is not limited to the example shown in
FIG. 2. For example, employing pattern tables 111 shown in FIGS. 5A, 5B, and 5C can
also achieve performance of the test operation of the A/D converter 14.
[0048] The pattern table 111 of FIG. 5A includes two test bit patterns similarly to
the example of pattern table of FIG. 2. The bit values of these test bit patterns are
complementary to each other.
[0049] The pattern table 111 of FIG. 5B includes three test bit patterns. As shown
in FIG. 5B, a pattern table 111 including three or more test bit patterns is to include test
bit patterns that cause the value of each bit to be tested to become both zero and 1. The
same applies to a pattern table 111 that includes two test bit patterns, and in this case the
bit values of the two test bit patterns are to be complementary to each other as described
above. Although FIG. 5B shows an example of the pattern table 111 that is used when
the A/D converter 14 outputs an 8-bit digital signal, such a pattern table 111 is applicable

to other cases regardless of the number of bits included in the digital signal. [0050] Although the test bit patterns shown in FIGS. 2, 5A, and 5B are test bit patterns for testing all bits of the digital data item output from the A/D converter 14, the bits to be tested may be limited to certain bits of the digital data item output from the A/D converter 14, such as limited to the lower 8 bits. In such a case, the pattern table 111 may store two test bit patterns whose bit patterns are complementary to each other only at the lower 8 bits as shown in FIG. 5C. In this case, regarding the flag, simple bit-wise evaluation of the flag to be tested is sufficient. [0051] Embodiment 2
Next, Embodiment 2 is described with focus on differences from the above-described Embodiment 1. Components having the same or corresponding configurations as those in Embodiment 1 are denoted by the same reference numerals. Although a case of directly using test bit patterns stored in the storage 11 for a test operation is described in Embodiment 1, in the present embodiment, a plurality of test bit patterns is obtained by performing arithmetic processing of a plurality of digital data items to generate analog test signals.
[0052] In the present embodiment, the storage 11 stores a plurality of digital data items 112 as illustrated in FIG. 6. The digital data items 112 are equal to, for example, the test bit patterns included in the pattern table 111 according to Embodiment 1 (refer to FIG. 2).
[0053] The test signal supplier 12 includes an addition module 122. The addition module 122 includes an adder for adding a particular digital value. The addition module 122 reads the digital data item 112 from the storage 11 and adds an offset value to a value indicated by the digital data item 112. The offset value may be a value which is predetermined and stored in an auxiliary storage or a fixed value of the design of the adder circuit. Then, the addition module 122 outputs to the test signal generation module 121 a test bit pattern indicating a sum obtained by the addition of the offset.

The test signal generation module 121 generates an analog test signal based on the test bit pattern output from the addition module 122. Although not limiting the present disclosure, the addition module 122 functions as the addition means in the claims. [0054] Next, test processing performed by the signal processing device 10 is described with reference to FIG. 7. As illustrated in FIG. 7, test processing according to the present embodiment includes the processes similar to those in steps S1–S2 according to Embodiment 1.
[0055] Following step S2, the addition module 122 reads a first digital data item 112 from the storage 11 (step S21). When the plurality of digital data items 112 is equal to the test bit patterns shown in FIG. 2, the first digital data item 112 is equal to the first test bit pattern of FIG. 2. However, the plurality of digital data items 112 may be read in any order.
[0056] Next, the test signal supplier 12 supplies an analog test signal having a level corresponding to the test bit pattern obtained by adding the offset value to the read digital data item 112 (step S22). Specifically, the test signal generation module 121 generates, by performing a D/A conversion, an analog signal that causes the A/D converter 14 to output a digital signal equal to the test bit pattern output from the addition module 122. If the offset value is set to zero, the test bit pattern is equal to the read digital data item 112.
[0057] Next, the signal processing device 10 performs step S5 that is similar to that of Embodiment 1. Following step S5, the signal processing device 10 determines whether the current digital data item 112 is the last digital data item 112 stored in the storage 11 (step S23).
[0058] When the determination in step S23 is negative (No in step S23), the addition module 122 generates a new test bit pattern by reading the next digital data item 112 and adding an offset value (step S24). This offset value is the same as the offset value used in step S22 following step S21.

[0059] Following step S24, the signal processing device 10 repeats the processes in and after step S22. Thus, each time the offset value is added to the digital data item 112 to generate a test bit pattern, an analog test signal having a level corresponding to the test bit pattern is generated.
[0060] When the determination in step S23 is positive (Yes in step S23), the signal processing device 10 performs processes similar to those in steps S8–S10 of Embodiment 1.
[0061] As described above, the test signal supplier 12 of the signal processing device 10 includes the addition module 122, and analog test signals corresponding to the test bit patterns obtained by the addition module 122 adding a fixed offset value to different digital data items 112 are generated. Such configuration enables, merely by appropriately setting the offset value, changing between various types of sets of test bit patterns used in performing the test operation. For example, when the plurality of the digital data items 112 is equal to the test bit patterns shown in FIG. 5C, changing the offset value is sufficient for changing bits to be tested. Similarly, when the plurality of digital data items 112 is equal to the test bit patterns shown in FIG. 2, changing the offset value is sufficient for changing bits to be tested to obtain, for example, test bit patterns equal to the test bit patterns shown in FIG. 5C. [0062] Embodiment 3
Next, Embodiment 3 is described with focus on differences from the above-described Embodiment 2. Components having the same or corresponding configurations as those in Embodiment 2 are denoted by the same reference numerals. As illustrated in FIG. 8, a signal processing device 10 according to the present embodiment includes an adjuster 18, which differentiates the present embodiment from Embodiment 2.
[0063] Embodiment 2 described above is based on the premise that the A/D converter 14 has constant conversion characteristics. However, even if a level of an

analog signal supplied to the A/D converter 14 is constant, a value of the digital signal output from the A/D converter 14 may actually change due to various factors such as temperature drift. When such a change occurs, appropriately detecting a failure in which a bit value is fixed may be difficult. The signal processing device 10 according to the present embodiment compensates for the change described above by using the adjuster 18, and causes the A/D converter 14 to output a digital signal appropriate for the operation test. The signal processing device 10 according to the present embodiment is described below.
[0064] The function of the adjuster 18 is achieved by an MPU. The adjuster 18 adjusts the offset value such that a difference between a value indicated by the test bit pattern output from the addition module 122 and a value of the digital signal output from the A/D converter 14 becomes 0. Specifically, the adjuster 18 compares a test bit pattern after addition of the offset value with a value of a digital signal obtained through conversion of an analog test signal corresponding to the test bit pattern and output by the A/D converter 14. Then, the adjuster 18 corrects the offset value based on the comparison such that the difference becomes 0, thereby causing the A/D converter 14 to output a digital signal equal to the original test bit pattern. Without particular limitation, the adjuster 18 functions as the adjusting means in the claims.
[0065] Next, test processing performed by the signal processing device 10 is described with reference to FIG. 9. As illustrated in FIG. 9, test processing according to the present embodiment includes processes similar to those in steps S1–S2 and S21–S22 according to Embodiment 2.
[0066] Following step S22, the signal processing device 10 determines whether a difference between a current test bit pattern and a value of digital signal output from the A/D converter 14 is equal to or greater than a threshold value (step S31). Specifically, the adjuster 18 determines whether a difference between a value indicated by a test bit pattern output from the addition module 122 and a value of a digital signal that is

obtained by conversion of an analog test signal generated based on the test bit pattern and
is output by the A/D converter 14 is equal to or greater than a predetermined threshold
value. The threshold value may be zero or a non-zero value.
[0067] Upon determination that the difference is not equal to or greater than the
threshold value (No in step S31), processing by the signal processing device 10 shifts to
step S5. On the other hand, upon determination that the difference is equal to or greater
than the threshold value (Yes in step S31), the signal processing device 10 adjusts the
offset value to reduce the difference (step S32). Specifically, the adjuster 18 corrects the
offset value by reducing, from the offset value, a difference obtained by reducing, from
the value of the digital signal output from the A/D converter 14, the value of the test bit
pattern output from the addition module 122.
[0068] Then, the signal processing device 10 performs the processing in and after
step S5 of Embodiment 2.
[0069] As described above, the signal processing device 10 includes the adjuster 18
that adjusts the offset value. Adjustment of the offset value performed by the adjuster
18 causes the A/D converter 14 to output a digital signal appropriate for the test, thereby
enabling the signal processing device 10 to accurately diagnose whether bit values are
fixed.
[0070] Embodiment 4
Next, Embodiment 4 is described with focus on differences from the above-described Embodiment 1. Components having the same or corresponding configurations as those in Embodiment 1 are denoted by the same reference numerals. As illustrated in FIG. 10, a signal processing device 10 according to the present embodiment includes a timer 19 for performing regular test processing, which differentiates the present embodiment from Embodiment 1.
[0071] In Embodiment 1 described above, to perform the operation test of the A/D converter 14, an analog test signal different from the non-test signal input from the input

terminal 101 of the signal processing device 10 is supplied to the A/D converter 14, and thus, the signal processing device 10 cannot realize its intrinsic performance. However, the operation test need not be performed when switching of a bit value of a digital signal output from the A/D converter 14 can be detected in a state where the non-test signal is supplied. An example of omitting regular test processing in such a case is described with reference to FIGS. 10 and 11.
[0072] The timer 19 includes a crystal oscillator or an oscillator circuit. The timer 19 outputs, to the test signal generation module 121 at a predetermined cycle, a trigger signal indicating a start time of the test. The cycle is, for example, 8 hours, 24 hours or one week. However, another cycle may be appropriately employed. [0073] Next, operation test processing performed by the signal processing device 10 is described with reference to FIG. 11. The operation test processing may start upon power up of the signal processing device 10, or may start upon an instruction by a user of the signal processing device 10.
[0074] In the operation test processing, the signal processing device 10 selects the non-test signal as a signal to be input into the A/D converter 14 (step S41). Next, the signal processing device 10 performs a flag initialization process (step S42). The initialization process is equivalent to the initialization process in step S2 illustrated in FIG. 3 of Embodiment 1.
[0075] Next, the signal processing device 10 updates the flag in accordance with a bit value of a digital signal that is output from the A/D converter 14 so as to correspond to the non-test signal (step S43). Specifically, the determiner 15 updates values of the two latch arrays using a value of the digital signal obtained through conversion of the non-test signal and output by the A/D converter 14. More specifically, the determiner 15 updates a value of the first latch array using a result of an AND operation between a value output from the A/D converter 14 and the value of the first latch array, and updates a value of the second latch array using a result of an OR operation between the value output from the

A/D converter 14 and the value of the second latch array.
[0076] Next, the signal processing device 10 determines whether the current time is
the start time of the test processing (step S44). Specifically, the test signal supplier 12
determines whether the timer 19 has output the trigger signal.
[0077] Upon determination that the current time is not the start time of the test
processing (No in step S44), the signal processing device 10 repeats the performance of
the processes in and after step S43. Thus, the flag is repeatedly updated using the digital
signal that is output from the A/D converter 14 based on the non-test signal. Normally
the level of the non-test signal changes from moment to moment, and thus the flag is to
be updated based on a plurality of the non-test signals each having a different level.
[0078] On the other hand, upon determination that the current time is the start time
of the test processing (Yes in step S44), the signal processing device 10 determines, for
each bit to be tested, whether a value of the bit differs before versus after the level of the
non-test signal changes (step S45). In other words, the signal processing device 10
determines, for each bit to be tested, whether a value of the bit becomes both 1 and zero.
Specifically, the determiner 15 determines, by determining whether the value of the first
latch array is "0000h" and the value of the second latch array is "FFFFh" as shown in FIG.
4B, whether a value of each bit to be tested of the bits included in the digital signal output
from the A/D converter 14 switches.
[0079] When the determination in step S45 is positive (Yes in step S45), processing
by the signal processing device 10 shifts to step S42 without the performance of the test
processing of step S46. Thus, an operation test using the non-test signal is repeatedly
performed.
[0080] On the other hand, when the determination in step S45 is negative (No in
step S45), the signal processing device 10 performs the test processing (step S46). The
test processing is equal to the series of processing illustrated in FIG. 3.
[0081] Next, the signal processing device 10 determines whether an error signal is

output in the test processing of step S46 (step S47). Upon determination that an error signal is not output (No in step S47), the signal processing device 10 repeats the processing in and after step S42. Upon determination that an error signal is output (Yes in step S47), the signal processing device 10 ends the operation test processing. [0082] As described above, the test signal supplier 12 periodically generates an analog test signal and supplies the analog test signal to the A/D converter 14. Thus, the test processing is performed periodically. Therefore, detection of a failure in a relatively short time can be achieved when the A/D converter 14 fails.
[0083] Furthermore, the determiner 15 determines whether values of bits included in the digital signal obtained by conversion of the non-test signal and output by the A/D converter 14 switch, and the test signal supplier 12 omits generation of the next analog test signal when a determination is made that a value of the bit, based on the non-test signal, is switched. Such configuration enables detection of a failure of the A/D converter 14 based on the non-test signal, and enables reduction of load applied to the signal processing device 10 by omitting performance of the test processing. [0084] Embodiment 5
Next, Embodiment 5 is described with focus on differences from the above-described Embodiment 4. Components having the same or corresponding configurations as those in Embodiment 4 are denoted by same reference numerals. Further, since the test processing of Embodiment 4 is equivalent to that of Embodiment 1, the same reference numerals as in Embodiment 1 are used regarding the test processing. [0085] In Embodiment 4 described above, analog test signals each having a level corresponding to the corresponding test bit pattern of the plurality of test bit patterns are generated in order similarly to Embodiment 1. However, when switching of values of certain bits of the bits to be tested can be detected in a state where the non-test signal is supplied to the A/D converter 14, there is no need to generate analog test signals using test bit patterns for switching the values of the certain bits. Thus, an intensive test for

one or more bits whose changes in values cannot be detected based on the non-test signal may be performed. Such test processing is described below.
[0086] As illustrated in FIG. 12, a process similar to the process in step S1 of Embodiment 1 is performed in test processing of the present embodiment. Next, the signal processing device 10 refers to the flag (step S51). Specifically, the test signal generation module 121 refers to values of the first latch array and the second latch array. [0087] Next, the signal processing device 10, based on the non-test signal, selects a first test bit pattern corresponding to a value that is not output from the A/D converter 14 (step S52). Specifically, the test signal generation module 121 extracts one or more test bit patterns to be tested from the pattern table 111 with reference to values of the first latch array and the second latch array, and selects the first test bit pattern of the extracted test bit patterns.
[0088] Here, switching of a value is detected regarding bits in which the corresponding value of the first latch array changes from initial value 1 to zero and the corresponding value of the second latch array changes from initial value zero to 1. Thus, test bit patterns that are to be tested are test bit patterns for testing switching of bits other than the bits whose change in value are already detected. In other words, the test bit patterns to be tested are obtained by excluding test bit patterns for testing the previously diagnosed bits from the pattern table 111. For example, when the lower 2 bits are diagnosed in employing the pattern table of FIG. 5B, a testing using the first test bit pattern may be omitted. In this case, the test signal generation module 121 extracts the second bit pattern and the third bit pattern. Such extraction of test bit patterns is achieved by extracting test bit patterns that cause each of non-diagnosed bits to become a value of 1 and test bit patterns that cause each of the non-diagnosed bits to become a value of zero. Since the diagnosed bits need only become a value of 1 or zero, test bit patterns that cause outputs of values of both 1 and zero for the diagnosed bits are not adopted.

[0089] Following step S52, the signal processing device 10 performs steps similar to those in S4–S10 of Embodiment 1. The "last test bit pattern" in step S6 is the last test bit pattern of the test bit patterns extracted in step S52. The "next test bit pattern" in step S7 is the next bit pattern in sequential selection of the bit patterns extracted in step S52 in order from the bit pattern having the smallest number.
[0090] As described above, the determiner 15 determiners whether values of bits included in the digital signal output from the A/D converter 14 switch based on both an analog test signal and a non-test signal. Furthermore, the test signal supplier 12 generates analog test signals after excluding test bit patterns that are not required to be used due to the determination by the determiner 15 based on the non-test signal. Thus, when the non-test signal includes a value corresponding to a test bit pattern of the pattern table, the test signal supplier 12 omits generation of an analog test signal based on the test bit pattern. In other words, the test signal supplier 12 omits the supplying of an analog test signal corresponding to a test bit pattern of a plurality of test bit patterns when switching of values of all bits to be tested by the test bit pattern can be detected based on a determination using a non-test signal, thereby enabling reduction of a time for performing the test processing.
[0091] In the present embodiment, an extraction of some of the test bit patterns from the pattern table 111 is achieved by referring to a flag. However, such an extraction of certain test bit patterns from the pattern table 111 may be achieved by, for example, recording a non-test signal and excluding a test bit pattern corresponding to the recorded non-test signal. [0092] Embodiment 6
Next, Embodiment 6 is described with focus on differences from the above-described Embodiment 1. Components having the same or corresponding configurations as those in Embodiment 1 are denoted by the same reference numerals. As illustrated in FIG. 13, a signal processing device 10 according to the present

embodiment differs from Embodiment 1 by including two A/D converters.
[0093] In Embodiment 1 described above, one test circuit including the test signal
supplier 12 and the determiner 15 is arranged for one A/D converter. However, a test
circuit provided for collective use by a plurality of the A/D converters may be arranged to
efficiently perform the operation test with a compact configuration. An example of
arranging one test circuit for two A/D converters is described below.
[0094] The signal processing device 10 includes an input terminal 103 to which a
signal is input from the exterior, an output terminal 104 for outputting a signal to the
exterior, and an A/D converter 142 that serves as an A/D conversion unit.
[0095] The input terminal 103 is equivalent to the input terminal 101, and the
output terminal 104 is equivalent to the output terminal 102. Thus, a 2-channel analog
signal is input into the signal processing device 10, and the signal processing device 10
outputs a 2-channel digital signal.
[0096] The selector 13 selects a signal to be input into the A/D converter 142 from
an analog test signal or a signal input from the input terminal 103, and supplies the
selected signal to the A/D converter 142.
[0097] The A/D converter 142 outputs a digital signal obtained by conversion of
the input signal to the output terminal 104 and the determiner 15. Test operations for
each of the A/D converters 14 and 142 may be performed separately. In such a case, the
selector 13 selects one of the A/D converter 14 and the A/D converter 142, and supplies
an analog test signal to the selected one. The test signal supplier 12 is to supply an
analog test signal to the A/D converter 14 and the A/D converter 142 by switching a
supply destination of the analog test signal between the A/D converter 14 and the A/D
converter 142. Thus, operation test of the A/D converter 142 is performed at a timing
different from a timing at which operation test of the A/D converter 14 is executed. On
the other hand, the test operations for each of the A/D converters 14 and 142 may be
performed at the same timing. In such a case, the determiner 15 performs the two tests

in parallel. In performing the two tests in parallel, the first latch array and the second
latch array are used for diagnosing an output from the A/D converter 14, and a third latch
array and a fourth latch array are used for diagnosis of an output from the A/D converter
142.
[0098] The outputter 16 has a configuration similar to that of Embodiment 1. The
outputter 16 according to the present embodiment may output information indicating
which of A/D converters 14 and 142 fails.
[0099] The signal processing device 10 includes the A/D converters 14 and 142 as
described above, and a determination is made as to whether values of bits included in a
digital signal output from these converters are fixed. Such configuration enables
detection of a failure regardless of which of the two A/D converters 14 and 142 fails.
[0100] Furthermore, although a case of arranging two A/D converters 14 and 142 is
described in the present embodiment, detection of a failure can be achieved in the same
manner as in the present embodiment even in a case of arranging three or more A/D
converters.
[0101] Embodiment 7
Next, Embodiment 7 is described with focus on differences from the above-described Embodiment 1. Components having the same or corresponding configurations as those in Embodiment 1 are denoted by the same reference numerals. A signal processing device 10 according to the present embodiment employs a pattern table 111 of FIG. 14, which differentiates the present embodiment from Embodiment 1. [0102] Above Embodiment 1 describes an example of testing whether switching of a bit value of a digital signal output from the A/D converter 14 occurs by testing each bit separately to detect a failure. However, failures of an A/D converter include an error in which a value of certain output bit changes in tandem with a change in values of bits adjoining the certain bit. Thus, a configuration that enables detection of such an error further improves detection accuracy of a failure of an A/D converter. Hereinafter an

example of detecting an error in which a value of a bit changes in tandem with a change in a value of another bit is specifically described.
[0103] As shown in FIG. 14, test bit patterns included in a pattern table 111 according to the present embodiment each include a bit having a value different from values of other bits of the corresponding bit pattern. In performing an operation test of the A/D converter 14 using the pattern table 111, the test signal supplier 12 generates analog test signals each corresponding to the corresponding test bit pattern in an order by which a position of a bit having a different value from those of the other bits shifts to the adjacent digit one by one. The example shown in FIG. 14 describes a case of generating analog test signals such that the digit of a bit that is the only bit having a value of 1 in the corresponding bit pattern shifts up to the adjacent digit one by one from the least significant bit, and then the digit of a bit that is the only bit having a value of zero in the corresponding bit pattern shifts up to the adjacent digit one by one from the least significant bit.
[0104] Next, test processing performed by the signal processing device 10 is described with reference to FIG. 15. The test processing includes processes similar to those in steps S1–S8 of FIG. 3 according to Embodiment 1. A flag used in the test processing includes, in addition to the first latch array and the second latch array, flag data indicating whether switching of values of certain bits affected by changes in values of the other bits occurs. The flag data may be implemented in hardware by a latch circuit or as a flag field in software.
[0105] In step S5, the signal processing device 10 updates a flag that includes flag data. Specifically, the determiner 15 determines, every time step S5 is performed, whether a test bit pattern selected from the pattern table 111 is equal to a digital signal output from the A/D converter 14. Then, when these values are different from each other, the determiner 15 updates the flag data by adding, as data indicating an error in which a value of a bit changes in tandem with a change in a value of another bit, data

indicating a position of a bit of the selected pattern table 111 that is the only digit having a value of 1 or zero among the test bit pattern selected from the pattern table 111 and a position of a bit having the same value as that of the only digit having a value of 1 or zero of the selected test bit pattern.
[0106] When the determination in step S8 is positive (Yes in step S8), the signal processing device 10 determines whether a change in a value of a bit in tandem with a change in a value of another bit occurs (step S71). Specifically, the determiner 15 refers to the flag data and determines whether the flag data includes data indicating an error in which a value of a bit changes in tandem with a change in a value of another bit. [0107] Upon determination that a change in a value of a bit in tandem with a change in a value of another bit does not occur (No in step S71), processing by the signal processing device 10 shifts to step S9. On the other hand, upon determination that a change in a value of a bit in tandem with a change in a value of another bit occurs (Yes in step S71), the signal processing device 10 outputs an error signal (step S10). Information output in step S10 following a positive determination in step S71 includes information related to an error in which a value of a bit changes in tandem with a change in a value of another bit. The information related to the error may include information indicating occurrence of the error and a position of a bit that changes in tandem with a change in a value of another bit.
[0108] As described above, the signal processing device 10 enables detection of an error in which a value of certain bit of bits included in a digital signal output from the A/D converter 14 change in tandem with a change in a value of another bit, in addition to detection of a failure in certain bits are fixed. Such an error may be caused by, for example, crosstalk noise.
[0109] For example, a digital signal output from the A/D converter 14 may malfunction such that a value of the second-least significant bit always becomes the same as a value of the least significant bit. In employing the pattern table 111 of FIG. 2 when

such an error occurs, selecting the first test bit pattern leads to an output of a digital signal having a value of "11...11" from the A/D converter 14 and selecting the second test bit pattern leads to an output of a digital signal having a value of "00...00" from the A/D converter 14. Thus, detection of an error in which a value of a bit changes in tandem with a change in a value of another bit cannot be achieved.
[0110] On the other hand, employing the pattern table 111 according to the present embodiment enables detection of an error in which a value of certain bit changes in tandem with a change in values of bits adjoining the certain bit, in addition to detection of a failure in which certain bits are fixed. This enables improvement of the rate of detection of a failure that occurs in the A/D converter 14.
[0111] Furthermore, although the present embodiment describes a case of generating analog test signals such that a position of a bit that is the only bit having a value of zero or 1 in the corresponding bit pattern shifts up to the adjacent digit one by one, analog test signals may be generated, for example, such that a position of a bit that is the only bit having a value of zero or 1 in the corresponding bit pattern shifts down to the adjacent digit one by one. That is to say, the test signal supplier 12 need only supply analog test signals to the A/D converter 14 such that a position of a bit that is the only bit having a value of 1 or zero in the corresponding test bit pattern shifts between consecutive bit patterns one by one. [0112] Embodiment 8
Next, Embodiment 8 is described with focus on differences from the above-described Embodiment 1. The same or corresponding configurations as those in Embodiment 1 are denoted by the same reference numerals. As illustrated in FIG. 16, a signal processing device 30 according to the present embodiment includes a D/A converter and performs an operation test of the D/A converter, which differentiates the present embodiment from the signal processing device 10 according to Embodiment 1. [0113] Embodiment 1 described above enables detection of a failure in which

certain values of bits included in a digital signal output from an A/D converter are fixed. On the other hand, a D/A converter may have a failure in which changes in values of bits included in a digital signal input into the D/A converter do not affect an output value since an input value is fixed to 1 or zero and the digital signal is not recognized correctly. An example of detecting of a failure in which the value of the bit included in the digital signal input into the D/A converter is fixed is described below.
[0114] The signal processing device 30 includes a D/A converter that converts a digital signal into an analog signal and outputs the analog signal, which provides a function for outputting to the exterior an analog signal obtained by converting, by the D/A converter, a digital signal input from the exterior. Further, the signal processing device 30 performs an operation test of the D/A converter by monitoring a value output from the D/A converter after supplying a test signal to the D/A converter, and thus has a function for accurately detecting a failure of the D/A converter when the D/A converter fails.
[0115] The signal processing device 30 includes an input terminal 301 into which a digital signal is input from the exterior, an output terminal 302 for outputting an analog signal to the exterior, a storage 31 that stores various data, a test signal supplier 32 that generates a digital test signal used for testing operation of the D/A converter 34 and supplies the digital test signal to the D/A converter 34, a selector 33 that selects a signal input into the D/A converter 34, the D/A converter 34 that serves as an D/A converter, an A/D converter 35 that performs A/D conversion on an analog signal output from the D/A converter 34, a determiner 36 that determines whether the D/A converter 34 fails, and an outputter 37 that outputs information indicating a failure of the D/A converter 34. Although not limiting the present disclosure, the D/A converter 34 functions as the D/A conversion means in the claims.
[0116] The input terminal 301 is a terminal for inputting values of bits of a 1 channel digital signal in parallel. The input terminal 301 is connected to, for example, a

sensor or a device that outputs a digital signal. For example, a 16-bit digital signal
indicating an integer that falls within the range from -32,768 to +32,767 is input into the
input terminal 301.
[0117] The output terminal 302 is a terminal for outputting a 1-channel analog
signal. An actuator or a device that utilizes signals output by the signal processing
device 30 connects to the output terminal 302. The output terminal 302 outputs, for
example, a direct current voltage that falls within a range from -10V to +10V as an
analog signal.
[0118] The storage 31 has a configuration similar to that of the storage 11 according
to Embodiment 1 and stores a pattern table 311 that is similar to the pattern table 111
according to Embodiment 1.
[0119] The test signal supplier 32 sequentially reads from the storage 31 the test bit
patterns of the pattern table 311 and outputs to the selector 33 the read test bit patterns as
digital test signals.
[0120] The selector 33 includes a switching device. The selector 33 selects a
signal to be input into the D/A converter 34 from a digital test signal or an analog signal
input from the input terminal 301, and supplies the selected signal to the D/A converter
34. A signal selected by the selector 33 as a signal different from a digital test signal is
appropriately expressed as a non-test signal.
[0121] The D/A converter 34 is a so-called D/A converter circuit. The D/A
converter 34 outputs to the output terminal 302 and the A/D converter 35 an analog
signal obtained by converting the supplied digital signal. The A/D converter 35 is a
so-called A/D converter circuit. The A/D converter 35 converts an analog signal output
from the D/A converter 34 into a digital signal, and outputs the digital signal to the
determiner 36.
[0122] The determiner 36 has the same configuration as that of the determiner 15
according to Embodiment 1, and the outputter 37 has the same configuration as that of

the outputter 16 according to Embodiment 1.
[0123] The determiner 36 includes a Micro Processer Unit (MPU), and has the same configuration as that of the determiner 15 according to Embodiment 1. Specifically, the determiner 36 determines whether values of bits, included in the digital signal that is obtained by conversion of the digital test signal by the D/A converter 34 and the A/D converter 35 and is output by the A/D converter 35, switch. More specifically, to determine whether a failure in which a value of a bit is fixed occurs, the determiner 36 determines, for each bit of a plurality of to-be-tested bits of the digital signal, whether a value of the bit differs before versus after the value of the digital test signal switches. Similarly to Embodiment 1, the determiner 36 updates a value of the first latch array using a result of an AND operation between a value output from the A/D converter 35 and the value of the first latch array, and updates a value of the second latch array using a result of an OR operation between the value output from the A/D converter 35 and the value of the second latch array, thereby enabling detection of the presence or absence of a failure.
[0124] The outputter 37 has the same configuration as that of the outputter 16 according to Embodiment 1. When the determiner 36 determines that a failure in which a value of a bit is fixed occurs, the outputter 16 outputs information indicating a failure of the D/A converter 34. This information may be data indicating details of the failure and may be output as an illumination of the LED or a warning sound of the buzzer. [0125] The controller 38 includes an MPU, a ROM, and a RAM. The controller 38 centrally controls each component of the signal processing device 30. [0126] As described above, the signal processing device 30 supplies a digital test signal to the D/A converter 34, and determines whether the D/A converter 34 correctly recognizes the digital test signal. Specifically, detection of a failure of the D/A converter 34 can be achieved by monitoring a value output from the A/D converter 35 and determining whether values of bits included in the signal input into and processed by

the D/A converter 34 switches.
[0127] Here, detection of a failure of the D/A converter 34 can be achieved when
the A/D converter 35 operates normally. However, when the A/D converter 35 fails,
distinguishing the failure of the A/D converter 35 from the failure of the D/A converter
34 is difficult. Thus, monitoring of an analog signal output from the D/A converter 34
and input into the A/D converter 35 may be performed to determine which of the D/A
converter 34 and the A/D converter 35 fails.
[0128] Although Embodiments 2–7 describe modified examples of detection of a
failure of an A/D converter according to Embodiment 1, the detection of a failure of a
D/A converter according to the present embodiment can be modified as described in
Embodiments 2–7. For example, in the case of modification as described in
Embodiment 3, an offset value may be corrected such that the difference between the test
bit pattern stored in the storage 11 and a value output from the A/D converter 35 becomes
small.
[0129] While embodiments according to the present disclosure are described above,
the present disclosure is not limited to the embodiments described above.
[0130] For example, although each of the signal processing devices 10 and 30
simply converts an input signal and outputs the converted signal in the above-described
embodiments, such configuration is not limiting. As illustrated in FIG. 17, the signal
processing device 10 may include, for example, a signal processor 191 that performs
signal processing on a signal input from the input terminal 101 and outputs a result of the
processing as a non-test signal to the selector 13, and a signal processor 192 that performs
signal processing on a signal output from the A/D converter 14 and outputs a result of the
processing to the output terminal 102. Either the signal processor 191 or the signal
processor 192 may be omitted from the signal processing device 10. Similarly, the
signal processing device 30 may include a signal processor.
[0131] Furthermore, as illustrated in FIG. 18, the signal processing device 10 may

include, instead of the input terminal 101 and the output terminal 102, a signal source that
generates a non-test signal and an outputter 194 that outputs information based on an
output from the A/D converter 14. Similarly, the signal processing device 30 may
include a signal source and an outputter that outputs information based on an output from
the D/A converter 34.
[0132] Furthermore, although embodiments described above describe cases in
which the width of the test bit patterns included in the pattern table 111 are equal to the
width of the bit of a digital signal output from the A/D converter 14, and also describe
cases in which the width of the test bit patterns included in the pattern table 311 are equal
to the width of the bit of a digital signal input into the D/A converter 34, another
configuration may be employed. The width of the test bit patterns stored in the storages
11 and 31 may be equal to the width of bits to be tested of a digital signal that is input or
output. For example, when the lower 8 bits are to be tested, the width of the test bit
patterns may be 8 bits.
[0133] Furthermore, dedicated hardware or an ordinary computer system can also
achieve the functions of the signal processing devices 10 and 30.
[0134] For example, distributing a program to be executed by the controllers 17 and
38 by storing the program in a computer-readable recording medium and installing the
program in a computer can achieve a device for performing the above-described
processing.
[0135] Furthermore, the program may be stored in a disk device of a server device
on a communication network such as the Internet, for example, superimposed on a carrier
wave, and downloaded to a computer.
[0136] Furthermore, starting and executing the program while transferring the
program via the communication network can also achieve the above-described
processing.
[0137] Further, the above-described processing can also be achieved by causing all

or part of the program to be executed on the server device, and executing the program while the computer transmits and receives information related to the processing through the communication network.
[0138] In the case where the functions described above are implemented by an Operating System (OS) or implemented by cooperation between the OS and an application, for example, distribution of only a portion other than the OS by storing the portion in a medium, or by downloaded to a computer, is permissible. [0139] The means for achieving the functions of the signal processing devices 10 and 30 is not limited to software, and dedicated hardware including circuits may achieve some or all of the functions.
[0140] The foregoing describes some example embodiments for explanatory purposes. Although the foregoing discussion has presented specific embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the broader spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. This detailed description, therefore, is not to be taken in a limiting sense, and the scope of the invention is defined only by the included claims, along with the full range of equivalents to which such claims are entitled.
Industrial Applicability [0141] The present disclosure is suitable for detection of a failure of a converter.
Reference Signs List
[0142] 10, 30 Signal processing device
11, 31 Storage 111, 311 Pattern table 112 Digital data item
12, 32 Test signal supplier 122 Addition module

121, 321 Test signal generation module
13, 33 Selector
14, 142, 35 A/D converter
15, 36 Determiner
16, 37 Outputter
17, 38 Controller

18 Adjuster
19 Timer
34 D/A converter
101 Input terminal
102 Output terminal
103 Input terminal
104 Output terminal
191, 192 Signal processor
193 Signal source
194 Outputter

301 Input terminal
302 Output terminal

We Claim:
1. A signal processing device comprising:
A/D conversion means for converting an analog signal into a digital signal and outputting the digital signal;
supplying means for supplying, to the A/D conversion means, an analog test signal corresponding to a test bit pattern;
determination means for determining, when a level of the analog test signal supplied to the A/D conversion means switches, whether a value of a bit to be tested of the digital signal output by the A/D conversion means switches after switching of the level of the analog test signal; and
output means for outputting a result of the determination by the determination means.
2. The signal processing device according to claim 1,
wherein the supplying means comprises:
storage means for storing a plurality of predetermined digital data items; and addition means for adding an offset value to the plurality of digital data
items stored in the storage means to obtain a plurality of the test bit patterns, and
wherein the supplying means supplies, to the A/D conversion means, a plurality of
the analog test signals each corresponding to the corresponding test bit pattern obtained
by the addition means.
3. The signal processing device according to claim 2, further comprising
adjusting means for adjusting the offset value such that a difference between the test bit
pattern output from the addition means and the digital signal output from the A/D
conversion means becomes small.

4. The signal processing device according to claim 1, wherein
the test bit pattern is a plurality of bit patterns,
each of the plurality of bit patterns includes one bit having a value different from values of other bits of the corresponding bit pattern, and
the supplying means supplies, to the A/D conversion means, a plurality of the analog test signals each corresponding to the corresponding test bit pattern such that a position of the one bit shifts between consecutive bit patterns one by one.
5. The signal processing device according to any one of claims 1 to 4, wherein the supplying means periodically supplies the analog test signal.
6. The signal processing device according to claim 5, wherein
the determination means determines whether a value of the bit to be tested of a digital signal obtained through conversion of a non-test signal and output by the A/D conversion means switches after changing of a level of the non-test signal, the non-test signal being different from the analog test signal, and
the supplying means omits next generation of the analog test signal when the determination means determines based on the non-test signal that the value of the bit to be tested switches.
7. The signal processing device according to any one of claims 1 to 4, wherein
the determination means determines whether a value of the bit to be tested of a
digital signal obtained through conversion of a non-test signal and output by the A/D conversion means switches after changing of a level of the non-test signal, the non-test signal being different from the analog test signal, and
the supplying means omits supplying of the analog test signal corresponding to one test bit pattern of the plurality of test bit patterns when switching of all bits to be tested by

the one test bit pattern is confirmed by determination based on the non-test signal.
8. The signal processing device according to any one of claims 1 to 7, further
comprising another A/D conversion means for converting an analog signal into a digital
signal and outputting the digital signal,
wherein the supplying means supplies the analog test signal to the A/D conversion means and the another A/D conversion means by switching a supply destination of the analog test signal between the A/D conversion means and the another A/D conversion means.
9. A signal processing device comprising:
D/A conversion means for converting a digital signal into an analog signal and outputting the analog signal;
A/D conversion means for converting the analog signal output from the D/A conversion means into a digital signal;
supplying means for supplying a digital test signal to the D/A conversion means while changing a value of the digital test signal;
determination means for determining whether a value of each bit of a plurality of bits to be tested of a digital signal switches after the supplying means switches a value of the digital test signal, the digital signal being obtained by conversion of the digital test signal through the D/A conversion means and the A/D conversion means and output by the A/D conversion means; and
output means for outputting a result of the determination by the determination means as a test result.
10. An operation test method for testing operation of A/D conversion means for
converting an analog signal into a digital signal and outputting the digital signal, the

method comprising the steps of:
supplying an analog test signal to the A/D conversion means while changing a level of the analog test signal; and
determining whether a value of each bit of a plurality of bits to be tested of a digital signal switches after the change in the level of the analog test signal, the digital signal being obtained through conversion of the analog test signal and output by the A/D conversion means.
11. An operation test method for testing operation of D/A conversion means for converting a digital signal into an analog signal and outputting the analog signal, the method comprising the steps of:
supplying a digital test signal to the D/A conversion means while changing a value of the digital test signal; and
determining whether a value of each bit of a plurality of bits to be tested of a digital signal switches after the change in the value of the digital test signal, the digital signal being output from A/D conversion means after the A/D conversion means converts an analog signal obtained through conversion of the digital test signal and output by the D/A conversion means into the digital signal.