[DESCRIPTION]
[Title of Invention]
SIGNAL PROCESSOR AND SIGNAL PROCESSING METHOD
[Technical Field]
[0001]
The present disclosure relates to a signal processor and a
\ signal processing method and in particular, to a signal
\ processor and a signal processing method which make it possible
to perform high-speed data transmission easily in a
semiconductor chip, for example.
[Background Art] i [0002]
There are a method of performing data transmission in parallel
and a method of performing data transmission in series as
examples of a method for data exchange between semiconductor
chips.
[0003]
In the case of performing data transmission in parallel, data
transmission can be performed at high speed compared with the
;
case of performing data transmission in series.
[0004] I In addition, when performing data transmission in parallel,
the data transmission can be performed at higher speed by
increasing the bus width.
[0005]
< 1
In the case of performing data transmission in parallel,
however, the number of wiring lines in a semiconductor chip
or the number of pins of a semiconductor chip is increased
compared with the case of performing data transmission in
series.
I [0006]
In addition, if the bus width is increased when performing data
transmission in parallel, it becomes difficult to adjust the
i
timing of transmission or reception of each bit of data j
transmitted in parallel (parallel data).
[0007]
As described above, since the number of wiring lines in a
semiconductor chip or the number of pins of a semiconductor
chip is increased when performing data transmission in parallel,
a method of performing data transmission in series is adopted
when there are restrictions on the number of wiring lines in
a semiconductor chip or the number of pins of a semiconductor
chip.
[0008]
Meanwhile, in the case of transmitting parallel data in series,
it is necessary to perform P/S (Parallel/Serial) conversion
for converting parallel data into serial data at the
i
. transmission side and to perform S/P (Serial/Parallel)
conversion for converting data transmitted in series (serial
i
data) into parallel data at the receiving side.
j
2
[0009]
As a semiconductor chip which performs P/S conversion and S/P
conversion, there is a semiconductor chip called a SERDES
(Serializer/De-serializer) (for example, refer to NPL 1).
[0010]
Fig. 1 is a block diagram showing an example of the
configuration of an SERDES in the related art. j
[0011]
In Fig. 1, the SERDES has a serializer 10 and a de-serializer
20.
[0012]
The serializer 10 has a bit converter 11, a P/S converter 12,
a driver 13, and a pad.
[0013]
For example, 8-bit parallel data is supplied from the
high-order application (not shown) to the bit converter 11.
[0014]
The bit converter 11 converts the 8-bit (width) parallel data
from the high-order application into 10-bit parallel data in
order to prevent 0 or 1 (low or high) from continuing for a
long time in serial data and supplies the 10-bit parallel data
]
to the P/S converter 12.
[0015]
j The P/S converter 12 converts the 10-bit parallel data from
the bit converter 11 into serial data and supplies the serial
i
3
I
; ;
'•
:
%
data to the driver 13.
[0016]
The driver 13 is driven according to the serial data from the
P/S converter 12 and outputs a signal according to the serial
data. j
[0017]
An output of the driver 13 is connected to a pad (electrode)
14, and the signal output from the driver 13 is output to the
outside of the SERDES through the pad 14 and a wiring line
provided in the pad 14.
[0018]
The de-serializer 20 has a pad 21, a receiver 22, an equalizer
23, a CDR (Clock and Data Recovery) 24, an S/P converter 25,
a word alignment section 26, and a bit converter 27.
[0019]
A signal of serial data output from another SERDES is supplied
to the receiver 22 through the pad 21, for example.
[0020]
The receiver 22 receives the signal supplied through the pad
21 and supplies the signal to the equalizer 23.
: [0021]
\ The equalizer 23 equalizes the signal from the receiver 22 and
: supplies the result to the CDR 24.
) [0022]
i
The CDR 24 generates a clock from the signal supplied from the
4
;
'••
equalizer 23 and outputs the serial data to the S/P converter j
25 according to the clock.
|
[0023] j
The S/P converter 25 converts the serial data from the CDR 24 j
into parallel data and supplies the parallel data to the word
alignment section 26.
[0024]
The word alignment section 2 6 performs word alignment of the
parallel data from the S/P converter 25 and supplies to the
bit converter 27 10-bit parallel data obtained as a result,
for example.
[0025]
The bit converter 27 converts the 10-bit parallel data from
the word alignment section 2 6 into 8-bit parallel data by
performing inverse conversion of the conversion of the bit
converter 11 and supplies the 8-bit parallel data to the
high-order application.
[0026]
In recent years, however, the amount of data treated in the
high-order application has increased, that is, the data
i
;
< transmission speed has increased.
[0027]
)
i j In order to transmit the data at high speed, it is necessary
\ to increase the operation speed of the SERDES.
j [0028]
1 5
*
However, if the operation speed of the SERDES is increased,
attenuation of a signal in wiring lines extending from the pads
14 and 21 to the outside of the SERDES becomes large and the
frequency band of a signal becomes wide. Accordingly, since
(impedance) matching becomes difficult, reflection or
radiation occurs easily.
[0029]
In addition, in order to compensate for the attenuation of a
signal or the like, it is necessary to provide the equalizer
23 in the SERDES.
[0030]
Here, if the attenuation of a signal or the like is not large,
it is not necessary to provide the equalizer 23 in the SERDES.
However, in order to increase the operation speed of the SERDES,
it is necessary to provide the equalizer 23 in the SERDES since
the attenuation of a signal or the like becomes large.
[0031]
In addition, in order to increase the operation speed of the
SERDES, it is necessary to increase the operation speed of the
P/S converter 12, the driver 13, the receiver 22, the CDR 24,
and the S/P converter 25 which are a block for processing of
serial data in the SERDES. In this case, however, power
consumption of the block for processing of serial data is
increased.
[0032]
6
Therefore, the increase in the operation speed of the SERDES
1 is restricted by electric power which can be supplied to the
SERDES, and increasing the speed further is difficult. !
[Citation List]
[Non Patent Literature]
[0033]
[NPL 1] "R. Palmer, J. Poulton, W. J. Dally, J. Eylesl, A.
M. Fullerl, T. Greer, M. Horowitz, M. Kellam, F. Quan, F.
Zarkeshvari, "A 14 mW 6.25 Gb/s Transceiver in 90 ran CMOS for
Serial Chip-to-Chip Communications", 2007 IEEE International
Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS,
ISSCC 2007"
[Summary of Invention]
[Technical Problem]
[0034]
•
As described above, performing high-rate data transmission
\ (high-speed data transmission) in the SERDES may be difficult
•
due to power consumption. Moreover, also in a semiconductor
•
chip other than the SERDES, performing high-speed data
;
• transmission may be similarly difficult due to power
• consumption.
j [0035]
5
; Thus, it is desirable to make it possible to perform high-speed
] data transmission easily.
[Solution to Problem]
7
-
!
[0036]
I A first embodiment of the present disclosure is directed to
a one-chip semiconductor chip in which a plurality of frequency
converters that perform frequency conversion of input signals
to output converted signals are formed. In the signal
processor, the plurality of frequency converters perform
frequency conversion into converted signals in different
frequency bands, and the converted signals output from the
plurality of frequency converters are combined to output a
composite signal.
[0037]
The first embodiment of the present disclosure is also directed
to a signal processing method including: performing frequency
conversion into converted signals in different frequency bands
by means of a plurality of frequency converters of a signal
processor, which is a one-chip semiconductor chip in which the
plurality of frequency converters that perform frequency
\ conversion of input signals to output converted signals are
formed; combining the converted signals output from the
plurality of frequency converters to output a composite signal.
: [0038]
According to the first embodiment described above, the
plurality of frequency converters of the signal processor,
which is a one-chip semiconductor chip in which the plurality
of frequency converters that perform frequency conversion of
8
• 1
i
j
i
input signals to output converted signals are formed, perform I
I frequency conversion into converted signals in different
frequency bands. Then, the converted signals output from the
plurality of frequency converters are combined to output a
composite signal.
[0039]
•
A second embodiment of the present disclosure is directed to
; a one-chip semiconductor chip in which a plurality of frequency
converters, which perform frequency conversion of converted
signals obtained by performing frequency conversion of input
signals to output the input signals, are formed. In the signal
processor, the plurality of frequency converters perform
frequency conversion of converted signals in different
5 frequency bands. To each of the plurality of frequency
'. converters, at least a converted signal in a frequency band
to be frequency-converted by the frequency converter, of a
I composite signal obtained by combining a plurality of converted
1 signals in different frequency bands, is distributed.
[0040]
The second embodiment of the present disclosure is also
directed to a signal processing method including: performing
frequency conversion of converted signals in different
frequency bands by means of a plurality of frequency converters
of a signal processor, which is a one-chip semiconductor chip
in which the plurality of frequency converters that perform
•
:
9
i
:
i
I
frequency conversion of converted signals obtained by 1
I performing frequency conversion of input signals to output the
j
input signals are formed; and distributing to each of the
plurality of frequency converters at least a converted signal
in a frequency band, which is to be frequency-converted by the
1 frequency converter, of a composite signal obtained by
j combining a plurality of converted signals in different
i frequency bands.
[0041]
According to the second embodiment described above, the
plurality of frequency converters of the signal processor,
which is a one-chip semiconductor chip in which a plurality
j
j of frequency converters that perform frequency conversion of
converted signals obtained by performing frequency conversion
of input signals to output the input signals are formed, perform
frequency conversion of converted signals in different
' frequency bands. In this case, to each of the plurality of
• frequency converters, at least a converted signal in a
frequency band, which is to be frequency-converted by the
I
i frequency converter, of the composite signal obtained by
combining the plurality of converted signals in different
frequency bands, is distributed.
[0042]
A third embodiment of the present disclosure is directed to
a one-chip semiconductor chip in which a plurality of first
10
frequency converters, which perform frequency conversion of
input signals to output converted signals, and a plurality of
second frequency converters, which perform frequency
conversion of the converted signals to output the input signals,
are formed. The plurality of first frequency converters
perform frequency conversion into converted signals in
different frequency bands, the converted signals output from
the plurality of first frequency converters are combined, and
a composite signal is output. The plurality of second
frequency converters perform frequency conversion of the
converted signals in different frequency bands. To each of
the plurality of frequency converters, at least a converted
signal in a frequency band to be frequency-converted by the
frequency converter, of a composite signal from another
semiconductor chip, is distributed.
[0043]
According to the third embodiment of the present disclosure,
\ the plurality of first frequency converters of the signal
processor, which is a one-chip semiconductor chip in which the
j plurality of first frequency converters that perform frequency
i
conversion of input signals to output converted signals and
the plurality of second frequency converters that perform
1
I frequency conversion of the converted signals to output the
= input signals are formed, perform frequency conversion into
converted signals in different frequency bands. Then, the
i
11
•
f
converted signals output from the plurality of first frequency
converters are combined to output a composite signal. On the
i
other hand, the plurality of second frequency converters
perform frequency conversion of the converted signals in
different frequency bands. To each of the plurality of
frequency converters, at least a converted signal in a
frequency band to be frequency-converted by the frequency
: converter, of the composite signal from another semiconductor
chip, is distributed.
[Advantageous Effects of Invention]
[0044]
According to the first to third embodiments of the present
disclosure, high-speed data transmission can be performed
, easily.
[Brief Description of Drawings]
[0045]
[Fig. 1]
": Fig. 1 is a block diagram showing the configuration of an
example of an SERDES in the related art.
[Fig. 2]
Fig. 2 is a block diagram showing the configuration of a signal
processor according to an embodiment of the present disclosure .
[Fig. 3]
; Fig. 3 is a block diagram showing examples of the configuration
of a transmitter 51 and a receiver 61.
; 12
[Fig. 4]
Fig. 4 is a circuit diagram showing an example of the
configuration of an RF amplifier which can be adopted as j
amplifiers 73 and 81.
[Fig. 5]
Fig. 5 is a view showing an amplitude characteristic (60 GHz
Gain) of a 60 G amplifier and the size (60 GHz Sll) of a
reflection coefficient Sll at the input terminal Tl side and
an amplitude characteristic (80 GHz Gain) of an 80 G amplifier
and the size (80 GHz Sll) of the reflection coefficient Sll
at the input terminal Tl side.
[Fig. 6]
Fig. 6 is a view showing a phase (60 GHz Sll) of the reflection
coefficient Sll at the input terminal Tl side of the 60 G
amplifier and a phase (60GHzS22) of the reflection coefficient
S22 at the output terminal T2 side and a phase (80 GHz Sll)
of the reflection coefficient Sll at the input terminal Tl side
i
i
of the 80 G amplifier and a phase (80 GHz S22) of the reflection
coefficient S22 at the output terminal T2 side.
: [Fig. 7]
i
> Fig. 7 is a smith chart showing each locus of the reflection
i coefficient Sll (60 GHz Amp Sll) and the reflection coefficient
S22 (60 GHz Amp S22) of the 60 G amplifier and each locus of
: the reflection coefficient Sll (80 GHz Amp Sll) and the
reflection coefficient S22 (80 GHz Amp S22) of the 80 G
13
amplifier.
J [Fig. 8]
Fig. 8 is a smith chart showing each locus of the reflection
coefficient Sll (60 GHz Amp Sll) and the reflection coefficient
S22 (60 GHz Amp S22) of the 60 G amplifier and each locus of
i the reflection coefficient Sll (80 GHz Amp Sll) and the
i
reflection coefficient S22 (80 GHz Amp S22) of the 80 G
amplifier.
[Fig. 9]
Fig. 9 is a circuit diagram showing an example of the
i
I configuration of a combiner 41 formed by only a connection point
which makes a connection between connection lines of outputs
of a 60 G transmission amplifier and an 80 G transmission
; amplifier.
I [Fig. 10]
Fig. 10 is a circuit diagram showing a circuit used in the
simulation for measuring parameters of the 60 G transmission
amplifier and the 80 G transmission amplifier, which is
performed for the combiner 41 formed by only a connection point
•; which makes a connection between the connection lines of the
outputs of the 60 G transmission amplifier and the 8 0 G
transmission amplifier.
[Fig. 11]
Fig. 11 is a view showing the amplitude characteristics of the
60 G transmission amplifier, the 80 G transmission amplifier,
•
14
•
and the combiner 41.
j [Fig. 12]
Fig. 12 is a view showing the phase characteristics of the 60
G transmission amplifier, the 80 G transmission amplifier, and
the combiner 41.
[Fig. 13]
Fig. 13 is a circuit diagram showing an example of the
i
configuration of a splitter 42 formed by only a connection point
: which makes a connection between connection lines of the inputs
of the 60 G receiving amplifier and the 80 G receiving
i amplifier.
i
] [Fig. 14]
j Fig. 14 is a circuit diagram showing a circuit used in the
: simulation for measuring parameters of the 60 G receiving
amplifier and the 80 G receiving amplifier, which is performed
\ for the splitter 42 formed by only a connection point which
makes a connection between the connection lines of the inputs
of the 60 G receiving amplifier and the 80 G receiving
amplifier.
; [Fig. 15]
Fig. 15 is a view showing the amplitude characteristics of the
60 G receiving amplifier, the 80 G receiving amplifier, and
the splitter 42.
[Fig. 16]
Fig. 16 is a view showing the phase characteristics of the 60
15
]
G receiving amplifier, the 80 G receiving amplifier, and the
I splitter 42.
[Description of Embodiments]
[0046]

! [0047]
Fig. 2 is a block diagram showing an example of the
configuration of a signal processor according to an embodiment
of the present disclosure.
[0048]
In Fig. 2, the signal processor is a one-chip semiconductor
chip which functions as an SERDES, for example.
[0049]
In addition, in Fig. 2, the same reference numerals are given
j to components corresponding to those in Fig. 1, and the
explanation will be appropriately omitted hereinbelow.
j [0050]
The signal processor shown in Fig. 2 includes a plurality of,
I for example, three SERDES sections 31i, 312, and 313, a combiner
j
1 41, and a splitter 42. These SERDES sections 31i to 313, the
i
{ combiner 41, and the splitter 42 are formed, for example, on
i
a CMOS (Complementary Metal Oxide Semiconductor) which is a
one-chip semiconductor chip.
[0051]
•
16
:
j
-'•.
I The SERDES section 31i has a serializer 50 and the de-serializer
i 60.
!
[0052]
The serializer 50 has a bit converter 11, a P/S converter 12,
and a transmitter 51.
[0053]
Accordingly, the serializer 50 is the same as the serializer
*
i 10 shown in Fig. 1 in that the bit converter 11 and the P/S
i
converter 12 are provided but is different from the serializer
] 10 shown in Fig. 1 in that the transmitter 51 is provided instead
of the driver 13 and the pad 14.
; [0054]
\ Serial data are supplied from the P/S converter 12 to the
; transmitter 51.
• [0055]
The transmitter 51 performs frequency conversion of the serial
5 data from the P/S converter 12, which is a baseband signal
:
;
(signal in a predetermined frequency band), and outputs a
converted signal (converted signal in a higher frequency band
than the predetermined frequency band) which is a signal in
a high frequency band.
;
;
[0056]
Accordingly, the transmitter 51 functions as a frequency
converter which performs frequency conversion of the baseband
signal into the converted signal which is a signal in a high
•
-.
1 frequency band.
1 [0057]
The converted signal output from the transmitter 51 is supplied
to a combiner 41 by cable line (wiring line).
[0058]
1 $
I The de-serializer 60 has a receiver 61, a CDR 24, an S/P
converter 25, a word alignment section 26, and a bit converter
27.
[0059]
j Accordingly, the de-serializer 60 is the same as the
de-serializer 20 shown in Fig. 1 in that the CDR 24, the S/P
converter 25, the word alignment section 26, and the bit
1 converter 27 are provided but is different from the
! de-serializer 20 shown in Fig. 1 in that the receiver 61 is
I provided instead of the receiver 22 and the equalizer 23.
I [0060]
1 At least a converted signal is supplied from the splitter 42
to the receiver 61.
[0061]
The receiver 61 performs frequency conversion of the converted
signal from the splitter 42 and outputs the serial data which
is a baseband signal.
: [0062]
"; Accordingly, the receiver 61 functions as a frequency converter
which performs frequency conversion of the converted signal,
I 18
w
i
I which is a signal in a high frequency band, into the baseband
I
', signal.
I [0063]
I The serial data output from the receiver 61 is supplied to the
1 CDR 24 and is processed in the same manner as in the case of
1 the de-serializer 20 shown in Fig. 1.
[0064]
, The SERDES sections 312 and 313 are formed similar to the SERDES
j section 31i.
1 [0065]
I
i However, in the SERDES section 3I2, a transmitter corresponding
to the transmitter 51 performs frequency conversion into a
"i
5.
1 converted signal in a different frequency band from those of
< the other SERDES sections 31i and 3I3.
[0066]
In addition, in the SERDES section 312, a receiver
" corresponding to the receiver 61 performs frequency conversion
into a converted signal in a different frequency band from those
of the other SERDES sections 31i and 3I3.
i [0067]
The same is true for the SERDES section 3I3.
[0068]
Hereinafter, the bit converter 11, the P/S converter 12, the
CDR 24, the S/P converter 25, the word alignment section 26,
the bit converter 27, the serializer 50, the transmitter 51,
19
:
:
the de-serializer 60, and the receiver 61 (blocks corresponding
1 to these) of the SERDES section 31i are appropriately expressed
as a bit converter Hi, a P/S converter 12if a CDR 24if an S/P
j converter 25i, a word alignment section 26i, a bit converter
1 27i, a serializer 50i, a transmitter 51i, a de-serializer 60i,
and a receiver 61i, respectively, using a subscript index i.
j [0069]
'. In addition, the center frequency of the converted signal
\ output from the transmitter 51i of the SERDES section 31i is
expressed as fsi, and the center frequency of the converted
j signal to be frequency-converted by the receiver 61i of the
i
j SERDES section 31± is expressed as fri.
[0070]
Frequencies fsi, fs2, and fs3 are different from each other,
: and frequencies fri, fr2, and fr3 are also different from each
other.
j [0071]
i
; In addition, the frequency fsi (here i = 1, 2, 3) and the
frequency fri- (here I' = 1, 2, 3) may be different or equal.
[0072]
When a composite signal to be adjusted is transmitted or
received through a common (the same) transmission path, it is
possible to perform transmission and reception of data
simultaneously in the signal processor shown in Fig. 2 if the
•
frequencies fsi and fri- are different for all combinations of
•
}
•
20
i
i and i'. However, if the frequencies fsi and fri- are equal
I for even one of the combinations of i and i', it is necessary
3 I to perform the transmission and reception of data in a
time-division manner (half-duplex communication) in the
signal processor shown in Fig. 2.
[0073]
Moreover, if frequencies corresponding to the frequencies fsi
and fri are expressed as frequencies fSi ' and fri ', respectively,
in another signal processor which transmits/receives data
to/from the signal processor shown in Fig. 2 and is configured
similar to the signal processor shown in Fig. 2, the frequencies
fsi and fri' match each other and the frequencies fri and fsi'
match each other.
[0074]
The combiner 41 combines the converted signals output from the
transmitters 51i to 5I3 of the SERDES sections 31i to 313 and
-, outputs a composite signal.
>.
1
i [0075]
Here, the combiner 41 may be formed by a BPF (Band Pass Filter)
(here, three BPFs) which is for restricting a frequency band
of a converted signal having the frequency fsi as its center
frequency, which is output from the transmitter 51i of the
SERDES section 31i, to a predetermined band width and a
; connection point which connects connection lines of outputs
of three BPFs that restrict the frequency bands of converted
I 21
-
1 signals output from the transmitters 51i to 5I3, for example.
| [0076]
Now, the BPF for restricting the frequency band of the converted
i
I signal having the frequency fsi as its center frequency which
is output from the transmitter 51i, among the three BPFs
provided in the combiner 41, is expressed as BPF#i. Then, in
the combiner 41 formed by the three BPF#1, BPF#2, and BPF#3
and a connection point which connects connection lines of the
j outputs of the three BPF#1 to BPF#3, the frequency band of the
t
! converted signal output from the transmitter 51i is restricted
I
1 bytheBPF#i. Then, the converted signals output from the three
I
5 BPF#1 to BPF#3 are combined at the connection point which
I connects the connection lines of the outputs of the three BPF#1
3
1 to BPF#3.
1
\ [0077]
In addition, the combiner 41 may be formed without a BPF, for
example. That is, the combiner 41 may be formed by only the
connection point of outputs of the transmitters 51i to 513.
5
Detailed explanation thereof will be given later.
[0078]
A composite signal output from the combiner 41, that is, a
signal obtained by frequency multiplexing of the converted
; signals output from the transmitters 51i to 513 is transmitted
, to another signal processor by cable or wirelessly through a
pad (not shown).
22
.
[0079] 1
"j The composite signal transmitted by cable or wirelessly is
I
supplied from another signal processor to the splitter 42
through a pad (not shown).
[0080]
The splitter 42 distributes to each of the receivers 61i to
• 6I3 of the SERDES sections 31i to 3I3 at least a converted signal
in a frequency band which is included in the composite signal
supplied thereto and is to be frequency-converted by the
I receiver 61i, that is, a converted signal having the frequency
I
fri as its center frequency.
I [0081]
Here, the splitter 42 may be formed by a BPF (Band Pass Filter)
(here, three BPFs) for extracting a converted signal, which
has the frequency fri as its center frequency and is to be
; frequency-converted by the receiver 61i of the SERDES section
.] 31i, from the composite signal and a connection point which
makes a connection of connection lines of inputs of the three
-
BPFs, for example.
I [0082]
Now, a BPF for extracting a converted signal having the
1 frequency fn as its center frequency among the three BPFs
"i
provided in the splitter 42 is expressed as BPF'#i. Then, in
the splitter 42 formed by the three BPF'#1, BPF'#2, and BPF1 #3
and a connection point which connects connection lines of the
"
i
23
•
1
If
inputs of the three BPF'#1 to BPF'#3, the composite signal is
I supplied to each of the three BPF'#1 to BPF'#3 from the
J connection point which connects the connection lines of the
inputs of the three BPF'#1 to BPF'#3. Then, in the BPF'#i,
a converted signal having the frequency fri as its center
i
frequency is extracted and is then supplied (distributed) to
the receiver 61i.
j.
j [0083]
I In addition, the splitter 42 may be formed without a BPF, for
1 example. That is, the splitter 42 may be formed by only the
I connection point of inputs of the receivers 61i to 6I3.
j
\ Detailed explanation thereof will be given later.
I
j [0084]
j In the signal processor configured as described above, for
i
i
example, 8-bit parallel data is supplied from the high-order
•
application to each of the bit converters H i to II3.
[0085]
The bit converter Hi converts the 8-bit parallel data from
1 the high-order application into 10-bit parallel data and
j supplies the 10-bit parallel data to the P/S converter 12i. I [0086]
The P/S converter 12i converts the 10-bit parallel data from
the bit converter 11 into serial data and supplies the serial
data to the transmitter 51i.
[0087] • 24
9
1 The transmitter 51i performs frequency conversion of the serial
j data, which is a baseband signal from the P/S converter 12i,
i
J into a converted signal having the frequency fsi as its center
1 frequency and supplies the converted signal to the combiner
1 41 through a cable line.
J [0088]
I The combiner 41 combines the converted signals output from the
J transmitters 51i to 5I3 and outputs the composite signal.
j [0089]
1 The composite signal output from the combiner 41 is transmitted
I to another signal processor by cable or wirelessly.
j [0090]
1 On the other hand, the composite signal transmitted by cable
J or wirelessly is supplied from another signal processor to the
I splitter 42.
j [0091]
I The splitter 42 distributes at least a converted signal having
I the frequency fri as its center frequency, which is included
I in the composite signal supplied thereto, to the receiver 61i.
1 [0092]
I The receiver 61i performs frequency conversion of the converted
1 signal, which is included in the signal from the splitter 42
1 and has the frequency fri as its center frequency, into serial
I data, which is a baseband signal, and supplies the serial data
I to the S/P converter 25± through the CDR 24±.
: 25
•
:
•
I [0093]
\ The S/P converter 25± converts the serial data, which is
j
supplied through the CDR 24i, into 10-bit parallel data, and
supplies the 10-bit parallel data to the bit converter 27
through the word alignment section 2 6j..
1 [0094]
The bit converter 27 converts the 10-bit parallel data, which
is supplied through the word alignment section 26, into 8-bit
\ parallel data, and supplies the 8-bit parallel data to the
i
.
: high-order application.
[0095]
As described above, in the signal processor, serial data which
f
is a baseband signal is frequency-converted into converted
j signals in different frequency bands by the plurality of
J
j (three) transmitters 51i to 5I3, and the converted signals
output from the transmitters 51i to 5I3 are combined and the
I composite signal is output.
1
j [0096]
s In addition, at least a converted signal in a frequency band,
5
I which is to be frequency-converted by the receiver 61i and which
:
j is included in the composite signal transmitted from another
signal processor, is distributed to the receiver 61i, and the
1
I converted signal in a frequency band to be frequency-converted
j
j by the receiver 61i is frequency-converted into serial data,
1 I which is a baseband signal, by the receivers 6I1 to 6I3.
26
1 •*;
i
[0097]
1
i
\ Therefore, high-speed data transmission can be performed
i
J easily.
1 [0098]
1 That is, compared with the SERDES in Fig. 1, the signal
J processor shown in Fig. 2 has the plurality of (three) SERDES
sections 31i to 313 as blocks which perform the same P/S
conversion and S/P conversion as in the SERDES shown in Fig.
1. Accordingly, compared with the SERDES in Fig. 1, data can
' be processed three times without increasing the processing
speed of the P/S converter 12, the CDR 24, and the S/P converter
25 which are blocks for processing the serial data (accordingly,
without increasing the power consumption of each block which
i processes the serial data) . Simply, it is possible to process
data three times in the same period.
[0099]
In addition, high-speed data transmission can be performed as
in the signal processor shown in Fig. 2 simply by providing
the three serializers 10 and the three de-serializers 20 in
]
the SERDES shown in Fig. 1, for example.
I [0100]
' However, for example, when the three serializers 10 and the
three de-serializers 20 are provided in the SERDES shown in
Fig. 1, the number of pads 14 and 21 is increased. Accordingly,
it may be difficult to provide the three serializers 10 and
:
•_
: 27
!
!
3
' the three de-serializers 20 depending on the restrictions, such
as the number of wiring lines in a semiconductor chip as the
SERDES or the number of pins of a semiconductor chip.
[0101]
; In contrast, in the signal processor shown in Fig. 2, serial
1 data which is a baseband signal is frequency-converted into
converted signals in different frequency bands by the three
transmitters 51i to 5I3, the converted signals output from the
transmitters 51i to 5I3 are combined by the combiner 41, and
the composite signal is output.
[0102]
Accordingly, the number of pads for outputting the composite
signal is one no matter how many SERDES sections are provided.
j
That is, the number of pads is not increased.
[0103]
Moreover, in the signal processor shown in Fig. 2, the splitter
\ 42 distributes to the receiver 61i at least a converted signal
I
in a frequency band which is to be frequency-converted by the
.; receiver 61i and is included in a composite signal, which is
obtained by combining converted signals in different frequency
bands and is transmitted from another signal processor, and
each of the receivers 6I1 to 6I3 performs frequency conversion
of the converted signal in a frequency band, which is to be
J frequency-converted by the receiver 61i, into serial data which
is a baseband signal.
:
\ 28
.;
t
I
I [0104]
[ Accordingly, the number of pads for inputting (supplying) to
the splitter 42 the composite signal transmitted from another
signal processor is one no matter how many SERDES sections are
provided. That is, the number of pads is not increased.
[0105]
As described above, the number of pins of a semiconductor chip
1 which is the signal processor shown in Fig. 2 is not increased
1 no matter how many SERDES sections are provided.
1 [0106]
1 In addition, in the signal processor shown in Fig. 2, the serial
1 data which is a baseband signal is transmitted from each of
I the plurality of (three) transmitters 51i to 5I3 after being
1 frequency-converted into converted signals in different
1 frequency bands. Accordingly, compared with the case of
1
transmitting the serial data by increasing the operation speed
in the SERDES shown in Fig. 1, there is an advantage in that
'•
imperfections in transmission path characteristics (for
•
example, the presence of a frequency with large or small
attenuation in the transmission path) can be easily solved by
j adjusting the frequency band of a converted signal acquired
by frequency conversion, for example.
[0107]
Here, although the three SERDES sections 31i to 313 are provided
in the signal processor in Fig. 2, two SERDES sections or four
I 29
!
1
1
1
*
I or more SERDES sections may also be provided in the signal
i
\ processor.
l
[0108]
] In addition, transmission and reception of a composite signal
'• between the signal processor shown in Fig. 2 and another signal
processor may be performed either by cable or wirelessly. In
the case of wireless transmission and reception, separate
i antennas (an antenna for transmission and an antenna for
'•
: reception) may be used or one common antenna may be used for
j transmission and reception of a composite signal.
; [0109]
In addition, when transmission and reception of a composite
signal between the signal processor shown in Fig. 2 and another
i signal processor are performed wirelessly, not only the air
.
but also various kinds of waveguides, such as a dielectric
j waveguide, may be adopted as the wireless transmission path.
An example of the dielectric waveguide is disclosed in
JP-A-2010-103982.
[0110]
In addition, although both the serializer 50i and the
de-serializer 60i are provided in the SERDES section 31i in
Fig. 2, only the serializer 50i or the de-serializer 60i may
be provided in the SERDES section 31i when necessary.
[0111]
1 When only the serializer 50i is provided in the SERDES section
I
30
: 31i, the signal processor may be formed without the splitter
42. When only the de-serializer 60i is provided in the SERDES
section 31i, the signal processor may be formed without the
combiner 41.
[0112]

[0113]
Fig. 3 is a block diagram showing examples of the configuration
of the transmitter 51 and the receiver 61 shown in Fig. 2.
[0114]
The transmitter 51 and the receiver 61 perform frequency
conversion between a baseband signal and a signal in a
millimeter wave band, for example.
[0115]
In addition, the signal in a millimeter wave band is a signal
with a frequency of about 30 to 300 GHz, that is, a signal with
a wavelength of about 1 to 10 mm. Since the signal in a
millimeter wave band has a high frequency, high-speed data
transmission becomes possible. In addition, in the case of
wireless transmission and reception, an about 1 mm bonding wire
i
\ can be adopted as an antenna, for example.
j [0116]
: The transmitter 51 has an oscillator 71, a mixer 72, and
amplifier 73.
31
i
i
i
j
1
••A
-'•
I [0117]
I
j Hereinafter, the oscillator 71, the mixer 72, and amplifier
* 1 73 provided in the transmitter 51i are appropriately written
as an oscillator 71j., a mixer 72i, and an amplifier 73i,
respectively.
• [0118]
The oscillator 71 generates a carrier in a millimeter wave band,
for example, by oscillation and supplies it to the mixer 72.
[0119]
The center frequencies fsi to fs3 of the converted signals
output from the transmitters 51i to 513 correspond to
frequencies of carriers generated by the oscillators 71i to
7I3 provided in the transmitters 51i to 5I3, respectively.
[0120]
Therefore, the frequencies of the carriers generated by the
oscillators 71i to 7I3 are different.
[0121]
To the mixer 72, a carrier is supplied from the oscillator 71
and serial data which is a baseband signal is supplied from
the P/S converter 12 (Fig. 2).
[0122]
Here, assuming that the data rate of the serial data supplied
to the mixer 72 is about 2.5 to 5.0 Gbps, for example, it is
preferable to set the frequency of the carrier generated by
the oscillator 71 to 30 GHz or more, for example, in order that
32
interference between converted signals, which are obtained by 1
frequency conversion of such serial data in the transmitters I
51i to 513, can be reduced and each converted signal can be 1
separated from a composite signal obtained by combining the I
converted signals.
[0123]
The mixer 72 mixes the serial data and the carrier from the
oscillator 71 (multiplies the carrier from the oscillator 71
by the serial data) to modulate the carrier from the oscillator
71 according to the serial data and supplies to the amplifier
73 a modulated signal obtained as the result, that is, a
converted signal obtained by frequency conversion of the serial
data, which is a baseband signal, into an RF (Radio Frequency) |
signal in a frequency band corresponding to the carrier from !
the oscillator 71.
[0124]
The amplifier 73 amplifies the RF signal as a converted signal
from the mixer 72 and outputs the RF signal as a converted signal
after the amplification.
[0125]
The converted signal output from the amplifier 73 is supplied
to the combiner 41. The combiner 41 combines the RF signals
as converted signals output from the amplifier 73i to 733.
[0126]
On the other hand, the receiver 61 has an amplifier 81, an
33
i
1" oscillator 82, and a mixer 83.
[0127]
Hereinafter, the amplifier 81, the oscillator 82, and the mixer
83 provided in the receiver 61i are appropriately written as
an amplifier 81i, an oscillator 82i; and a mixer 83i,
respectively.
[0128]
At least an RF signal including a converted signal in a
frequency band, which is to be frequency-converted by the
i i
receiver 61i, of the composite signal transmitted from another
signal processor is supplied to the amplifier 81i.
[0129]
The amplifier 81 amplifies the RF signal supplied thereto and
supplies to the oscillator 82 and the mixer 83 an RF signal
which is obtained by the amplification and which is a converted
signal in a frequency band to be frequency-converted by the 1
receiver 61i. I
[0130] I
The oscillator 82 operates with the converted signal (RF |
signal) from the amplifier 81 as an input signal. The |
oscillator 82 generates by oscillation a reproduction carrier I,
synchronized with the converted signal (carrier) as an input I
signal, that is, a reproduction carrier corresponding to the I
carrier used for frequency conversion into the converted signal |
and supplies the reproduction carrier to the mixer 83. |
34 I
[0131]
The mixer 83 mixes the converted signal from the amplifier 81
1
and the reproduction carrier from the oscillator 82 (multiplies
the converted signal from the amplifier 81 by the reproduction
carrier from the oscillator 82) to demodulate the converted
signal (modulated signal) and supplies to the CDR 24 a modulated
signal obtained as the result, that is, serial data obtained
by frequency conversion of the converted signal into a baseband
signal (Fig. 2).
[0132]

[0133]
Fig. 4 is a circuit diagram showing an example of the
configuration of an RF amplifier which can be adopted as the
amplifiers 7 3 and 81 in Fig. 3. 1
[0134]
The amplifiers 73 and 81 can be similarly formed since they
are RF amplifiers which amplify an RF signal.
[0135]
In Fig. 4, one end of a capacitor CI is connected to an input
terminal Tl of an RF amplifier, and the other end of the
capacitor CI is connected to one end of a coil LI. The other
end of the coil LI is connected to a positive terminal of a
DC power supply Vccl whose negative terminal is grounded.
[0136]
35
1 A connection point between the capacitor CI and the coil Ll
[ is connected to a gate of a FET (MOS FET) #1 whose source is
i
grounded.
[0137]
A drain of the FET#1 is connected to a source of an FET (MOS
FET) #2, and a gate and a drain of the FET#2 are connected to
one end and the other end of a coil L2, respectively.
[0138]
In addition, substrates of the FET#1 and the FET#2 are grounded.
[0139]
A connection point between the gate of the FET#2 and the coil
L2 is connected to a positive terminal of a DC power supply 1
Vcc2 whose negative terminal is grounded. I
[0140] I
A connection point between the drain of the FET#2 and the coil I
L2 is connected to one end of a capacitor C2, and the other I
end of the capacitor C2 is connected to an output terminal T2 |
of the RF amplifier. I
[0141] I
The RF amplifier shown in Fig. 4 can be used in cascade I
connection. Accordingly, each of the amplifiers 73 and 81 may I
I be formed by only one RF amplifier shown in Fig. 4 or by cascade I
connection of a plurality of RF amplifiers shown in Fig. 4 which I
are necessary. f
[0142] I
j
36 I
J In addition, when the amplifier 7 3 or 81 is formed by only one
i
1 RF amplifier shown in Fig. 4, the other ends of resistors Rl
1
J and R2 each of which has grounded one end are connected to the
input terminal Tl and the output terminal T2, respectively.
[0143]
In addition, when the amplifier 73 or 81 is formed by cascade
\ connection of a plurality of RF amplifiers shown in Fig. 4,
the other ends of the resistors Rl and R2 each of which has
grounded one end are connected to the input terminal Tl of the
first RF amplifier and the output terminal T2 of the last RF
amplifier, respectively.
[0144]
Hereinafter, it is assumed that each of the amplifiers 73 and
81 is formed by only one RF amplifier shown in Fig. 4 for
convenience of explanation.
[0145]
Since the amplifier 73 or 81 amplifies an RF signal in a
millimeter wave band which is a high-frequency signal, an
inductance load may be used as an input-side or output-side
load of an RF amplifier as such an amplifier 73 or 81.
[0146]
In the millimeter wave band, a coil with small inductance can
be adopted as the inductance load, and such a coil can be easily
formed on the CMOS.
[0147]
37 I
I In the RF amplifier shown in Fig. 4, the coil LI is an inductance
t load at the input side and the coil L2 is an inductance load
at the output side.
[0148]
When the inductance load is adopted as an input-side load of
the' RF amplifier, the frequency characteristics at the input
side of the RF amplifier become band pass type characteristics,
such as a BPF. Accordingly, it is possible to separate a signal
in a part of the frequency band from RF signals input (supplied)
to the RF amplifier and to amplify the signal.
[0149]
In addition, when the inductance load is adopted as an
output-side load of the RF amplifier, the frequency
characteristics at the output side of the RF amplifier become
band pass type characteristics, such as a BPF. Accordingly, 1
it is possible to restrict the frequency band of the RF signal
output from the RF amplifier.
[0150]
As described above, the frequency characteristics at the input I
side or the output side become band pass type characteristics I
by adopting the RF amplifier, of which a load at the input side 1
or the output side is an inductance load, as the amplifier 73 I
or 81 shown in Fig. 3. For this reason, the combiner 41 or I
the splitter 42 can be simply formed by only the connection 1
point, which makes a connection between connection lines, 1
38 I
without a BPF as described above in Fig. 2.
1 [0151]
In addition, if an RF amplifier as the amplifier 7 3 of the
transmitter 51 connected to the combiner 41 is formed such that
at least the frequency characteristics at the output side of
the frequency characteristics at the input and output sides
become band pass type characteristics, the combiner 41 can be
formed without a BPF.
[0152]
Accordingly, as the input-side load in the RF amplifier as the
amplifier 73 of the transmitter 51 connected to the combiner
41, a load which is not an inductance load can be adopted, that
is, a resistor can be used instead of the coil LI.
[0153]
In addition, if an RF amplifier as the amplifier 81 of the
receiver 61 connected to the combiner 42 is formed such that
at least the frequency characteristics at the input side of
the frequency characteristics at the input and output sides
become band pass type characteristics, the splitter 42 can be
formed without a BPF.
[0154] I
Accordingly, as the output-side load in the RF amplifier as
the amplifier 81 of the receiver 61 connected to the splitter
42, a load which is not an inductance load can be adopted, that I
is, a resistor can be used instead of the coil L2. I
39 I
[0155]
In the RF amplifier as the amplifier 81 of the receiver 61,
however, it is preferable to adopt the inductance load as the
output-side load instead of a resistor when a gain equal to
| or larger than a predetermined value is necessary.
[0156]
Moreover, in the RF amplifier shown in Fig. 4, a transfer
coefficient S12 from the output terminal T2 to the input
terminal Tl among S parameters (scattering parameters) becomes
a small value.
[0157]

[0158]
Next, forming the combiner 41 and the splitter 42 by only the
connection point, which makes a connection between connection I
lines, without a BPF by adopting the RF amplifier in Fig. 4 1
as the amplifiers 73 and 81 in Fig. 3 will be described. 1
[0159] I
In addition, the following explanation will be given focusing I
on the two transmitters 51i and 512 of the three transmitters I
51i to 5I3 for convenience of explanation. 1
[0160] I
In addition, it is assumed that the transmitter 51i performs I
frequency conversion of a baseband signal into an RF signal 1
as a converted signal in a frequency band having a center I
40 I
j
frequency fsi of 60 GHz (hereinafter, also referred to as a
60 G band signal) and the transmitter 512 performs frequency
conversion of a baseband signal into an RF signal as a converted
signal in a frequency band having a center frequency fsi of
80 GHz (hereinafter, also referred to as an 80 G band signal)
I which is different from 60 GHz.
! [0161]
Similarly, also in the three receivers 61i to 6I3, the
explanation is given focusing on the two receivers 6I1 and 6I2.
It is assumed that the receiver 6I1 performs frequency
conversion of the 60 G band signal into a baseband signal and
the receiver 612 performs frequency conversion of the 80 G band
signal into a baseband signal.
[0162]
In this case, although the amplifier 73i of the transmitter
51i amplifies a 60 G band signal and the amplifier 732 of the §
transmitter 512 amplifies an 80 G band signal, the amplifier 1
73i of the transmitter 51i and the amplifier 732 of the I
transmitter 512 are different from an RF amplifier as the 1
amplifier 73i which amplifies a 60 G band signal and an RF 1
amplifier as the amplifier 732 which amplifies an 80 G band I
signal only in the inductances of the coils LI and L2. 1
[0163] I
That is, a coil with an inductance suitable for amplifying the I
60 G band signal is adopted as the coils Ll and L2 of the RF |
41 I
I ^m
j amplifier as the amplifier 73i which amplifies the 60 G band
signal, and a coil with an inductance suitable for amplifying
the 80 G band signal is adopted as the coils LI and L2 of the
RF amplifier as the amplifier 732 which amplifies the 80 G band
signal. I
i
[0164]
The same is true for the amplifier 81i of the receiver 611 and
the amplifier 8I2 of the receiver 6I2.
[0165]
Hereinafter, the RF amplifier as the amplifier 73i which
amplifies the 60 G band signal is also called a 60 G transmission
amplifier, and the RF amplifier as the amplifier 732 which
amplifies the 80 G band signal is also called an 80 G
transmission amplifier. I
[0166] j
Similarly, the RF amplifier as the amplifier 811 which j
amplifies the 60 G band signal is also called a 60 G receiving 1
amplifier, and the RF amplifier as the amplifier 8I2 which I
amplifies the 80 G band signal is also called an 80 G receiving 1
amplifier. I
[0167] 1
Moreover, hereafter, the 60 G transmission amplifier and the I
t
60 G receiving amplifier are also called a 60 G amplifier I I collectively, and the 80 G transmission amplifier and the 80 .
G receiving amplifier are also called an 80 G amplifier '
•
42
collectively.
[0168]
Figs. 5, 6, 7 and 8 are views showing simulation results of
[ the simulation for measuring various kinds of parameters of
the 60 G amplifier and the 80 G amplifier.
[ [0169]
Moreover, in the simulation, as shown in Fig. 4, a series
circuit of the resistor Rl and an AC power supply PI were
connected to the input terminal Tl and a series circuit of the I
resistor R2 and an AC power supply P2 were connected to the 1
output terminal T2 and various kinds of parameters of the 60 I
G amplifier and the 80 G amplifier were measured while changing I
the frequencies of the AC power supplies PI and P2 when I
necessary. 1
[0170] i
Fig. 5 shows an amplitude characteristic (60 GHz Gain) of the I
60 G amplifier and the size (absolute value) (60 GHz Sll) of 1
a reflection coefficient Sll at the input terminal Tl side and I
an amplitude characteristic (80 GHz Gain) of the 80 G amplifier I
and the size (80 GHz Sll) of the reflection coefficient Sll I
at the input terminal Tl side. I
[0171] I
The isolation between the amplitude characteristic of the 60 I
G amplifier and the amplitude characteristic of the 80 G I
amplifier is preferably set such that each of the 60 G band 1
43 I
signal after amplification in the 60 G amplifier and the 80
1 G band signal after amplification in the 80 G amplifier can
be received at the receiving side when the 60 G band signal
after amplification and the 80 G band signal after
amplification are transmitted through the transmission path j
after frequency multiplexing.
[0172]
Fig. 6 shows a phase (60 GHz Sll) of a reflection coefficient
Sll at the input terminal Tl side of the 60 G amplifier and
a phase (60 GHz S22) of a reflection coefficient S22 at the
output terminal T2 side and a phase (80 GHz Sll) of the
reflection coefficient Sll at the input terminal Tl side of
the 80 G amplifier and a phase (80 GHz S22) of the reflection
coefficient S22 at the output terminal T2 side.
[0173]
Fig. 7 is a smith chart showing each locus of the reflection 1
coefficient Sll (60 GHz Amp Sll) and the reflection coefficient j
S22 (60 GHz Amp S22) of the 60 G amplifier and each locus of 1
the reflection coefficient Sll (80 GHz Amp Sll) and the I
reflection coefficient S22 (80 GHz Amp S22) of the 80 G 1
amplifier, which are measured while changing the frequencies I
of the AC power supplies PI and P2 from 59 GHz to 61 GHz. I
[0174] j
According to Fig. 7, the sizes (absolute values) of the 1
reflection coefficients Sll and S12 of the 80 G amplifier for I
44
I
the signals of 59 GHz to 61 GHz are close to 1.0. Therefore,
i the signals of 59 GHz to 61 GHz, that is, 60 G band signals
1 are almost reflected at the input and output sides of the 80
G amplifier.
[0175]
Fig. 8 is a smith chart showing each locus of the reflection
coefficient Sll (60 GHz Amp Sll) and the reflection coefficient
S22 (60 GHz Amp S22) of the 60 G amplifier and each locus of
the reflection coefficient Sll (80 GHz Amp Sll) and the
reflection coefficient S22 (80 GHz Amp S22) of the 80 G
amplifier, which are measured while changing the frequencies
of the AC power supplies PI and P2 from 7 9 GHz to 81 GHz.
[0176]
According to Fig. 8, the sizes (absolute values) of the
reflection coefficients Sll and S12 of the 60 G amplifier for i
!
the signals of 79 GHz to 81 GHz are sufficiently large although
they are not as large as the reflection coefficients Sll and
S12 of the 80 G amplifier shown in Fig. 7. Therefore, the
signals of 79 GHz to 81 GHz, that is, 80 G band signals are 1
sufficiently reflected at the input and output sides of the 1
60 G amplifier. 1
[0177] I
As described above, since the frequency characteristics at the I
input and output sides of the 60 G amplifier and the 8 0 G |
amplifier become band pass type characteristics, 8 0 G band I
45 I
4
signals are reflected at the input and output sides of the 60
1 G amplifier and 60 G band signals are reflected at the input
J and output sides of the 80 G amplifier.
[0178]
Accordingly, when connection lines of outputs of the 60 G
transmission amplifier and the 80 G transmission amplifier are j
simply connected to each other, the 60 G band signal output
from the 60 G transmission amplifier is reflected at the output
side of the 80 G transmission amplifier and the 80 G band signal
output from the 80 G transmission amplifier is reflected at
the output side of the 60 G transmission amplifier. For this
reason, combination of the 60 G band signal output from the
60 G transmission amplifier and the 80 G band signal output
from the 80 G transmission amplifier can be performed just by
connecting the connection lines of the outputs of the 60 G
transmission amplifier and the 80 G transmission amplifier.
[0179]
In addition, when a composite signal obtained by combining the
60 G band signal and the 80 G band signal is given to the
connection point at which connection lines of inputs of the
60 G receiving amplifier and the 80 G receiving amplifier are
simply connected to each other, the 80 G band signal included I
in the composite signal is reflected at the input side of the I
60 G receiving amplifier and the 60 G band signal included in I
the composite signal is reflected at the input side of the 80 |
46 [
*
G receiving amplifier. Accordingly, distribution of the 60
s
I G band signal included in the composite signal to the 60 G
receiving amplifier and distribution of the 80 G band signal
included in the composite signal to the 80 G receiving amplifier i
can be performed just by connecting the connection lines of
the inputs of the 60 G receiving amplifier and the 8 0 G receiving
amplifier.
[0180]
That is, the combiner 41 which combines the 60 G band signal
output from the 60 G transmission amplifier with the 80 G band
signal output from the 80 G transmission amplifier may be formed
by only the connection point, which makes a connection between
the connection lines of the outputs of the 60 G transmission
amplifier and the 80 G transmission amplifier, without a BPF. I
[0181] I
In addition, the splitter 42 which distributes the 60 G band I
signal and the 80 G band signal included in the composite signal I
may be formed by only the connection point, which makes a I
connection between the connection lines of the inputs of the 1
60 G transmission amplifier and the 80 G transmission amplifier, |
without a BPF. I
[0182] I
As described above, by adopting the RF amplifier shown in Fig. |
4 as the amplifier 73 of the transmitter 51 and the amplifier ';
81 of the receiver 61 shown in Fig. 3, the combiner 41 can be 47 •
!
formed by only the connection point, which makes a connection
between the connection lines of the outputs of the transmitters 1
51i to 513, without a BPF and the splitter 42 can be formed 1
i
by only the connection point, which makes a connection between
the connection lines of the inputs of the receivers 61i to 613,
without a BPF.
[0183]
The SERDES sections 31i to 3I3, the combiner 41, and the splitter 1
42 which form the signal processor shown in Fig. 2 can be formed I
on a one-chip semiconductor chip, such as a CMOS, with small 1
sizes by forming the combiner 41 and the splitter 42 with only 1
the connection point which makes a connection between the I
connection lines. I
[0184] I
Fig. 9 is a circuit diagram showing an example of the I
configuration of the combiner 41 formed by only a connection 1
point which makes a connection between connection lines of the I
outputs of the 60 G transmission amplifier and the 8 0 G 1
transmission amplifier. I
[0185] I
Moreover, in Fig. 9, reference numerals obtained by adding I
prime (') to the reference numerals given to the components 1
of the RF amplifier shown in Fig. 4 are given to components I
of the 60 G transmission amplifier corresponding to the I
components of the RF amplifier shown in Fig. 4, and reference ?
i
t
48 I
f
>
»
numerals obtained by adding double prime (") to the reference
numerals given to the components of the RF amplifier shown in
Fig. 4 are given to components of the 8 0 G transmission I
amplifier corresponding to the components of the RF amplifier
shown in Fig. 4.
[0186]
In Fig. 9, the combiner 41 is formed by only the connection
point which makes a connection between the connection lines
of the outputs of the 60 G transmission amplifier and the 8 0 I
G transmission amplifier. I
[0187] I
Fig. 10 is a circuit diagram showing a circuit used in the 1
simulation for measuring various kinds of parameters of the 1
60 G transmission amplifier and the 80 G transmission amplifier, I
which is performed for the combiner 41 (Fig. 9) formed by only I
the connection point which makes a connection between the I
connection lines of the outputs of the 60 G transmission I
amplifier and the 80 G transmission amplifier. I
[0188] I
In Fig. 10, AC power supplies PI1, PI", and P2 for measuring I
the parameters are connected to the circuit shown in Fig. 9. I
[0189] I
Figs. 11 and 12 are views showing simulation results of the I
simulation for measuring various kinds of parameters of the I
60 G transmission amplifier and the 80 G transmission amplifier, |
|
i
i
49 |
t
i i
t
which was performed using the circuit shown in Fig. 10 for the
1 combiner 41 (Fig. 9) formed by only the connection point which
i makes a connection between the connection lines of the outputs
of the 60 G transmission amplifier and the 80 G transmission
I
amplifier.
[0190]
That is, Fig. 11 shows an amplitude characteristic (60 GHz thru)
of a signal transmitted through (passing through) the 60 G
transmission amplifier, an amplitude characteristic (80 GHz
thru) of a signal transmitted through the 80 G transmission
amplifier, an amplitude characteristic (60 GHz in return) of
a signal reflected at the input side of the 60 G transmission
amplifier, an amplitude characteristic (80 GHz in return) of
a signal reflected at the input side of the 80 G transmission
amplifier, and an amplitude characteristic (output return) of I
a signal reflected from the output side of the combiner 41 (to I
the 60 G transmission amplifier side and the 80 G transmission j
amplifier side). 1
[0191] I
Fig. 12 shows a phase characteristic (60 GHz in return phase) 1
of a signal reflected at the input side of the 60 G transmission
I
amplifier, a phase characteristic (80 GHz in return phase) of I
I
a signal reflected at the input side of the 80 G transmission f
'('•
amplifier, and a phase characteristic (output return phase) *
of a signal reflected from the output side of the combiner 41. r
[
50
••
•
[0192]
1 Fig. 13 is a circuit diagram showing an example of the
configuration of the splitter 42 formed by only a connection j
I
point which makes a connection between connection lines of the
inputs of the 60 G receiving amplifier and the 80 G receiving
amplifier.
[0193]
Moreover, in Fig. 13, reference numerals obtained by adding
prime (') to the reference numerals given to the components
of the RF amplifier shown in Fig. 4 are given to components
of the 60 G receiving amplifier corresponding to the components
of the RF amplifier shown in Fig. 4, and reference numerals
obtained by adding double prime (") to the reference numerals
given to the components of the RF amplifier shown in Fig. 4
are given to components of the 80 G receiving amplifier
corresponding to the components of the RF amplifier shown in
Fig. 4.
[0194]
In Fig. 13, the splitter 42 is formed by only the connection j
point which makes a connection between the connection lines j
of the inputs of the 60 G receiving amplifier and the 80 G I
receiving amplifier. I
[0195] I
Fig. 14 is a circuit diagram showing a circuit used in the I
simulation for measuring various kinds of parameters of the I
51 I
60 G receiving amplifier and the 80 G receiving amplifier, which
is performed for the splitter 42 (Fig. 13) formed by only the
connection point which makes a connection between the
connection lines of the inputs of the 60 G receiving amplifier
and the 80 G receiving amplifier.
[0196]
In Fig. 14, AC power supplies PI, P2', and P2" for measuring
the parameters are connected to the circuit shown in Fig. 13.
[0197]
Figs. 15 and 16 are views showing simulation results of the
simulation for measuring various kinds of parameters of the
60 G receiving amplifier and the 80 G receiving amplifier, which
was performed using the circuit shown in Fig. 14 for the
splitter 42 (Fig. 13) formed by only the connection point which
makes a connection between the connection lines of the inputs
of the 60 G receiving amplifier and the 80 G receiving
amplifier. 1
[0198] I
That is, Fig. 15 shows an amplitude characteristic (60 GHz thru) 1
of a signal transmitted through (passing through) the 60 G 1
receiving amplifier, an amplitude characteristic (80 GHz thru) |
of a signal transmitted through the 80 G receiving amplifier, 1
an amplitude characteristic (60 GHz out return) of a signal I
reflected at the output side of the 60 G receiving amplifier, |
an amplitude characteristic (80 GHz out return) of a signal J
52 I
reflected at the output side of the 80 G receiving amplifier,
i
and an amplitude characteristic (input return) of a signal
reflected at the input side of the splitter 42.
[0199]
Fig. 16 shows a phase characteristic (60 GHz out return phase)
of a signal reflected at the output side of the 60 G receiving
amplifier, a phase characteristic (80 GHz out return phase)
i
of a signal reflected at the output side of the 80 G receiving
amplifier, and a phase characteristic (input return phase) of
a signal reflected at the input side of the splitter 42.
[0200]
In addition, embodiments of the present disclosure are not
limited to the embodiments described above, and various changes
may be made without departing from the scope of the present 1
disclosure. I
[0201] I
That is, although the case where the present disclosure is 1
applied to the signal processor, which is a one-chip 1
semiconductor chip functioning as the SERDES, has been 1
described in the present embodiment, the present disclosure I
may also be applied to semiconductor chips other than the f
SERDES. I
[0202] I
The present disclosure contains subject matter related to that |
disclosed in Japanese Priority Patent Application JP |
53 j
I
2011-032340 filed in the Japan Patent Office on February 17,
2011, the entire content of which is hereby incorporated by
reference.
[0203]
1
It should be understood by those skilled in the art that various
modifications, combinations, sub-combinations and
alterations may occur depending on design requirements and
other factors insofar as they are within the scope of the
appended claims or the equivalents thereof.
[Reference Signs List]
[0204]
10: serializer
11: bit converter
12: P/S converter
13: driver
14: pad j
20: de-serializer I
21: pad I
22: receiver I
23: equalizer 1
24: CDR I
25: S/P converter 1
26: word alignment section 1
27: bit converter I
31i, 312, 313: SERDES section I
54 I
I
£
41: combiner
42: splitter
50: serializer
51: transmitter
60: de-serializer
61: receiver
71: oscillator
72: mixer
73, 81: amplifier
82: oscillator
83: mixer
!
.
i
i
r
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i
S
i
I
55 I

I
!
[CLAIMS]
[Claim 1]
A signal processor comprising:
a plurality of frequency converters which perform frequency
conversion of input signals to output converted signals; and
an output section which combines the converted signals output
!
from the plurality of frequency converters and outputs a
composite signal, •
wherein the plurality of frequency converters are formed in 1
a one-chip semiconductor chip, and I
the plurality of frequency converters perform frequency I
conversion into converted signals in different frequency 1
bands. I
[Claim 2] I
55 I
The signal processor according to claim 1,
wherein each of the frequency converters performs frequency
conversion of a signal in a predetermined frequency band as
the input signal and outputs a converted signal in a higher
frequency band than the predetermined frequency band.
[Claim 3]
The signal processor according to claim 2,
wherein a combining section which combines the converted
signals and outputs the composite signal is further formed in
the semiconductor chip.
[Claim 4]
The signal processor according to claim 3,
wherein the combining section is a connection point which makes
a connection between connection lines of outputs of the
plurality of frequency converters.
[Claim 5] 1
The signal processor according to claim 4, I
wherein each of the frequency converters has an amplifier which I
amplifies the converted signal, and I
the amplifier has an inductance load at least at an output side I
of input and output sides. I
[Claim 6] 1
The signal processor according to claim 2, 1
wherein a plurality of P/S converters which convert parallel I
data into serial data are further formed in the semiconductor I
56 I
j
chip, and
j one of the frequency converters performs frequency conversion
of the serial data which is a baseband signal output from one
of the P/S converters.
[Claim 7]
The signal processor according to claim 2,
wherein the composite signal is transmitted wirelessly.
[Claim 8]
The signal processor according to claim 7,
wherein the composite signal is transmitted through a
dielectric waveguide.
[Claim 9]
The signal processor according to claim 2, I
wherein the frequency converter performs frequency conversion 1
for converting the baseband signal into the converted signal I
in a frequency band equal to or higher than 30 GHz. 1
[Claim 10] I
A signal processing method comprising: 1
performing frequency conversion into converted signals in
I
different frequency bands by means of a plurality of frequency |
i
converters which perform frequency conversion of input signals \ I to output converted signals; ;-
T
outputting the converted signals after performing frequency *
',
i
conversion of the input signals by means of the frequency i
converters of a signal processor; and
57
r
:
i •
i '•
* 1
combining the converted signals output from the plurality of 1
i I
' frequency converters to output a composite signal, |
wherein the plurality of frequency converters which perform *
frequency conversion of input signals to output converted I
signals and an output section which combines the converted |
signals output from the plurality of frequency converters and |
outputs a composite signal are provided, and |
the plurality of frequency converters are formed in a one-chip I
semiconductor chip. I
[Claim 11] I
A signal processor comprising: 1
a plurality of frequency converters which perform frequency I
conversion of converted signals, which are obtained by |
performing frequency conversion of input signals, to output I
the input signals, |
wherein the plurality of frequency converters are formed in |
a one-chip semiconductor chip, I
the plurality of frequency converters perform frequency I
conversion of converted signals in different frequency bands, I
and I'
to each of the plurality of frequency converters, at least a f
converted signal in a frequency band to be frequency-converted I
by the frequency converter, of a composite signal obtained by I
combining a plurality of converted signals in different I
frequency bands, is distributed. I
58 I
t
[Claim 12]
The signal processor according to claim 11,
i wherein each of the frequency converters performs frequency
conversion of the converted signal which is a signal in a higher
frequency band than a predetermined frequency band and outputs
a signal in the predetermined frequency band.
[Claim 13]
The signal processor according to claim 12,
wherein a distribution section which distributes to each of
the plurality of frequency converters at least a converted
signal in a frequency band to be frequency-converted by the
frequency converter is further formed in the semiconductor
chip.
[Claim 14]
The signal processor according to claim 13,
wherein the distribution section is a connection point which I
makes a connection between connection lines of inputs of the I
plurality of frequency converters. I
[Claim 15] I
The signal processor according to claim 14, 1
wherein each of the frequency converters has an amplifier which J
amplifies a signal input to the frequency converter, and |
the amplifier has an inductance load at least at an input side I
of input and output sides. f
[Claim 16] I
59 J
The signal processor according to claim 12,
1 wherein a plurality of S/P converters which convert serial data
I into parallel data are further formed in the semiconductor chip,
' and
one of the frequency converters performs frequency conversion
| of a converted signal in a frequency band, which is to be
frequency-converted by the frequency converter, into the
serial data, which is a baseband signal, and supplies the
frequency-converted serial data to one of the S/P converters.
[Claim 17]
The signal processor according to claim 12,
wherein the composite signal is transmitted wirelessly.
[Claim 18]
The signal processor according to claim 17,
wherein the composite signal is transmitted through a 1
dielectric waveguide. J
[Claim 19] I
The signal processor according to claim 12, I
wherein the frequency converter performs frequency conversion 1
for converting a converted signal in a frequency band, which I
is equal to or higher than 30 GHz, into a baseband signal. I
[Claim 20] 1
A signal processing method comprising: 1
performing frequency conversion into converted signals in I
different frequency bands by means of a plurality of frequency I
60 I
i
converters which perform frequency conversion of converted
signals, which are obtained by performing frequency conversion
I
of input signals, to output the input signals;
distributing to each of the plurality of frequency converters
at least a converted signal in a frequency band, which is to
be frequency-converted by the frequency converter, of a
composite signal obtained by combining a plurality of converted
signals in different frequency bands; and
performing frequency conversion of the converted signal by the
frequency converter to output the input signal, I
wherein a signal processor distributes to each of the plurality J
of frequency converters at least a converted signal in a I
frequency band, which is to be frequency-converted by the |
frequency converter, of a composite signal obtained by I
combining a plurality of converted signals in different ;
frequency bands, and i
the plurality of frequency converters are formed in a one-chip
semiconductor chip.
[Claim 21]
A signal processor comprising:
a plurality of first frequency converters which perform
frequency conversion of input signals to output converted 1
signals; and f
a plurality of second frequency converters which perform I
frequency conversion of the converted signals to output the I
61 I
input signals,
I wherein the plurality of first frequency converters and the
I
plurality of second frequency converters are formed in a I
one-chip semiconductor chip, J
the plurality of first frequency converters perform frequency I
conversion into converted signals in different frequency bands,
the converted signals output from the plurality of first
frequency converters are combined, and a composite signal is 1
output, 1
the plurality of second frequency converters perform frequency I
conversion of the converted signals in different frequency 1
bands, and |
to each of the plurality of frequency converters, at least a I
converted signal in a frequency band to be frequency-converted I
by the frequency converter, of a composite signal from another |
semiconductor chip, is distributed. I
I
27
WO 2012/111278 PCT/JP2012/000844
^ input signals;
distributing to each of the plurality of frequency converters at least a
converted signal in a frequency band, which is to be frequencyconverted
by the frequency converter, of a composite signal obtained
by combining a plurality of converted signals in different frequency
' bands; and
performing frequency conversion of the converted signal by the
frequency converter to output the input signal,
wherein a signal processor distributes to each of the plurality of
frequency converters at least a converted signal in a frequency band,
which is to be frequency-converted by the frequency converter, of a
composite signal obtained by combining a plurality of converted
signals in different frequency bands, and
the plurality of frequency converters are formed in a one-chip semiconductor
chip.
[Claim 21] A signal processor comprising:
a plurality of first frequency converters which perform frequency
conversion of input signals to output converted signals; and
a plurality of second frequency converters which perform frequency
conversion of the converted signals to output the input signals,
wherein the plurality of first frequency converters and the plurality of
second frequency converters are formed in a one-chip semiconductor
chip,
the plurality of first frequency converters perform frequency
conversion into converted signals in different frequency bands, the
converted signals output from the plurality of first frequency converters
are combined, and a composite signal is output,
the plurality of second frequency converters perform frequency
conversion of the converted signals in different frequency bands, and
to each of the plurality of frequency converters, at least a converted
signal in a frequency band to be frequency-converted by the frequency
converter, of a composite signal from another semiconductor chip, is
distributed.