WE CLAIM
1. A modular simultaneous MIMO communication system comprising (a) a
PC 500, (b)a System Ethernet interface 501, (c)a Receive block R, (d) a
Transmit block T, (e)an Oven-Controlled Crystal Oscillator (OCXO) 522
and (f) a Clock Distribution 524wherein:
a. The PC 500 is any computing device that can transmit and receive
Ethernet data;
b. The PC 500 is connected through the System Ethernet interface
501 to the Receive block R and the Transmit block T;
c. The Clock Distribution 524 refers to a circuit that performs
distribution of Clock from the OCXO 522 or an external Clock
throughout the system;
d. The OCXO 522 provides an ultra-low jitter 10MHz clock and is
powered independently, to eliminate any clock leakage on power
supply lines; and
e. The system can also be clocked from a 10MHz external clock
source instead of an internal OCXO.
2. The modular simultaneous MIMO communication system of Claim 1
where the System Ethernet Interface 501 refers collectively to an Ethernet
data processing system that includes (a) an Ethernet Data Port 501a, (b) an
Ethernet Control Port 501b, (c) an ETH2TXIPB application 63, (d) a
Baseband Logic 66, (e) a Transmit Inter-Processor Bus 55, (f) an
IPB2MODEM Writer 56, (g) a DPDCM 57, (h) a HDLC encoder 58, (i) a
HDLC decoder 70, (j) a XCLK domain 69, (k) a MODEM2IPB writer 68,
(l) a Receive Side Inter-Processor Bus 67, (m) a RXIPB2ETH application
64, (n) a Baseband Processor 32and (o) an Application Processor 40
wherein, Input Bits 501xare transformed to analog stream and transmitted
over an Intermediate Frequency (IF) interface.

3. The modular simultaneous MIMO communication system of Claim 1 where the Transmit block T consists of (a) a Scrambler 535, (b) an FEC Encoder 534, (c)a Burst Modulator 533, (d) a DAC driver 531, (e)a Digital to Analog Converter (DAC)528, (f)a DAC DATACLK Generator 529, (g)a Low Pass Filter 527, (h) an IQ-Modulator 526, (i)an IQ-Modulator LO Generator 523, (j)an IF Front-end 525, (k) a Splitter 519 and (l) Transmit signals 517, 518, wherein:
a. The scrambler535is used to enable accurate timing recovery on the
receiver without resorting to redundant line coding and to disperse
the energy on the carrier,it disperses the data to meet the maximum
power spectral density requirements;
b. Scrambled Input Bits 535x are those transmitted after scrambling
and interleaving process;
c. The FEC Encoder 534 is a suitable standard forward error
correction encoder used to encode the data;
d. Encoded and Scrambled Input Bits 534x are bits after Scrambling
and FEC encoding processes;
e. The Burst Modulator 533 converts the data bits to In-phase (I) and
Quadrature-Phase (Q) data with appropriate gain and further
converts the stream of I and Q data to a user selected data rate
without any drop in received input data;
f. The DAC Driver 531 runs on a user selected Clock Frequency,
which is an operating frequency of the Digital to Analog Converter
528 and converts the data into a format suited for the same;
g. The Digital to Analog Converter 528,accepts a multi-bit parallel
digital data from the DAC Driver531and produces an analog
voltage proportional to the digital value;
h. The Digital to Analog Converter 528 has dual channels, one for In-Phase (I) data and the other for Quadrature-phase(Q) data;

i. The Low Pass Filter 527 eliminates harmonics that are outside of
passband from an output of the Digital to Analog Converter 528 to
conserve bandwidth; j. The IQ-Modulator 526 combines the In-phase (I) and the
Quadrature-phase (Q) outputs of the Low Pass Filter 527 and
upconverts to Intermediate Frequency (IF); k. The IF Front-end 525 comprises an SAW Filter network,
Attenuators and Low Noise Amplifiers of the Transmit side; l. The Splitter 519sends two copies of the signal to two different
transmit ports; m. The Transmit Out-1 517is the signal given to one transmit port and
thereon to the associated transmit connector, whereas the Transmit
Out-2 518 is the signal given to another transmit port and then to
the associated transmit connector; n. The IQ-Modulator 526 is clocked by the IQ- 523, which in turn
receives its input clock from the DAC Data Clock Generator 529;
and o. The DAC Data Clock Generator 529 generates the clock required
for the Digital to Analog Converter 528 from the Clock
Distribution 524.
4. The modular simultaneous MIMO communication system of Claim 1 where the Receive block R consists of (a) Receive Channel-1 516a, Receive Channel-2 516b, Receive Channel-3 516c and Receive Channel-4 516d, (b) Intermediate Frequency (IF) Front-end-1 515a, Intermediate Frequency (IF) Front-end-2 515b, Intermediate Frequency (IF) Front-end-3 515c and Intermediate Frequency (IF) Front-end-4 515d, (c) IQ Demodulators 514a, 514b, 514c, 514d, (d)Signal Conditioning 513a, 513b, 513c, 513d, (e) Analog to Digital Converters (ADC) 512a, 512b, 512c, 512d, (f) a Multilevel Equalizer Aided Channel Combining and Demodulator 511, (g) a Forward Error Correction (FEC) Decoder 508,

(h)a Descrambler 507, (i)a 4x IQ DEMOD LO Generator 520 and (j) a 4×ADC CLK Generator 521, wherein:
a. The Descrambler 507 organizes the data which is muddled by the
Scrambler 535 during the transmission;
b. The Scrambled Bit Output 508x corresponds to an input of the
Descrambler 507;
c. The FEC Decoder 508 on the receive side is responsible for
decoding of the data which is encoded by the FEC Encoder 534 on
the transmit side such that, if the FEC Encoder 534 is disabled on
the transmit side then the FEC Decoder 508 will be evaded;
d. Bit Error Rate (BER) 509corresponds to number of bit inaccuracies
that are observed over a predefined data length;
e. Encoded and Scrambled Bit output 510 are bits before being sent
to the FEC Decoder 508;
f. The Multilevel Equalizer Aided Channel Combining and
Demodulator 511 acquire the data from the multiple Analog to
Digital Converters (ADC) 512a..d, performs Co-Phasing,
subsequently diversity combining, equalizes and demodulates the
signal to obtain the data;
g. The Analog to Digital Converters (ADC) 512a..d converts the
analog baseband signal to a proportional multi-bit parallel digital
value;
h. The Signal Conditioning 513a..d prepares analog signal to be
suitable for the Analog to Digital Converters (ADC) 512a..d; i. The IQ Demodulators 514a..d convert the Intermediate Frequency
(IF) signal to a baseband signal; j. The Intermediate Frequency (IF) Front-end515a..d comprises of
Analog Filter networks, Attenuators and Low Noise Amplifiers for
each receive channel; k. Multiple Receive Channels516a..d corresponds to the input signal
given to the system through connectors of the enclosure;

l. The 4x IQ DEMOD LO Generator 520 generates the clock required for the respective IQ Demodulator 514a..d; and
m. The4 x ADC Clock Generator 521 generates the clock necessary for the respective Analog to Digital Converter 512a..dand provide the input clock to the4x IQ DEMOD LO Generator 520, the4 x ADC Clock Generator 521inputs are generated from the Clock Distribution 524.
5. The modular simultaneous MIMO communication system of Claim 1, the Baseband processor and Application Processor in a chip with its embedded blocks comprising (a) an Ethernet Data Port 501a, (b) an ETH2TXIPB application 63, (c) a Baseband Logic 66, (d) a Transmit Inter-Processor Bus 55, (e) an IPB2MODEM Writer 56, (f) a DPDCM 57, (g) a HDLC encoder 58, (h) a HDLC decoder 70, (i) a XCLK domain 69, (j) a MODEM2IPB writer 68, (k) a Receive Side Inter-Processor Bus 67, (l) a RXIPB2ETH application 64, (m) a Baseband Processor 32, (n) an Application Processor 40, (o) a Burst Modulator 59, (p) a DPDCM Lossless 60, (q) a DAC Driver 531, (r) a Descrambler 507, (s) an FEC Decoder 508, (t)anFEC Encoder 534, (u) a Scrambler 535, (v)a Digital data to DAC 41via one or more interface connectors, (w) Scrambled Bit output 510 and (x)Bit Error Rate (BER) 509 wherein:
a. The Ethernet Data Port 501a obtains transmit data and sends out
received data;
b. The ETH2TXIPB Application 63 is responsible for manipulating
the user data such as providing compression and encryption of data
received from PC 500 via the Ethernet Data Port 501a;
c. The Baseband Logic 66 encapsulates all the processing involved in
converting the Multilevel Equalizer Aided Channel Combining and
Demodulator 511 output to bits, this also encapsulates processing
involved in converting the bits suitable for input to Digital to
Analog Converter (DAC) 528a;

d. The Transmit Inter-Processor Bus 55 which is of any Standard
Inter-Processor Communication Bus forwards the data obtained
from the Application Processor 40 to the Baseband Processor 32;
e. The IPB2MODEM Writer 56 is responsible for generating the flow
control signal so as to match the data transmission speed of the
Application Processor 40, which also acts as a buffer to match the
speeds of the Application Processor 40 to the Baseband Processor
32;
f. The DPDCM 57 converts the stream of In-phase (I) and
Quadrature-Phase (Q) data to the user selected data rate;
g. The HDLC Encoder58is a standard High-Level Data Link Control
(HDLC) and is a bit oriented code transparent synchronous data
link layer protocol that converts the 8-Bit parallel data to 1-Bit
serial data, also adds the header, footer and standard Cyclic
Redundancy Check (CRC) and manipulates the data in order to
eliminate the header occurrence in the data stream;
h. The XCLK Domain 69 converts the data on a User Clock into a standard clock which is used for further processing;
i. The MODEM2IPB writer 68 translates the flow control signal from the Baseband Processor 32 and the Application Processor 40, also acts as the buffer to synchronize the Baseband Processor 32 and Application Processor 40;
j. The Receive Side Inter-Processor bus 67 is responsible for handing over the data obtained from the Receive block R of the system to the RXIPB2ETH Application 64 which aids in manipulating the user data such as providing decompression and decryption of the received data packets;
k. The Baseband Processor 32 modulates the data received from the Application processor 40 and also decodes the data received from the Multilevel Equalizer Aided Channel Combining and Demodulator 511;

l. The Application Processor 40 andtheBaseband Processor 32 is
realized as one or more Application Specific Integrated Circuits
(ASIC) or Field Programmable Gate Arrays (FPGA’s) or a
combination of both; m. The FEC Encoder 534 is a suitable standard forward error
correction encoder used to encode the data; n. The Burst Modulator 59 converts the data bits to In-phase (I) and
Quadrature-Phase (Q) data with appropriate gain; o. The DPDCM Lossless 60 converts the stream of In-phase (I) and
Quadrature Phase (Q) data to the user selected data rate without
skipping any input data received; p. The DAC Driver 531a runs on a selected clock frequency, which is
the operating frequency of the Digital to Analog Converter 528a
and converts the data into a format suited for the same; q. The FEC Decoder 508 on receive signal processing side is
responsible for decoding of the data that is encoded by the FEC
Encoder 534 on the transmit side and if the FEC Encoder 534 is
disabled on the transmit side, the FEC Decoder 508 will be
bypassed; r. The scrambler535is used to enable accurate timing recovery on the
receiver without resorting to redundant line coding and to disperse
the energy on the carrier,it disperses the data to meet the maximum
power spectral density requirements; s. The Descrambler 507 organizes the data which is muddled by the
Scrambler 535 during the transmission; t. The HDLC Decoder 70 undoes the action done by the HDLC
Encoder 58 and converts the bit data into bytes and CRC is used to
validate the byte data and subsequently removed; u. The Digital data to DAC 41via one or more interface connectors is
the entry point for the TX CHAIN PCB assembly; and

v. The data from Transmit of the Baseband Processor 32 will enter the TX CHAIN PCB Assembly via the Inter-board Connectors.
6. A modular apparatus for simultaneous MIMO communication having a Communication Modem whose components include (a) an Ethernet Data Port 501a, (b) an Ethernet Control Port 501b, (c) an Application Processor 40, (d) a Baseband Processor 32, (e)a transmit PCBassembly,(f)a receivePCBassembly,(g) a Multilevel Equalizer Aided Channel Combining and Demodulator 511, (h) an OCXO522 and (i) a Clock Distribution 524, wherein:
a. The transmit PCBassembly, TX Chain PCBA-Front-end 525a
includes transmit ports, a Digital to Analog Converter 528a and
forms a transmit analog signal conditioning part of the system and,
one or more transmit ports TX Port-139a and TX Port-239bto
transmit Intermediate Frequency (IF) signal;
b. The receivePCB assembly having a Front-end comprising, a RX
Chain PCBA-Front-end-1 515h, a RX Chain PCBA-Front-end-2
515g, a RX Chain PCBA-Front-end-3 515f and a RX Chain
PCBA-Front-end-4 515e, and one or more receive ports including,
RX PORT-1 38d, RX PORT-2 38c, RX PORT-3 38b and RX
PORT-4 38a, where the PCBA-Front-end 515e..hprovide signal
conditioning to the IF received from receive ports;
c. The Ethernet Data Port 501a obtains transmit data and sends out
received data while the Ethernet Control Port enables toconfigure
andcontrol the characteristics of the modem sub-system running in
the Baseband Processor32and theApplication Processor40;
d. The Application Processor 40 facilitates the exchange of data
between the Ethernet Data Port 501a and the Baseband Processor
32 and is realized as one or more Application Specific Integrated
Circuits or Field Programmable Gate Arrays (FPGA’s) or a
combination of both; and

e. The Baseband Processor 32 performs the function of modulating the data received from the Application Processor 40 and also decodes the data received from the Multilevel Equalizer Aided Channel Combining and Demodulator 511 and is realized as one or more Application Specific Integrated Circuits or Field Programmable Gate Arrays (FPGA’s) or a combination of both.
7. The modular apparatus for simultaneous MIMO communication of Claim 6, wherein a wholly enclosed system in isometric view has the front panel comprising (a) an Ethernet Data Connector 501c, (b)an Ethernet Control Connector 501d, (c) a RX Connector-1 38e,(d) a RX Connector-2 38f,(e) a RX Connector-3 38g, (f) a RX Connector-4 38h, (g)aTX Connector-1 39c, (h) a TX Connector-2 39d and (i) an external Clock Connector 411, comprising:
a. The Ethernet Data Connector 501cis connected by a cable to the
Ethernet Data Port 501a;
b. The Ethernet Control Connector 501d provides interface to the
configuration of the Baseband Processor 32 and the Application
Processor 40, and is situated in an enclosure of the apparatus
connected by a cable to the Ethernet Control Port 501b;
c. The RX Connector-1 38e, RX Connector-2 38f, RX Connector-3
38g, RX Connector-4 38h are on a field space of the apparatus that
are connected by a cable to the receive ports, RX Port-1 38d, RX
Port-2 38c, RX Port-3 38b, RX Port-4 38a;
d. The TX Connector-1 39c and TX Connector-2 39d are connected
to TX Port-1 39a andTX Port-2 39b by a cable; and
e. The external Clock Connector 411 is a connector that carries an
external 10 MHz stable reference to the system and can be used
instead of the OCXO 522assembled into the system.

8. The modular apparatus for simultaneous MIMO communication of Claim 6, where the important components in transmit PCB Assembly consists of (a) a Digital to Analog Converter (DAC) 528a,(b) an IQ-Modulator 526, (c) a TX Low Pass Filter 527, (d) a TX Saw Filter-1 46a, a TX Saw Filter-2 46b, (e) a TX Digital Step Attenuator 47, (f) a TX Low Noise Amplifier 48, (g) a Splitter 519, (h) transmit ports, TX Port-1 39a,TX Port-2 39b, (i)an IQ MOD LO Generator 520a, (j) a DAC DATACLK Generator 529aand (k) Digital data to DAC41via one or more interface connectors comprising:
a. The Digital to Analog Converter (DAC) 528ahas dual channels,
one for In-Phase (I) data and other for Quadrature-phase (Q) Data
accepts a multi-bit parallel digital data;
b. The TX Low Pass Filter 527that removes harmonics that are
outside of the passband from the output of the Digital to Analog
Converter528a to conserve bandwidth, and the TX Low Noise
Amplifier 48 provides amplification to bandpass signal;
c. The IQ-Modulator 526that combines the In-phase (I) and
Quadrature-phase (Q) outputs of the TX Low Pass Filter 527 and
upconverts to Intermediate Frequency;
d. The TX Saw Filter-146athat removes the out-of-band noise in a
spectrum of the Transmit signal, and the TX Digital Step
Attenuator 47 prevents subsequent components from getting into
saturation, also aids to attenuate signal strength, if required;
e. The TX Saw Filter-2 46bthat is responsible for removing out-of-
band noise in the spectrum of the Transmit signal which is
introduced after the TX Low Noise Amplifier48;
f. The Splitter 519is applied to achieve transmit diversity by sending
two copies of the same signal to two transmit ports;
g. The transmit Intermediate Frequency (IF) signal that is given to the
transmit ports TX Port-139a and TX Port-2 39b, the number of
ports is any even number as determined during installation;

h. The IQ MOD LO Generator 520a generates clock required for the IQ-Modulator 526 from the DAC DATACLK Generator 529a, and the DAC DATACLK Generator 529a generates the clock needed to the Digital to Analog Converter 528a from the Clock Distribution 524; and
i. The Digital data to DAC 41via one or more interface connectors refers to a digital form of data that is given to the Digital to Analog Converter 528a, the digital value corresponds to an analog voltage value which is the output of the Digital to Analog converter 528.
9. The modular apparatus for simultaneous MIMO communication of Claim 6 where the receive PCB Assembly consists of (a) an Analog to Digital converter 512, (b)an ADC CLK Generator 521a, (c) an IQ DEMOD LO Generator 50, (d) an IQ Demodulator 514, (e) an Amplifier 51, (f)a RX Saw Filter-2 52a, (g) a RX Saw Filter-1 52b, (h) a RX Low Noise Amplifier 53, (i)a RX Digital Step Attenuator 54, (j)Receive-in 516 and (k) Digital data from ADC 43 further comprising:
a. The Receive-in 516 that refers to the ports, RX Port-1 38d, RX
Port-2 38c, RX Port-3 38b and RX Port-4 38a;
b. The RX Saw Filter-1 52bthat is a bandpass filter centered at an IF
frequency is responsible for removing out-of-band noise from the
signal;
c. The RX Digital Step Attenuator 54thatprevents the subsequent
components from getting into saturation and also aids to attenuate
the signal strength if required, and the RX Low Noise Amplifier 53
provides amplification to bandpass signal;
d. The RX Saw Filter-2 52athatfacilitates removal of the out-of-band
noise in spectrum of its received input;
e. The IQ Demodulator 514thatconverts filtered and conditioned IF
signal to baseband at 0Hz and provides In-phase (I) and
Quadrature-phase (Q) signals;

f. The Amplifier 51thatmagnifies and shifts DC level of the baseband
signal to levels appropriate for further signal processing;
g. The Analog to Digital converter 512thatconverts the analog
baseband signal to a proportional, multi-bit parallel digital value;
h. The ADC CLK Generator 521athat generates clock required for the Analog to Digital Converter 512 from the Clock Distribution 524, and the IQ DEMOD LO Generator 50 generates the clock required for the IQ Demodulator 514 from the 4×ADC CLK Generator 521; and
i. The Digital data from ADC 43thatis a digital form of data which is an output of the Analog to Digital Converter 512and the digital value corresponds to an analog voltage value which is an input of the Analog to Digital Converter 512.
10. The modular apparatus for simultaneous MIMO communication of Claim 6 wherea top side view of the fully assembled unenclosed system comprises(a) an Ethernet Data Port 501a, (b) an Ethernet Control Port 501b, (c) a Carrier Card 465, (d) a System Processor 466, (e) a Clock Distribution 524, (f) a Multilevel Equalizer Aided Channel Combining and Demodulator 511, (g) an OCXO 522and (h) PCB Assemblies, RX Chain PCBA-Front-end-1 515h, RX Chain PCBA-Front-end-2 515g, RX Chain PCBA-Front-end-3 515f, RX Chain PCBA-Front-end-4 515e and (i) a TX Chain PCBA-Front-end 525a, wherein:
a. The Ethernet Data Port 501a is a port from which transmit data is
obtained and to which received data is sent;
b. The Ethernet Control Port 501benables to configure and control
the characteristics of the modem sub-system running in the
Baseband Processor32 and the Application Processor40;
c. The System Processor 466 consists of the Application Processor 40
and Baseband Processor 32 realized in a single Field
Programmable Gate Array (FPGA);

d. The Multilevel Equalizer Aided Channel Combining and
Demodulator 511 is a unique equalizer realized as one or more
Application Specific Integrated Circuits (ASIC) or Field
Programmable Gate Arrays (FPGA’s) or a combination of both and
acts on digital data received at output of the Receive front-end
blocks;
e. The OCXO 522 provides an ultra-low jitter 10MHz clock and is
powered independently to eliminate any clock leakage on power
supply lines and the system can also be clocked from a 10MHz
external clock source instead of an internal OCXO;
f. The Clock Distribution 524 refers to a circuit that performs
distribution of clock from the OCXO 522 or an external clock
throughout the system;
g. The Carrier Card 465 is a PCB Assembly that holds all other
discrete circuits onto itself;
h. The TX Chain PCBA-Front-end 525a is a PCB Assembly that forms analog signal conditioning section and consists of multiple components including a Digital to Analog Converter 528a; and
i. The RX Chain PCBA-Front-end-1 515h, RX Chain PCBA-Front-end-2 515g, RX Chain PCBA-Front-end-3 515f, RX Chain PCBA-Front-end-4 515e are PCB assemblies that provide signal conditioning to IF received from receiving ports and are front-end assemblies, also include an Analog to Digital Converter 512 resulting in digital output analogous to the input.
11. The modular apparatus for simultaneous MIMO communication of Claim 6, wherein a bottom side view of a fully assembled unenclosed system comprises(a) a Digital data to DAC 41via one or more interface connectors, (b) a Digital to Analog Converter 528a, (c) DAC DATACLK Generator 529a, (d) a TX Low Pass Filter 527, (e)an IQ MOD LO Generator 520a, (f) an IQ-Modulator 526, (g) a TX Saw Filter-1 46a, TX

Saw Filter-2 46b, (h)a TX Digital Step Attenuator 47, (i) a TX Low Noise Amplifier 48, (j) a Splitter 519, (k) transmit ports,TX Port-1 39a,TX Port-2 39b, (l) a TX Chain PCBA-Front-end 525a, (m)receive ports, RX PORT-1 38d, RX PORT-2 38c, RX PORT-3 38b, RX PORT-4 38a, (n) receive Saw Filters, CH-1 RX Saw Filter-1 413, CH-2 RX Saw Filter-1 424, CH-3 RX Saw Filter-1 433, CH-4 RX Saw Filter-1 442, (o) Digital Step Attenuators, CH-1 Digital Step Attenuator 414, CH-2 Digital Step Attenuator 425, CH-3 Digital Step Attenuator 434, CH-4 Digital Step Attenuator 443, (p) Low Noise Amplifiers, CH-1 Low Noise Amplifier 415, CH-2 Low Noise Amplifier 426, CH-3 Low Noise Amplifier 435, CH-4 Low Noise Amplifier 444, (q) receive Saw Filters, CH-1 RX Saw Filter-2 416, CH-2 RX Saw Filter-2 427, CH-3 RX Saw Filter-2 436, CH-4 RX Saw Filter-2 445, (r) IQ Demodulators, CH-1 IQ Demodulator 514a, CH-2 IQ Demodulator 514b, CH-3 IQ Demodulator 514c, CH-4 IQ Demodulator 514d, (s) IQ DEMOD Clock generators, CH-1 IQ DEMOD CLKGEN 419, CH -2 IQ DEMOD CLKGEN 429, CH-3 IQ DEMOD CLKGEN 438, CH -4 IQ DEMOD CLKGEN 447, (t) Amplifiers, CH-1 Amplifier 418, CH-2 Amplifier 451, CH-3 Amplifier 452, CH-4 Amplifier 453, (u) Analog to Digital Converters 512a,512b,512c,512d, (v) a Clock Distribution 524, (w) ADC Clock generators, CH-1 ADC CLKGEN 421, CH-2 ADC CLKGEN 430, CH-3 ADC CLKGEN 439, CH-4 ADC CLKGEN 448, (x) a Digital Data from CH-1 ADC to Connector 422, (y) a Digital Data from CH-2 ADC to Connector 431, (z) a Digital Data from CH-3 ADC to Connector 440, (aa) a Digital Data from CH-4 ADC to Connector 449, (bb) RX Chain PCBA-Front-end 515h, 515g, 515f, 515e, (cc) a Multilevel Equalizer Aided Channel Combining and Demodulator 511 and (dd) a Carrier Card 465, wherein:
a. The TX Chain PCBA-Front-end 525a is a PCB assembly that forms transmit analog signal conditioning section of the system and consists of multiple components including the Digital to Analog Converter 528a;

b. TheDigital data to DAC 41via one or more interface connectorsis
an entry point for the TX Chain PCB assembly, data from the
Transmit side of the Baseband Processor 32will enter the TX Chain
PCB assembly via Inter-board connectors;
c. PCB trace length of the Digital to Analog Converter 528adata
clock is reduced, by placing the DAC DATACLK Generator
529aadjacent to the Digital to Analog Converter 528a,which is
contiguous to the TX Low Pass Filter 527for minimizing the PCB
trace length of the analog signal trace;
d. The IQ MOD LO Generator 520ais placed adjacent to the IQ-
Modulator 526 to lessen the PCB trace length, and this component
derives its clock from the DAC DATACLK Generator 529a,hence
placed adjacent to it;
e. The TX Low Pass Filter 527 is placed after the Digital to Analog
converter528a, the IQ-Modulator 526after the TX Low Pass Filter
527 and theTX Saw Filter-146a after the IQ-Modulator526,the TX
Digital Step Attenuator47 after the TX Saw Filter-1 46a, the TX
Low Noise Amplifier 48 after the TX Digital Step Attenuator47,
the TX Saw Filter-246b after the TX Low Noise Amplifier
48andthe Splitter 519 after the TX Saw Filter-2 46b;
f. TheTX Port-2 39bis positioned after the Splitter 519, the TX Port-
139a is also positioned after the Splitter519 and adjacent to the TX
Port-239b whereas the RX PORT-1 38d, RX PORT-2 38c, RX
PORT-3 38b, RX PORT-4 38a are placed at an edge of the
Receive Front PCBA;
g. The CH-1 RX Saw Filter-1 413, CH-2 RX Saw Filter-1 424, CH-3
RX Saw Filter-1 433, CH-4 RX Saw Filter-1 442 removes out of
the band noise in signal and are placed just after the respective RX
Ports 38d, 38c, 38b, 38a;
h. The CH-1 Digital Step Attenuator 414, CH-2 Digital Step Attenuator 425, CH-3 Digital Step Attenuator 434, CH-4 Digital

Step Attenuator 443 prevent subsequent LNA from getting into saturation and also aids to attenuate signal strength if required, these are placed after respective RX Saw Filters, CH-1 RX Saw filter-1413, CH-2 RX Saw filter-1424,CH-3 RX Saw filter-1433,CH-4 RX Saw filter-1442;
i. The CH-1 Low Noise Amplifier 415, CH-2 Low Noise Amplifier 426, CH-3 Low Noise Amplifier 435, CH-4 Low Noise Amplifier 444 are intended to provide amplification to bandpass signal and are positioned after respective Digital Step Attenuators 414, 425, 434, 443;
j. The CH-1 RX Saw Filter-2 416, CH-2 RX Saw Filter-2 427, CH-3 RX Saw Filter-2 436, CH-4 RX Saw Filter-2 445 are responsible for removing out-of-band noise in a spectrum of signal that is introduced after Low Noise Amplifier and is located after the Low Noise Amplifiers 415,426,435,444;
k. The CH-1 IQ Demodulator 514a, CH-2 IQ Demodulator 514b, CH-3 IQ Demodulator 514c, CH-4 IQ Demodulator 514d convert Intermediate Frequency bandpasssignal to a baseband signal and are placed after the respective RX Saw Filter-2416,427,436,445, also, have respective IQ DEMOD CLKGEN 419,429,438,447 adjacent to them in order to decrease the PCB trace length of Clock Signal input to these components;
l. The CH-1 Amplifier 418, CH-2 Amplifier 451, CH-3 Amplifier 452, CH-4 Amplifier 453, amplify and perform DC level shift of analog signal to levels appropriate to respective Analog to Digital Converters 512a,512b,512c,512d, are positioned after the respective IQ Demodulators514a, 514b, 514c,514d;
m. The CH-1 IQ DEMOD CLKGEN 419, CH -2 IQ DEMOD CLKGEN 429, CH-3 IQ DEMOD CLKGEN 438, CH -4 IQ DEMOD CLKGEN 447generate IQ demodulator clock from ADC CLKGEN and are adjacent to respective IQ Demodulators on one

side to reduce PCB trace length of the IQ Demodulator Clock signal and ADC CLKGEN to lessen reference clock signal trace length;
n. The CH-1 Analog to Digital Converter 512a, CH-2 Analog to Digital Converter 512b, CH-3 Analog to Digital Converter 512c, CH-4 Analog to Digital Converter 512d convert analog signal from respective Amplifiers 418,451,452,453 to proportional digital values and are situated after the respective amplifiers and are also placed adjacent to the respective ADC CLKGEN 421,430,439,448 to minimize the PCB trace length of ADC Clock Signal;
o. The CH-1 ADC CLKGEN 421, CH-2 ADC CLKGEN 430, CH-3 ADC CLKGEN 439, CH-4 ADC CLKGEN 448 provide clock signal to respective ADCs 512a, 512b, 512c, 512d using input from the Clock Distribution 524 and are placed immediately adjacent to the Analog to Digital Converter for reduced ADC Clock signal trace length, also positioned very adjacent to respective IQ DEMOD CLKGEN 419,429,438,447 to lessen reference clock signal lengths;
p. The Digital Data from CH-1 ADC to Connector 422, Digital Data from CH-2 ADC to Connector 431, Digital Data from CH-3 ADC to Connector 440, Digital Data from CH-4 ADC to Connector 449 are the exit points of each of the respective RX Chain PCBA-Front-end 515h, 515g, 515f, 515e;
q. The Digital data from ADC 43 are forwarded to Inter-Board Connectors and are taken to the Multilevel Equalizer Aided Channel Combining and Demodulator 511 for further processing of data;
r. The RX Chain PCBA-Front-end comprises a connector that carries the buffered digital ADC samples from the respective RX Chain PCBA-Front-end 515h, 515g, 515f, 515e to the Carrier Card 465; and

s. The TX Chain PCBA-Front-end 525a holds transmit side components of the apparatus, the RX Chain PCBA-Front-end-1 515h, RX Chain PCBA-Front-end-2 515g, RX Chain PCBA-Front-end-3 515f, RX Chain PCBA-Front-end-4 515e hold receive side components of the Communication modem and are mounted on bottom side of the Carrier Card 465, connected electrically via inter-board connectors and mechanically using spacers.