CLIAMS:1. A communication system comprising:
a plurality of communication modules;
a bus driver; and
a bus line configured to connect the bus driver with the plurality of communication modules, wherein the bus driver receives data from the plurality of communication modules and integrates the data in a defined pattern to generate an output value based on which a voltage corresponding to the output value is identified such that the bus line is driven using the voltage.

2. The system of claim 1, wherein the data from the plurality of communication modules is in the form of a sequence of bits, and integration of the data is performed by conversion of the sequence of bits of the plurality of communication modules at a given time instance into a decimal output value.

3. The system of claim 1, wherein the data from each of the plurality of communication modules is integrated by positioning the data from the plurality of communication modules in the defined pattern and by computing the output value based on the pattern layout of the data from the plurality of communication modules.

4. The system of claim 1, wherein the bus driver issues a synchronous clock signal to each of the plurality of communication modules, and wherein the plurality of communication modules send their data synchronously to the bus driver based on the clock signal.

5. The system of claim 1, wherein the bus driver stores the data from the plurality of communication modules in a main register.

6. The system of claim 5, wherein each of the plurality of communication modules is assigned a bit position in the main register, and wherein the plurality of communication modules are aware of their respective bit positions.
7. The system of claim 1, wherein the pattern indicates the bit position for data from each of the plurality of communication modules.

8. The system of claim 1, wherein the voltage is sensed by ADC of the plurality of communication modules and decoded back by the plurality of communication modules.

9. The system of claim 1, wherein at least one of the plurality of communication modules senses the voltage as a sample and stores the sample in a receive buffer.

10. The system of claim 9, wherein the receive buffer of the at least one of the plurality of communication modules checks for a start signature indicative of the communication module sending a message.

11. A method comprising the steps of:
receiving, at a bus driver, data from a plurality of communication modules; and
integrating, at the bus driver, the data in a defined pattern to generate an output value based on which a voltage corresponding to the output value is identified such that a bus line that is operatively coupled to the bus driver and to the plurality of communication modules is driven using the voltage.
,TagSPECI:TECHNICAL FIELD
[0001] The present disclosure generally relates to the field of multi module communication. In particular, the present disclosure pertains to methods and systems for simultaneous multi module communication.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art
[0003] With growing adaptation of smart grid technologies in power distribution sector, power transmission devices, such as transformers, switches, circuit breakers, switchgear, meters etc need to be able to send/receive data in addition to transferring/controlling the electronic power. For the smart grid participating devices such as circuit breakers of present day, it is not only enough to detect/clear/manage the electrical faults or transfer the electric power, but it is also very important that these devices communicate with each in efficient manner. To enable a real smart grid system, participating devices should be able to communication with each other without much delay in communication. As we progress into the world of smart power grids, it is imperative that different participating devices start talking to each other in time bounded manner so that the appropriate decisions can be taken on time.
[0004] For example, a circuit breaker of smart grid system of present day should not only be able to detect and clear faults, but should also have communication facility to exchange data simultaneously other circuit breaker in the network. Circuit breakers are expected to communicate amongst themselves as well as with their accessory modules or another module and hence required to be able to exchange huge amount of data. As the size of grid is becoming bigger, the number of circuit breakers in the system/network is increasing and so is the amount of data that needs to be exchanged among them. Transferring such big data from multiple participating devices in time efficient manner is a major challenge.
[0005] To enable communication among smart grid devices, different communication protocols, such as CAN BUS, Profi Bus, MOD bus etc are used by these smart grid devices. These protocols have predefined structure of sending and receiving communication data, wherein the smart grid devices can communicate with other similar smart grid device using multiple module connections over a shared communication channel/line. As the communication among these smart grid devices, such as circuit breakers, is enabled through a shared bus, these smart grid devices should also be able to manage the control of the bus line properly such that the signals/data send by different circuit breakers don’t overlap. That means at any given time only one module can send signals/data over the shared bus to avoid loss or data or data corruption. Allocation of bus line is generally controlled using a scheduling algorithm such that at any given time only one module send signal on the bus line, when multiple modules need to send signal/data. If multiple modules start sending different signal/data at the same on a single bus line, the signal/data might get corrupted and may cause loss of communication. In present implementation, any module that needs to send any signal/data, first checks if the bus line is free, and on affirmative conformation only it take control of the bus and sends the signal/data through the shared bus.
[0006] There may be cases where multiple modules needs to send signal/data, but as per the existing protocol, only one module gets the shared bus line for sending the signal/data and hence the other modules may have to wait for its turn. If two modules want to send data together the second module has to wait for the time taken by first module to send the data completely, and leave the control of the bus line before the second module takes control of the bus line and starts sending signal from second module. The problem manifolds when multiple modules have to send signals/data, as it may lead to longer waiting time for some of the modules.
[0007] Though the problem have been described with respect to smart grid system, and particularly for circuit breaker, the same problem exists for several other networks as well where plurality of nodes/modules communicate over a shared bus line.
[0008] Therefore, there is a need for a method and system for enabling simultaneous multi module communication among smart grid devices.

OBJECTS OF THE INVENTION
[0009] An object of the present disclosure is to provide method and system for enabling simultaneous communication of multiple modules.
[0010] Another object of the present disclosure is to reduce the delay/waiting time in multi-module communication system.
[0011] Another object of the present disclosure is to provide an equal opportunity to each module to send signal/data irrespective of the priority.
[0012] Another object of the present disclosure is to provide a robust and redundant method and system and method simultaneous multi-module communication that can detect any communication error.
[0013] Another object of the present disclosure is to provide a method and system for enabling simultaneous communication of multiple modules that is independent of any communication protocol or frame format.

SUMMARY
[0014] Aspects of present disclosure relate a method and system for enabling simultaneous multi mode communication over a shared channel/bus line. In an aspect, the proposed communication system includes a plurality of communication modules, a bus driver, and a bus line that is configured to connect the bus driver with the plurality of communication modules, wherein the bus driver receives data from the plurality of communication modules and integrates the data in a defined pattern to generate an output value based on which a voltage corresponding to the output value is identified such that the bus line is driven using the voltage.
[0015] In another aspect, the data from the plurality of communication modules can be in the form of a sequence of bits, and integration of the data can be performed by conversion of the sequence of bits of the plurality of communication modules at a given time instance into a decimal output value. In another aspect, the data from each of the plurality of communication modules can be integrated by positioning the data from the plurality of communication modules in the defined pattern and by computing the output value based on the pattern layout of the data from the plurality of communication modules.
[0016] In an aspect, the bus driver can issue a synchronous clock signal to each of the plurality of communication modules, wherein the plurality of communication modules can send their data synchronously to the bus driver based on the clock signal. In another aspect, the bus driver can store the data from the plurality of communication modules in a main register.
[0017] In yet another aspect, each of the plurality of communication modules can be assigned a bit position in the main register, wherein the plurality of communication modules can be aware of their respective bit positions. In yet another aspect, the pattern indicates the bit position for the data from each of the plurality of communication modules.
[0018] In an embodiment, the voltage can be sensed by ADC of the plurality of communication modules and can be decoded back by the plurality of communication modules, wherein at least one of the plurality of communication modules can sense the voltage as a sample and store the sample in a receive buffer. In an aspect, receive buffer of the at least one of the plurality of communication modules can check for a start signature that is indicative of the communication module sending a message.
[0019] The present disclosure further relates to a method having the steps of receiving, at a bus driver, data from a plurality of communication modules, and integrating, at the bus driver, the data in a defined pattern to generate an output value based on which a voltage corresponding to the output value is identified such that a bus line that is operatively coupled to the bus driver and to the plurality of communication modules is driven using the voltage.
[0020] In an embodiment, the present disclosure provides a method for enabling simultaneous multi module communication over a shared channel/bus line, wherein the method includes the steps of receiving, at a bus driver, binary values of data sequence from one or more modules attempting to send data/signal over a shared channel/bus line, combining and storing at the bus driver, the binary values received from one or more modules in a main register of configurable size, wherein the binary values received from one or more modules can be stored at an assigned bit position in the main register, and driving, by the bus driver, a shared bus line to a unique voltage value. In an embodiment, the unique voltage value can be determined by a digital to analog circuit of appropriate resolution based on the binary values of the main register.
[0021] In an embodiment, the method can further include the steps of receiving the unique voltage value by one or more modules, converting the unique voltage value at each of the one or more module into corresponding binary value a analog to digital circuit, storing binary values at each of the one or more modules in a receive registers allocated to each of the one or more modules, checking the binary values of receive registers allocated to each of the one or more modules to identify message start signature or message end signature, storing the binary values of receive register in a corresponding data buffer allocated to each of the one or more modules in case of match in message start signature and processing the binary values stored in corresponding data buffer allocated to each of the one or more modules in case of match in message end signature.
[0022] In an embodiment, the present disclosure provides a system for enabling simultaneous multi module communication over a shared channel. The system can include a digital value receiving module configured to receive, at a bus driver, binary values of data sequences from one or more modules, a register module that is configured to combine and store, at the bus driver, the binary values received from one or more modules in a main register of configurable size, wherein the binary values received from one or more modules can be stored at an assigned bit position in the main register, and a bus driver module that is configured to drive a bus line shared by the one or more modules to a unique voltage value, wherein the unique voltage value can be determined by a digital to analog circuit of appropriate resolution based on the binary values of the main register.
[0023] In an embodiment, system of the present disclosure can further include an analog to digital circuit that is configured to receive the unique voltage value at each of the one or more modules and determine corresponding binary values of received unique voltage value. System can further include a local register module at each of the one or more communication modules that is configured to store binary values in a receive register that is allocated for each of the one or more communication modules. System can further include a signature determination module configured to determine message start signature or message end signature in the binary values of receive registers allocated for each of the one or more communication modules. System can further include a buffer module configured to store the binary values of receive register in a corresponding data buffer allocated for each of the one or more communication modules in case of a match in message start signature. System of the present disclosure can further include a data processing module configure to process the binary values stored in corresponding data buffer allocated for each of the one or more modules in case of a match in message end signature.
[0024] In an embodiment, the assigned bit position of one or more modules in the main register can be known to the one or more modules so that the binary value of data sequence sent from a particular module can be reconstructed by other modules.
[0025] In an embodiment, the bus driver can be configured to send a synchronous clock signal, also referred as clock edge, to the one or more modules to initiate transmission of binary values of data sequence. One or more of the communication modules start sending the signal/data only after receiving the clock edge. In an example implementation, one more communication modules send binary values of data sequence synchronously to the bus driver.
[0026] In an example implementation, the unique voltage value can be determined by a digital to analog circuit of appropriate resolution based on maximum voltage of the bus and number of one or more communication modules. In an example implementation, the digital to analog converter can generate 2n unique voltage values, where n is the size of main register. In an example implementation, size of main register can be equal to the number of modules communicating over shared channel/bus line.
[0027] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components

BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0029] FIG. 1 illustrates architecture of multi module communication system design in accordance with an embodiment of the present disclosure.
[0030] FIG. 2 illustrates a concordance table of binary values, decimal values and unique voltage values in accordance with an embodiment of the present disclosure.
[0031] FIG. 3 illustrates an example of simultaneous multi module communication in accordance with an embodiment of the present disclosure.
[0032] FIG. 4 illustrates an example plot of unique voltage values of shared bus driven by the bus controller in accordance with an embodiment of the present disclosure.
[0033] FIG. 5 illustrates an example flow diagram of method for simultaneous multi module communication in accordance with an embodiment of the present disclosure.
[0034] FIG. 6 illustrates an example flow diagram of method for receiving the unique voltage values and determining the message from the unique voltage values in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0035] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0036] Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the “invention” may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the “invention” will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[0037] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0038] All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0039] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0040] Aspects of present disclosure relate a method and system for enabling simultaneous multi mode communication over a shared channel/bus line. In an aspect, the proposed communication system includes a plurality of communication modules, a bus driver, and a bus line that is configured to connect the bus driver with the plurality of communication modules, wherein the bus driver receives data from the plurality of communication modules and integrates the data in a defined pattern to generate an output value based on which a voltage corresponding to the output value is identified such that the bus line is driven using the voltage.
[0041] In another aspect, the data from the plurality of communication modules can be in the form of a sequence of bits, and integration of the data can be performed by conversion of the sequence of bits of the plurality of communication modules at a given time instance into a decimal output value. In another aspect, the data from each of the plurality of communication modules can be integrated by positioning the data from the plurality of communication modules in the defined pattern and by computing the output value based on the pattern layout of the data from the plurality of communication modules.
[0042] In an aspect, the bus driver can issue a synchronous clock signal to each of the plurality of communication modules, wherein the plurality of communication modules can send their data synchronously to the bus driver based on the clock signal. In another aspect, the bus driver can store the data from the plurality of communication modules in a main register.
[0043] In yet another aspect, each of the plurality of communication modules can be assigned a bit position in the main register, wherein the plurality of communication modules can be aware of their respective bit positions. In yet another aspect, the pattern indicates the bit position for the data from each of the plurality of communication modules.
[0044] In an embodiment, the voltage can be sensed by ADC of the plurality of communication modules and can be decoded back by the plurality of communication modules, wherein at least one of the plurality of communication modules can sense the voltage as a sample and store the sample in a receive buffer. In an aspect, receive buffer of the at least one of the plurality of communication modules can check for a start signature that is indicative of the communication module sending a message.
[0045] The present disclosure further relates to a method having the steps of receiving, at a bus driver, data from a plurality of communication modules, and integrating, at the bus driver, the data in a defined pattern to generate an output value based on which a voltage corresponding to the output value is identified such that a bus line that is operatively coupled to the bus driver and to the plurality of communication modules is driven using the voltage.
[0046] In an embodiment, the present disclosure provides a method for enabling simultaneous multi module communication over a shared channel/bus line, wherein the method includes the steps of receiving, at a bus driver, binary values of data sequence from one or more modules attempting to send data/signal over a shared channel/bus line, combining and storing at the bus driver, the binary values received from one or more modules in a main register of configurable size, wherein the binary values received from one or more modules can be stored at an assigned bit position in the main register, and driving, by the bus driver, a shared bus line to a unique voltage value. In an embodiment, the unique voltage value can be determined by a digital to analog circuit of appropriate resolution based on the binary values of the main register.
[0047] In an embodiment, the method can further include the steps of receiving the unique voltage value by one or more modules, converting the unique voltage value at each of the one or more module into corresponding binary value a analog to digital circuit, storing binary values at each of the one or more modules in a receive registers allocated to each of the one or more modules, checking the binary values of receive registers allocated to each of the one or more modules to identify message start signature or message end signature, storing the binary values of receive register in a corresponding data buffer allocated to each of the one or more modules in case of match in message start signature and processing the binary values stored in corresponding data buffer allocated to each of the one or more modules in case of match in message end signature.
[0048] In an embodiment, the present disclosure provides a system for enabling simultaneous multi module communication over a shared channel. The system can include a digital value receiving module configured to receive, at a bus driver, binary values of data sequences from one or more modules, a register module that is configured to combine and store, at the bus driver, the binary values received from one or more modules in a main register of configurable size, wherein the binary values received from one or more modules can be stored at an assigned bit position in the main register, and a bus driver module that is configured to drive a bus line shared by the one or more modules to a unique voltage value, wherein the unique voltage value can be determined by a digital to analog circuit of appropriate resolution based on the binary values of the main register.
[0049] In an embodiment, system of the present disclosure can further include an analog to digital circuit that is configured to receive the unique voltage value at each of the one or more modules and determine corresponding binary values of received unique voltage value. System can further include a local register module at each of the one or more communication modules that is configured to store binary values in a receive register that is allocated for each of the one or more communication modules. System can further include a signature determination module configured to determine message start signature or message end signature in the binary values of receive registers allocated for each of the one or more communication modules. System can further include a buffer module configured to store the binary values of receive register in a corresponding data buffer allocated for each of the one or more communication modules in case of a match in message start signature. System of the present disclosure can further include a data processing module configure to process the binary values stored in corresponding data buffer allocated for each of the one or more modules in case of a match in message end signature.
[0050] In an embodiment, the assigned bit position of one or more modules in the main register can be known to the one or more modules so that the binary value of data sequence sent from a particular module can be reconstructed by other modules.
[0051] In an embodiment, the bus driver can be configured to send a synchronous clock signal, also referred as clock edge, to the one or more modules to initiate transmission of binary values of data sequence. One or more of the communication modules start sending the signal/data only after receiving the clock edge. In an example implementation, one more communication modules send binary values of data sequence synchronously to the bus driver.
[0052] In an example implementation, the unique voltage value can be determined by a digital to analog circuit of appropriate resolution based on maximum voltage of the bus and number of one or more communication modules. In an example implementation, the digital to analog converter can generate 2n unique voltage values, where n is the size of main register. In an example implementation, size of main register can be equal to the number of modules communicating over shared channel/bus line.
[0053] FIG. 1 illustrates an exemplary architecture of the multi module communication system design in accordance with an embodiment of the present disclosure. As shown in the FIG. 1, module 1 102-1, module 2 102-2, module 3 102-3 and module N 102-N, collectively and interchangeably also referred as multi modules 102, can be connected through a common bus line 106 that works as a shared bus line for multiple modules 1 102. The method of present disclosure can be used to provide/enable simultaneous data/signal transfer by multi modules 102 through a common bus line 106, also known as shared bus line 106. To enable a simultaneous data transfer by multi modules, means to enable a capability for multiple modules 102 to transfer data/signal at the same time without much delay, a bus driver 104 working as the scheduler and/multiplexer for shared bus line 102 can be incorporated in the network. In an example implementation, the bus driver 104 sends a clock edge signal to one or more modules 102 to start sending the data/signal in a synchronous manner, wherein the modules 102, on receipt of the clock edge, start sending data through their Tx pins over Rx pin of the bus driver 104. The bus driver 104 can receive a synchronous data in form or binary values (“0” or “1”) from one or more modules 102 in a main register 108 at a fixed position assigned for each of the one or more modules 102. For example, binary value received from module 1 102-1 can always be stored at 1st position in main register 108, binary value received from module 2 102-2 can always be stored at 2nd position in main register 108, binary value received from module 3 102-3 can always be stored at 3rd position in main register 108, and similarly binary value received from module 102-N can always be stored at Nth position in the main register 108. In an example implementation, size of the register 108 can be equal to the number of modules 102 sharing a common bus 106.
[0054] In an example implementation, each module of the modules 102 can be assigned a bit position in the main register 108 i.e. the data from module 1 is stored in LSB bit of the main register 108, while data from module 2 is stored in the second bit of the register and so on. At every clock cycle, the bus drive 106 can take the binary values stored in register 108 and drive the bus line 106 to a corresponding unique voltage values as converted by a Digital to analog converter (DAC) . The corresponding unique voltage value to drive the share bus 106 can be determined by DAC based on the value stored in the register 108. One may appreciate that the values stored in the main register 108 are binary values received from multiple modules of modules 102, and not from a single module and hence the corresponding unique voltage value at which the bus driver 104 drives the bus 106 represents a combined signal of data multiplexed from all the participating modules 102. One can appreciate that the single bus line carries the combined data for multiple modules simultaneously. In an example implementation, the bus driver 104 can identify the pattern of the data and accordingly drives the shared bus 106 to a corresponding unique voltage through software logics. In an example implementation, each pattern, set of binary values can be assigned a unique voltage value.
[0055] On receiving the unique voltage value at ADC pins of the modules, the ADC attached with each module can convert the unique voltage value to the corresponding binary values, and store the binary values in respective receive registers allocated for each of the modules 102. For example, first bit of the binary values can be stored in the first receive register allocated for module 1 102-1, second bit of the binary value can be stored in the second receive register allocated for module 2 102-2, third bit of the binary value can be stored in the second received register allocated for module 3 102-3, and similarly Nth bit of binary value can be stored in the Nth receive register allocated for module 102-N. One can appreciate that the number of receive registers at each module can be equal to the number of participating modules 102.
[0056] In an example implementation, each module 102 when powered on, configures its peripherals and waits for the clock edge to be received from the driver 104, and at reception of clock edge, these modules 102 can start sampling the bus data and start transmitting ‘0’ on Tx line. In an example implementation, series of Bit ‘0’ may represent idle state on the bus. Whenever any of the modules 102 has data/message to be sent to another module of the network through shared bus 106, the transmitter module starts sending its message with a ‘start of message’ signature. Similarly, ‘end of message’ signal can also be sent by the transmitter module to indicate the end of message. In an example implementation, ‘start of message’ signal can be can be just a single Bit ‘1’ or a combination of multiple bits. Similarly the ‘end of message’ signal, which indicates the end of message, can be a continuous bit ‘0’ or any pre-defined format.
[0057] In an example implementation, module 102 can sense the unique voltage level/values as a sample, and convert the sample into digital data/binary values of which each bit corresponds to the bits transmitted by corresponding modules. These bits can be stored in ‘Receive Buffers’ dedicated for each of the one or more modules. At the next sample, another bit can be added into each receive buffer in the corresponding receive register based on the bit location of converted binary values. The receiving module can check for ‘Start Signature’ match, and if a match is detected in a particular receive buffer, it indicates that the corresponding module has started sending a message. In an example implementation, at the next sample, the receiving module can store the bit received from the corresponding sender module in the corresponding ‘Data Buffer’ assigned for each of the one or more modules. In an example implementation, for the subsequent samples followed by ‘start of message’ signal, the ‘Data Buffer’ of that corresponding module can store data bits and the receiver module can keep checking for ‘end of message’ signature, which indicates the end of a message. After the ‘end of message’ signature is matched, data in the ‘Data Buffer’ for that corresponding module can be sent for further processing.
[0058] One can appreciate that, using the teaching of present disclosure, the modules 102 sharing a common bus may not have to wait for bus to get ‘Idle’ to start sending a message. This in turn reduces overall wait time for all the modules, and assures equal opportunity for each module to send a message.
[0059] One can also appreciate that the converted binary values form of the sampled unique voltage level at any module 102 also reflects the data bit transmitted by itself, and hence allows a transmitter module to monitor its own transmitted data. This allows detection of an error on the bus line so that the corrective action can be taken in response.
[0060] In an example implementation, resolution of ADC and DAC circuit can be higher based on the number of module 102 sharing a common bus 106. In an example implementation, the unique voltage value can be determined by a digital to analog circuit of appropriate resolution based on maximum voltage of the shared bus 106 and number of modules 102. In an example implementation, the digital to analog converter can generate 2n unique voltage values, where n is the size of main register or the number of modules 102 sharing the common bus 106. For decoding the unique voltage values, analog to digital (ADC) circuit of equal resolution can be attached with each of the modules.
[0061] FIG. 2 illustrates a concordance table of binary values, decimal values and unique voltage values in accordance with an embodiment of the present disclosure. As shown the concordance table 200, for different binary values 202, corresponding decimal values 204 and unique voltage values 206 can be determined by the bus driver. FIG. 2 illustrates an example concordance table where the maximum voltage at which the shared bus can be driven is 5V and there are four modules connected in the network sharing a common bus. For four modules sending the signal/data simultaneously, there may be 16 (24) unique values. Similarly if there are five modules sending the signal/data simultaneously, there may be 32 unique values. For a network having four modules connected to a shared bus, 16 unique voltage values can be equally spaced apart. For example, for binary value 0000 in main register, the corresponding unique voltage value can be 0, for binary value 0001 the corresponding unique voltage value can be 0.333V, for binary value 0010 the corresponding unique voltage value can be 0.667V, and so on for binary value of 1111, the unique voltage value can be 5V.
[0062] In an example implementation, DAC circuit of bus driver can drive the shared bus based on the values stored in the main register, wherein the values stored in the main register can be combination of binary values received from multiple modules.
[0063] FIG. 3 illustrates an example of simultaneous multi module communication in accordance with an embodiment of the present disclosure. As illustrated, binary values received from modules can be stored in the main register at every clock cycle and the corresponding unique voltage values can be determined for driving the shared bus. As shown in FIG. 1, at clock 1, binary value 0 is received from module 1 302, binary value 1 is received from module 2 304, binary value 0 is received from module 3 306 and binary value 0 is received from module 4 308. Binary values received from different modules are stored in main register, which has value 0010. The bus driver can then convert the binary value stored in the main register in corresponding decimal value and corresponding unique voltage values to drive the share bus. To transfer the data received from multiple modules at clock 1, which is stored in the main register as “0010”, the bus driver can drive the shared bus at 0.667v. Similar to transfer the binary value “0011” stored in the main register during clock 2, the bus driver can drive the shared bus at 1V, to transfer the binary values “0101” stored in the main register during clock 3, the bus driver can drive the shared bus at 1.667v, and so on to transfer the binary value “1110” stored in main register during clock 12, the bus driver can drive the shared bus at 4.667v.
[0064] FIG. 4 illustrates an example plot of unique voltage values of shared bus driven by the bus controller in accordance with an embodiment of the present disclosure. The plot of unique voltage values is illustrated for 12 clock cycles as driven by the bus driver based on the binary values stored in the main register of bus driver at different clock cycle.
[0065] FIG. 5 illustrates an example flow diagram 500 of a method for simultaneous multi module communication in accordance with an embodiment of the present disclosure. As shown the flow diagram 500, the method for simultaneous multi module communication includes step 502 of receiving at the bus driver, binary values of data sequences from one or more modules. Step 504 includes combining and storing, at the bus driver, the binary values received from one or more modules in a main register, wherein the binary values received from one or more modules are stored at an assigned bit position in the main register. At step 606, driving, by the bus driver, a bus line shared by the one or more modules to a unique voltage value, wherein the unique voltage value is determined by a digital to analog circuit of appropriate resolution based on the binary values of the main register.
[0066] At steps 602, the bus driver receives bit values of data sequences of one or modules in synchronous manner. In an example implementation, the bus driver sent clock edge signal to one more modules to initiate data/signal transmission and hence clock is synchronized.
[0067] At step 604, the bus driver stores bit values receive at a particular clock from one or more module in the main register at a fixed bit location. In example implementation, the main register can have a fixed position for storing bit values received from a particular module. For example, the bus register can always store bit value received from module 1 at first bit position, bit value received from module 2 at second bit position and bit value received from module-N at Nth bit position.
[0068] At step 606, a DAC circuit over the bus driver can convert the bit values stored in the main register form of an analog signal represented by unique voltage value. The bus driver can drive the shared us at converted unique voltage value. The unique voltage values can be sensed by all the attached modules which can decode the unique voltage values to get the corresponding binary values and assemble them to determine the data/message sent by one or more modules.
[0069] FIG. 6 illustrates an example flow diagram of method for receiving the unique voltage values and determining the message from the unique voltage values in accordance with an embodiment of the present disclosure. The flow chart 600 illustrates the process steps that may be taken at the receiving modules that sense the unique voltage values and decode the unique values to get the corresponding binary values, assemble the binary value in respective data buffer assigned for one or more module, and determine the message sent by one or more modules.
[0070] At step 602, the unique voltage value is received by one or more communication modules, wherein, at step 604, binary values corresponding to the received voltage value is determined at the one or more modules, wherein the corresponding binary values can be determined by an analog to digital circuit of appropriate resolution based on the unique voltage value.
[0071] At step 606, the binary values can be stored in the respective receive registers of the one or more modules.
[0072] At step 608, it is checked as to whether ‘start of message’ signal is received by any of the communication modules such that if the ‘start of message’ signal is received, at step 610, subsequent binary values can be stored in data buffer of respective communication modules. At step 612, it is checked if ‘end of message’ signal is received by the communication module(s) such that if the ‘start of message’ signal is received, at step 614, binary values stored in the data buffers of respective communication modules can be processed.
[0073] In an example implementation, if the ‘start of message’ signal is not received, the binary values can be kept on the receive register only. On receiving the ‘start of message’ signal, the receiving module can keep storing the subsequent binary values in data buffer until the ‘end of message’ is received.
[0074] In an example implementation, each module when powered on, configures its peripherals and waits for the clock edge to be received from the bus driver and at reception of clock edge, these modules can start sampling the bus data and start transmitting ‘0’ on Tx line. In an example implementation, series of Bit ‘0’ may represent idle state on the bus. Whenever the any of the module have to sent data/message to another module of the network trough shared bus, the transmitter module starts sending its message with a ‘start of message’ Signature. Similarly, an ‘end of message’ signal can also be sent by the transmitter module to indicate the end of message. In an example implementation, the ‘start of message’ signal can be just a single Bit ‘1’ or a combination of multiple bits. Similarly the ‘end of message’ signal, which indicates the end of message, can be a continuous bit ‘0’.
[0075] In an example implementation, receiving module senses the unique voltage level/values as a sample and converts into digital data/binary values of which each bit will correspond to the bits transmitted by corresponding modules. These bits are stored in ‘Receive Buffers’ dedicated for each of the one or more modules. At the next sample, another bit will be added into each Receive Buffers in the corresponding receive register based on the bit location of converted binary values. The receiving module checks for ‘Start Signature’ match, and if a match is detected in a particular receive buffer it indicates that the corresponding module has started sending a message. In an example implementation, at the next sample, the receiving module will store the bit received from the corresponding sender module in the corresponding ‘Data Buffer’ assigned for each of the one or more modules. In an example implementation, for the subsequent samples followed by ‘start of message’ signal , the ‘Data Buffer’ of that corresponding module will be storing data bits and the receiver module will keep checking for ‘end of message’ Signature which indicates the end of a message. After ‘end of message’ signature is matched, the data in the ‘Data Buffer’ for that corresponding module can be sent for further processing.
[0076] One can appreciate that, using the teaching of present disclosure, the modules 102 sharing a common bus may not have to wait for bus to get ‘Idle’ to start sending a message. This in turn will reduce overall wait time for all the modules and assures equal opportunity for each module to send a message.
[0077] One can also appreciate that the converted binary values of the sampled unique voltage level also reflect the data bit transmitted by itself and hence allows a transmitter module to monitor its own transmitted data. This allows detection of an error on the bus line so that the corrective action can be taken in response.
[0078] In an aspect, the proposed system is designed to be a synchronous communication system, where the bus driver is the master, which provides clock to each module. Each module when powered on can configure its peripherals and wait for the clock edge to be received from the bus driver. At the reception of the clock edge, modules can start sampling the bus data and start transmitting ‘0’ on Tx line. Series of Bit ‘0’ will be the idle state on the bus. A module starts sending its message with a ‘Start Signature’, which can be just a single Bit ‘1’ or a combination of multiple bits. Similarly, there can be a ‘Stop Signature’ defined, which can indicate the end of message and after that the module will again keep sending bit ‘0’.
[0079] Reception of data involves a module senses a voltage level as a sample, which it can convert into digital data of which each bit can correspond to the bits transmitted by corresponding modules. These bits can be stored in ‘Receive Buffers’ dedicated for each module. At the next sample, another bit will be added into each receive buffers. The receiving module checks for ‘Start Signature’ matching. If a match is detected in a particular receive buffer, it indicates that the corresponding module has started sending a message. Now at the next sample, the receiving module will store the bit received from the corresponding sender module in its dedicated ‘Data Buffer’.
[0080] After that for the further samples, the ‘Data Buffer’ of that corresponding module will be storing data bits and the receiver module will keep checking for ‘Stop Signature’, which indicates the end of a message. After ‘Stop Signature’ is matched, the data in the ‘Data Buffer’ for that corresponding module will be sent for further processing.
[0081] Above paragraph explains reception process of one message. Since the AB Bus line allows multiple modules to send data bits, any other module can also start sending a message with the ‘Start Signature’. The module is constantly sampling the bus voltage and storing the bits received from every other module. Hence it can sense a ‘Start Signature’ from a second module in the middle of the first message too. After that all it has to do is start storing bits for 2 modules in the 2 dedicated ‘Data Buffers’. Hence a module on the bus need not wait for bus to get ‘Idle’ to start sending a message. This in turn will reduce overall wait time for all the modules and assures equal opportunity for each module to send a message.
[0082] When a module is sending data bits, it also is sampling the data on the bus line simultaneously. Hence the digital form of the sampled voltage level will also reflect the data bit transmitted by it. This allows a module to monitor its own transmitted data, which is used to detect an error on the bus line, and corrective action can be taken in response.
[0083] This communication system highlights its physical layer feature which allows the modules on the bus to communicate to each other at any time without data congestion on the bus as explained above in detail. This system is not limited to any specific communication protocol, which allows the designer to incorporate the invention with other protocols for higher levels of communication layers.
[0084] In an aspect, the present disclosure enables simultaneous communication of multiple modules. The present disclosure also reduces the delay in multi-module system, as each module can communicate without waiting for others to finish their communication and leave the control of the bus line. Each module can also have equal opportunity to communicate. Due to their capability of simultaneous communication, the present disclosure reduces the complexity in the system as all the critical data is sent without any delay. Furthermore, the proposed system is robust and redundant as the sent message is received by the sending module, it comes to know if any error or corruption of data if occurred. Accordingly it can take corrective action. It is not limited to any protocol or the frame format, rather it can be implemented with any protocol.
[0085] The method and system of present disclosure provides a physical layer feature that allows the modules on the shared bus to communicate with each other at any time without data congestion on the bus. This system is not limited to any specific communication protocol, which allows the designer to incorporate the invention with other protocols for higher levels of communication layers.
[0086] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0087] The present disclosure overcomes disadvantages associated with conventional multi module communication and enables simultaneous communication of multiple modules over a shared bus.
[0088] The present disclosure provides a method and system for simultaneous communication that reduces the delay/waiting time in multi-module communication.
[0089] The present disclosure provides an equal opportunity to each module to send signal/data irrespective of the priority
[0090] The present disclosure provides a robust and redundant method and system and method simultaneous multi-module communication that can detect any communication error.
[0091] The present disclosure to provide a method and system for enabling simultaneous communication of multiple modules that is independent of any communication protocol or frame format.