DESC:FORM – 2

THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003

COMPLETE SPECIFICATION
(SEE SECTION 10, RULE 13)

SINGLE CHIP X-BAND POWER AMPLIFIER

BHARAT ELECTRONICS LIMITED
WITH ADDRESS:
OUTER RING ROAD, NAGAVARA, BANGALORE 560045, KARNATAKA, INDIA

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.
TECHNICAL FIELD
[0001] The present invention relates to X-band power amplifier. The invention, more particularly, relates to X-band gallium arsenide (GaAs) monolithic microwave integrated circuit (MMIC) power amplifier.
BACKGROUND
[0002] X-band refers to a range of frequencies used in radio wave communication. X-band amplifiers are used to amplify modulated signals prior to transmission. To ensure efficient radio wave communication, X-band amplifiers having sufficient power gain, output power and high power-added efficiency (PAE) are essential.
[0003] CN103812458A titled “X-Wave Band Single-Chip Power Amplifier” mentions a X-band monolithic power amplifier which consists of an input matching circuit, a power distribution circuit, a three-level pHEMT amplifier, a power synthesis circuit and an output matching circuit integrated on the single chip. The Amplifier uses 0.25 µm Gallium Arsenide (GaAs) pHEMT T-gate process and is a single-chip of size 4.4 X 4.1 mm used in X-band radar and microwave communications systems.
[0004] US6359515B1 titled “MMIC Folded Power Amplifier” mentions a MIMIC power amplifier with a folded configuration. It introduces a methodology of using shared FETs. The amplifier configuration provides a multi-sectional configuration wherein one section may be the mirrored image of another. In a two section amplifier, the amplifier appears to be “folded.” The power amplifier disclosed may be suitable for ground based Ka-band transmitters operating between about 26.5 GHZ and 32 GHz.
[0005] US6259337B1 titled “High efficiency flip-chip monolithic microwave integrated circuit power amplifier” mentions a coplanar waveguide structure for use with an MMIC high power amplifier. The coplanar waveguide structure consists of a coplanar transmission line segment having more than two ground plane electrodes and a plurality of signal/dc current carrying electrodes. The coplanar waveguide structure forms an inductor for the MMIC high power amplifier, and makes use of closely spaced, parallel coplanar waveguide segments shorted at one end to form a shunt inductor at the output of high power flip-chip, MMIC amplifier.
[0006] CN104158503A titled “X-waveband power amplifier based on GaN” describes kind of GaN based X-band power amplifier by load pull method and input terminal matching conjugate to solve the negative resistance problems of transistors port. The power amplifier operates with bandwidth of 3.6 ~ 8.0 GHz, has maximum gain of 11.04 dB, maximum output power of 33 dBm, maximum PAE of 29.2%, the relatively small voltage standing wave.
[0007] From above referred prior art, US6359515B1 mentions techniques to reduce die size but does not detail the techniques to integrate the same in a single chip power amplifier for focused specifications. US6259337B1 provides ways to increase efficiency, but it requires use of external components to achieve the same. This leads to increase in layout area.
[0008] CN104158503A proposes GaN technology to achieve broad-band performance. However, though GaN is superior to GaAs in efficiency and power, it is not cost effective and requires higher supply voltage to achieve the same. CN103812458A mentions a single chip X-Band three stage power amplifier based on GaAs pHEMT realized in 4.1 X 4.4 mm die size. However, the achieved efficiency, gain and power and are not clearly detailed across the X-Band.
[0009] There is therefore felt a need of an invention which provides a single chip X-band power amplifier that solves the above mentioned problems associated with prior art X-band power amplifiers.
SUMMARY
[0010] This summary is provided to introduce concepts of the invention related to a single chip X-band power amplifier, as disclosed herein. This summary is neither intended to identify essential features of the invention as per the present invention nor is it intended for use in determining or limiting the scope of the invention as per the present invention.
[0011] In accordance with an embodiment of the present invention, there is provided a single chip X-band power amplifier. The amplifier comprises an input matching network configured to receive an external radio frequency (RF) input signal and match the 50 Ohm RF impedance to a predefined input impedance, a first stage amplifier configured to amplify the RF input signal, a first power divider configured to divide the power of the amplified signal from the first stage amplifier, a driver stage amplifier configured to amplify each power divided signal from the first power divider, a second power divider configured to divide the power of each amplified signal from the driver stage amplifier, an output stage amplifier configured to amplify each power divided signal from the second power divider, and a power combiner configured to combine the power of each amplified signal from the output stage amplifier and match the combined power to a predefined output impedance.
[0012] In an aspect, the amplifier is fabricated on a GaAs (gallium arsenide) substrate by a 0.25 µm pHEMT (pseudomorphic high electron mobility transistor) process with a die size of 4.4 X 3.3 mm.
[0013] In an aspect, the first stage amplifier has a single field effect transistor (FET) having gate periphery of 8 X 150 µm, and the predefined input impedance is the input impedance of the single FET.
[0014] In an aspect, the driver stage amplifier has four FET’s each having gate periphery of 8 X 150 µm, and the first power divider is further configured to match the power of the amplified signal from the first stage amplifier to the input impedance of each FET of the driver stage amplifier.
[0015] In an aspect, the output stage amplifier has eight FET’s each having gate periphery of 12 X 250 µm, and the second power divider is further configured to match the power of each amplified signal from the driver stage amplifier to the input impedance of each FET of the output stage amplifier.
[0016] In an aspect, the predefined output impedance is 50 Ohms RF impedance.
[0017] In an aspect, the amplifier includes a single gate bias for all the FET’s in each stage and a single drain bias for all the FET’s in each stage.
[0018] In an aspect, the amplifier, for maintaining stability, includes a plurality of series resistors connected to the gates of the FET’s and a plurality of parallel resistors in the input matching network, the power dividers and the power combiner.
[0019] In an aspect, each series resistor is an Ohmic resistor of 2 Ohm/sq. sheet resistance, and each parallel resistor is a tantalum nitride resistor of 50 Ohm/sq. sheet resistance.
[0020] In an aspect, the harmonics of the amplifier are tuned by employing active load pull analysis.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0021] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
[0022] Figure 1 illustrates a block diagram depicting architecture of an X-band GaAs MMIC power amplifier, according to an exemplary embodiment of the present invention.
[0023] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present invention. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION
[0024] The various embodiments of the present invention describe about an X-band GaAs monolithic microwave integrated circuit (MMIC) power amplifier.
[0025] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.
[0026] However, the amplifier is not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the present invention and are meant to avoid obscuring of the present invention.
[0027] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0028] In one of the embodiments, the X-Band GaAs MMIC power amplifier (100) as disclosed herein is a single chip having die size of 4.4 mm X 3.3 mm ultra-efficient, high power amplifier with high gain, operated in drain pulsed condition, using 0.25 µm GaAs pHEMT (pseudomorphic high electron mobility transistor) process in X-band. The single chip X-band power amplifier (100) comprises at least three stages of amplifiers and multiple stages of matching networks / power dividers / combiners. The amplifier comprises an input matching network (101), a first stage amplifier (102), a first power divider (103), a driver stage amplifier (104), a second power divider (105), an output stage amplifier (106), and a power combiner (107). The input matching network (101) is configured to receive an external radio frequency (RF) input signal and match the 50 Ohm RF impedance to a predefined input impedance. The first stage amplifier (102) is configured to amplify the RF input signal. The first power divider (103) is configured to divide the power of the amplified signal from the first stage amplifier (102). The driver stage amplifier (104) is configured to amplify each power divided signal from the first power divider (103). The second power divider (105) is configured to divide the power of each amplified signal from the driver stage amplifier (104). The output stage amplifier (106) is configured to amplify each power divided signal from the second power divider (105). The power combiner (107) is configured to combine the power of each amplified signal from the output stage amplifier (106) and match the combined power to a predefined output impedance.
[0029] The architecture of the single chip X-Band GaAs MMIC power amplifier (100) is illustrated figure 1. The architecture of X-Band three stage power amplifier (100) is realized on 0.25 µm D-mode GaAs pHEMT technology and fabricated on 100 µm thick wafer. The power amplifier is designed with FET cells having a typical power density of 1W/mm. Active load pull analysis has been employed and actual measured data for the FET cells has been used in the design of the amplifier (100) to extract enhanced performance in terms of power, efficiency and gain. The input matching network (101) connects the radio frequency input pin (RFIN) of the chip to input of the first stage amplifier (102). The first stage amplifier (102) consists of a single FET of 8 X 150 µm gate periphery. The input matching network (101) matches 50 Ohm RF impedance to the input impedance of the FET (102). The first power divider and inter-stage matching network (103), divides the power of the amplified signal from the first stage amplifier (102) and distributes the divided power from the first stage amplifier (102) to the driver stage amplifier (104) having four FET’s with gate periphery of 8 X 150 µm each. The inter-stage matching network in the first power divider (103) matches the output impedance of the first stage amplifier (102) to the input impedance of each of the four FET’s of the driver stage amplifier (104). The driver stage amplifier (104) amplifies each power divided signal from the first power divider (103). The output of the driver stage amplifier (104) is again divided and distributed by the second power divider and inter-stage matching network (105) and fed to the output stage (106) having eight FET’s of gate periphery 12 X 250 µm each. The inter-stage matching network in the second power divider (105) matches the output impedance of driver stage amplifier (104) to the input impedance of each FET of the output stage amplifier (106). The output stage amplifier (106) amplifies each power divided signal from the second power divider (105). The power of each amplified signal from the output stage amplifier (106) is combined using a novel power combiner (107) and matched to 50 Ohm output impedance by the output matching network of the power combiner (107).
[0030] The power amplifier (100) has been biased independently for each stage. Drain and gate bias for each stage has been brought out separately on the north and south side of the chip, to provide a single drain bias for all the FET’s in each stage and a single gate bias for all the FET’s in each stage. The front-end input stage of a single FET (102) has been designed to provide a gain of about 15 dB and the driver stage of four FET’s (104) has been designed to deliver a gain of about 12 dB. The design has been simulated for a gain of about 30 dB. The measured small signal gain of the power amplifier (100) is about 28 dB. With individual FET’s having high gain at low frequencies and the high target gain requirement of the power amplifier, stability issues were foreseen. Hence, for maintaining stability of the amplifier (100), Nyquist stability analysis was used based on which a plurality of series resistors have been connected to the gates of the FET’s (102, 104, and 106) and in biasing networks. For maintaining stability, a plurality of parallel resistors are included in input matching network (101), power dividers (103, 105) and power combiner (107).
[0031] The design was focused for high efficiency. This was accomplished by tuning the harmonics using active load pull for fundamental and harmonics. The input stage and driver stage FET’s (102, 104) have been sized for the required gain and drive required for output stage (106). Any excessive sizing of FET’s in these stages would have degraded the efficiency. Also, the inter-stage matching network was designed to see optimum load to extract maximum output power and to split/divide the signals to feed it to succeeding stages. The input matching network and output matching networks have included the effect of bond wires. Thermal management of the FET’s in particular and device in general are critical to achieve higher power added efficiency (PAE). Thermal analysis of individual FET structure and combined cells for different gate periphery and fingers were carried out. To achieve an optimum thermal dissipation in a reduced die size, factors like via sharing, gate to gate spacing were considered to further enhance the PAE.
[0032] The power amplifier (100) has been designed to ensure unconditional stability. Large signal stability analysis has been carried out for individual stages and a combination of ohmic resistor of 2 Ohm/sq. and tantalum nitride resistors of 50 Ohm/sq. sheet resistance as series resistors connected to the gates and as parallel resistors in matching networks, respectively, are included in the power amplifier (100). The decoupling network is designed using Nyquist stability to dampen low frequency oscillations. The matching networks are designed to suppress harmonics and produce optimum impedance to the fundamental by using MIM Capacitors of 600 pF/mm2 and 400 pF/mm2 and EM-simulated custom inductors.
[0033] Hence, techniques such as use of parallel resistors between two dividing/combining branches of matching networks to damp the odd mode oscillations have been incorporated. Additionally, Nyquist stability was checked for 50 Ohm and open load conditions without introducing additional losses and degraded performance. Thermal stack build-up of 0.25 µm pHEMT FET cell and sizing of gate periphery is based on thermal simulations to extract higher efficiency and power.
[0034] Further an optimum via sharing configuration has been employed for reduced thermal coupling without introducing phasing issues or reducing the transition frequency (Ft) of the FETs.
[0035] At least some of the technical advancements of the above disclosed single chip X-band power amplifier (100) include the following:
input power handling capability of +25 dBm minimum;
output power upto 13W and input, output impedance matched to 50 Ohms;
minimum of 40% PAE across 8.5-10.5 GHz (wafer Level) and in particular typical 42% PAE across 9-10 GHz;
output power of 40.5 dBm to 41.8 dBm across 8.5-10 GHz, and typical power of 41.0 dBm to 41.8 dB frequency range 9-10.0 GHz;
small signal gain of 27 dB to 30 dB across 8.5-10.5 GHz;
typical input return loss better than 12 dB and output return loss better than 10 dB across 8.5-10.5 GHz;
drain bias voltage of 7.5V to 8.5V with typical operation at 8V, and gate biasing voltage of -0.7V to -0.9V.
[0036] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:WE CLAIM:

1. A single chip X-band power amplifier (100) comprising:
an input matching network (101) configured to receive an external radio frequency (RF) input signal and match the 50 Ohm RF impedance to a predefined input impedance;
a first stage amplifier (102) configured to amplify the RF input signal;
a first power divider (103) configured to divide the power of the amplified signal from said first stage amplifier (102);
a driver stage amplifier (104) configured to amplify each power divided signal from said first power divider (103);
a second power divider (105) configured to divide the power of each amplified signal from said driver stage amplifier (104);
an output stage amplifier (106) configured to amplify each power divided signal from said second power divider (105); and
a power combiner (107) configured to combine the power of each amplified signal from said output stage amplifier (106) and match the combined power to a predefined output impedance.

2. The amplifier (100) as claimed in claim 1, wherein said amplifier (100) is fabricated on a 100 µm thick GaAs (gallium arsenide) substrate by a 0.25 µm pHEMT (pseudomorphic high electron mobility transistor) process with a die size of 4.4 X 3.3 mm.

3. The amplifier (100) as claimed in claim 1, wherein said first stage amplifier (102) has a single field effect transistor (FET) having gate periphery of 8 X 150 µm.

4. The amplifier (100) as claimed in claims 1 and 3, wherein said predefined input impedance is input impedance of said single FET (102).

5. The amplifier (100) as claimed in claim 1, wherein said driver stage amplifier (104) has four FET’s each having gate periphery of 8 X 150 µm.

6. The amplifier (100) as claimed in claims 1 and 5, wherein first power divider (103) is further configured to match the output impedance of said first stage amplifier (102) to the input impedance of each FET of said driver stage amplifier (104).

7. The amplifier as claimed in claim 1, wherein said output stage amplifier (106) has eight FET’s each having gate periphery of 12 X 250 µm.

8. The amplifier (100) as claimed in claims 1 and 7, wherein said second power divider (105) is further configured to match the output impedance of said driver stage amplifier (104) to the input impedance of each FET of said output stage amplifier (106).

9. The amplifier (100) as claimed in claim 1, wherein said predefined output impedance is 50 Ohms.

10. The amplifier (100) as claimed in claims 1 to 9, wherein said amplifier includes a single gate bias for all said FET’s in each stage and a single drain bias for all said FET’s in each stage.

11. The amplifier as claimed in claims 1 to 9, wherein said amplifier, for maintaining stability thereof, includes:
a plurality of series resistors connected to the gates of said FET’s, and
a plurality of parallel resistors in said input matching network (101), said power dividers (103, 105) and said power combiner (107).

12. The amplifier as claimed in claim 11, wherein each series resistor is an Ohmic resistor of 2 Ohm/sq. sheet resistance, and each parallel resistor is a tantalum nitride resistor with 50 Ohm/sq. sheet resistance.

13. The amplifier as claimed in claims 1 to 9, wherein harmonics of said amplifier (100) are tuned by employing active load pull analysis.

Dated this 30th day of March, 2019
FOR BHARAT ELECTRONICS LIMITED

By their Agent)

D. MANOJ KUMAR (IN/PA-2110)
KRISHNA & SAURASTRI ASSOCIATES LLP