TECHNICAL FIELD
The present disclosure generally relates to signal processing systems in RADARS. More specifically, the present disclosure relates to RADAR applications having both down conversion block and pulse compression block in a single filter thereby affording enhanced performance.
BACKGROUND
Background description includes information that can be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
In typical RADAR (used interchangeably with "radars" and its derivative words with regards to their respective meanings) applications, Digital Down Conversion (DDC) acts as a front end for signal processing applications and followed by Digital Pulse Compression (DPC). Both DDC and DPC are implemented in separate filters, sometimes even in separate modules. A generic architecture for DDC is shown in FIG. 1.
An ADC samples the detected analog signal and feeds the same into the DDC processing chain. In the DDC, a mixer is used in combination with a vector of one or more sinusoids to channelize the signal, following which each channel is filtered (to provide decimation and channel selectivity) and subsequently demodulated (or otherwise interpreted). The Digital Pulse Compression Filter is an example of a Matched Filter where the filter is designed to identify the characteristics of the transmitted pulse as they are returned to the receiver in the form of reflected pulses. Received pulses with same characteristics as of the transmitted pulse are identified by the Matched Filter whereas other received signals pass relatively unnoticed by the receiver. It performs a complex convolution of the input against a pre-stored waveform.
The transmitted pulse with bandwidth B is compressed in the DPC stage to a time resolution of 1/B sec. Note that this requires four real convolutions, two of which share a common set of coefficients. Thus, we generate four filter blocks, two FIR block process In-phase (I) data and the remaining two FIR block process Quadrature-phase (Q) data. The resulting data stream must be added or subtracted, depending on whether the real or

imaginary part is being computed as shown in FIG. 2.DPC Coefficients are generated using hamming window which results in suppression of range side lobe and widening of the main lode.
[006] In other words, conventional signal processing systems associated with
RADARs face a high-resource-components limitation. It is desirable that the aforementioned system affords better resource architecture while providing the same or better performance. Again, to overcome the limitations of resource availability, the single-filter approach to perform digital down conversion and digital pulse compression is proposed here which gives the same or better performance over the conventional method.
[007] Attempts have been made in the prior art to realize solutions for above-
mentioned limitation(s) but none have been able to provide an effective solution. For example, US patent documents such as US4359735, US5229775, US4673941 provide disclosure as to digital pulse compression aspects in general, but these patent documents provide substantial room for improvement in various pulse compression aspects. Therefore, there is a need in the art to provide a reliable and efficient RADAR application having both down conversion block and pulse compression block in a single filter thereby affording enhanced performance.
[008] All publications herein are incorporated by reference to the same extent as if
each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
[009] In some embodiments, the numbers expressing quantities or dimensions of
items, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that may vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors

necessarily resulting from the standard deviation found in their respective testing measurements.
[0010] As used in the description herein and throughout the claims that follow, the
meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0011] Groupings of alternative elements or embodiments of the invention disclosed
herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.
OBJECTS OF THE PRESENT DISCLOSURE
[0012] Some of the objects of the present disclosure, which at least one embodiment
herein satisfies are as listed herein below.
[0013] It is an object of the present disclosure to provide RADAR applications having
both down conversion block and pulse compression block in a single filter thereby affording
enhanced performance.
[0014] It is another object of the present disclosure to provide a simple and effective
RADAR application having both down conversion block and pulse compression block in a
single filter thereby affording enhanced performance.
[0015] It is another object of the present disclosure to provide a reliable and efficient
RADAR application having both down conversion block and pulse compression block in a
single filter thereby affording enhanced performance.
[0016] It is another object of the present disclosure to provide a robust RADAR
applications having both down conversion block and pulse compression block in a single
filter thereby affording enhanced performance.
SUMMARY
[0017] The present disclosure generally relates to signal processing systems in
RADARS. More specifically, the present disclosure relates to signal processing systems in RADARS that can afford both down conversion and pulse compression in a single filter.

[0018] This summary is provided to introduce simplified concepts of a system for
time bound availability check of an entity, which are further described below in the detailed
description. This summary is not intended to identify key or essential features of the claimed
subject matter, nor is it intended for use in determining/limiting the scope of the claimed
subject matter.
[0019] An aspect of the present disclosure pertains to an enhanced signal processing
system for use in electronic applications. The system comprises an analog to digital converter
(ADC), a field programmable gate array (FPGA), a conversion means, an oscillator
mechanism, a finite impulse response (FIR) filter, a data-rate reduction means, and a
combining means. The analog to digital converter (ADC) is capable of digitizing intermediate
frequency signal at a fixed sampling rate. The FPGA configured to perform digital down
conversion and pulse compression on signals received from the ADC. The conversion means
is configured to convert the intermediate frequency signal to a baseband frequency signal.
The oscillator mechanism is capable of generating an intended frequency based on the
intermediate frequency associated with the intermediate frequency signal. The FIR filter is
configured to correlate the baseband signal received and a transmitted baseband signal. The
data-rate reduction means is configured to reduce data-rate associated with the baseband
signal. The combining means is configured to eliminate unmatched signals.
[0020] In an aspect, the eliminating function associated with the combining means
occurs after the correlation function associated with the FIR filter.
[0021] In an aspect, the data-rate reduction function associated with the data-rate
reduction means occurs after the correlation function associated with the FIR filter.
[0022] In an aspect, the correlation function associated with the FIR filter includes
four parallel stages.
[0023] In an aspect, the conversion means is a digital mixer or a multiplier.
[0024] In an aspect, the oscillator means is controlled numerically.
[0025] In an aspect, the FIR filter operates at a rate equal to a sampling rate of the
ADC.
[0026] In an aspect, the FIR filter is capable of over clocking with regards to
resources associated with the enhanced signal processing system.
[0027] In an aspect, power difference among peaks and associated sub-peaks is up to
1dBwith regards to multiple target resolution.
[0028] Various objects, features, aspects and advantages of the inventive subject
matter will become more apparent from the following detailed description of preferred

embodiments, along with the accompanying drawing figures in which like numerals represent like components.
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The diagrams are for illustration only, which thus is not a limitation of the
present disclosure, and wherein:
[0030] FIG. 1 is a schematic representation of a conventional digital receiver, with
respect to an embodiment of the present disclosure.
[0031] FIG. 2 is a block diagram of pulse compressor, in accordance with an
embodiment of the present disclosure.
[0032] FIG. 3 shows normalized frequency response of input chirp signal, in
accordance with an embodiment of the present disclosure.
[0033] FIG. 4 shows frequency response comparison of DDC FIR filter and single
FIR filter, in accordance with an embodiment of the present disclosure.
[0034] FIG. 5 shows range resolution calculation for a pulse compressed output, in
accordance with an embodiment of the present disclosure.
[0035] FIG. 6 shows comparison simulation result of suggested pulse compression
method with conventional pulse compression output, in accordance with an embodiment of
the present disclosure.
[0036] FIG. 7 shows Doppler tolerance comparison, in accordance with an
embodiment of the present disclosure.
[0037] FIG. 8 shows comparison with respect to multiple target resolution, in
accordance with an embodiment of the present disclosure.
[0038] FIG. 9 is an enlarged version of FIG. 8 with respect to multiple target
resolution, in accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0039] The following is a detailed description of embodiments of the disclosure
depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0040] In the following description, numerous specific details are set forth in order to
provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0041] Embodiments of the present invention include various steps, which will be
described below. The steps may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, steps may be performed by a combination of hardware, software, and firmware and/or by human operators.
[0042] Various methods described herein may be practiced by combining one or more
machine-readable storage media containing the code according to the present invention with
appropriate standard computer hardware to execute the code contained therein. An apparatus
for practicing various embodiments of the present invention may involve one or more
computers (or one or more processors within a single computer) and storage systems
containing or having network access to computer program(s) coded in accordance with
various methods described herein, and the method steps of the invention could be
accomplished by modules, routines, subroutines, or subparts of a computer program product.
[0043] If the specification states a component or feature “may”, “can”, “could”, or
“might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0044] As used in the description herein and throughout the claims that follow, the
meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0045] Exemplary embodiments will now be described more fully hereinafter with
reference to the accompanying drawings, in which exemplary embodiments are shown. These exemplary embodiments are provided only for illustrative purposes and so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. The invention disclosed may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Various modifications will be readily apparent to persons skilled in the art. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Moreover, all statements herein reciting

embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure). Also, the terminology and phraseology used is for the purpose of describing exemplary embodiments and should not be considered limiting. Thus, the present invention is to be accorded the widest scope encompassing numerous alternatives, modifications and equivalents consistent with the principles and features disclosed. For purpose of clarity, details relating to technical material that is known in the technical fields related to the invention have not been described in detail so as not to unnecessarily obscure the present invention.
[0046] Thus, for example, it will be appreciated by those of ordinary skill in the art
that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named element.
[0047] Embodiments of the present invention may be provided as a computer program
product, which may include a machine-readable storage medium tangibly embodying thereon instructions, which may be used to program a computer (or other electronic devices) to perform a process. The term “machine-readable storage medium” or “computer-readable storage medium” includes, but is not limited to, fixed (hard) drives, magnetic tape, floppy diskettes, optical disks, compact disc read-only memories (CD-ROMs), and magneto-optical disks, semiconductor memories, such as ROMs, PROMs, random access memories (RAMs), programmable read-only memories (PROMs), erasable PROMs (EPROMs), electrically erasable PROMs (EEPROMs), flash memory, magnetic or optical cards, or other type of media/machine-readable medium suitable for storing electronic instructions (e.g., computer programming code, such as software or firmware).A machine-readable medium may include

a non-transitory medium in which data may be stored and that does not include carrier waves and/or transitory electronic signals propagating wirelessly or over wired connections. Examples of a non-transitory medium may include, but are not limited to, a magnetic disk or tape, optical storage media such as compact disk (CD) or digital versatile disk (DVD), flash memory, memory or memory devices. A computer-program product may include code and/or machine-executable instructions that may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.
[0048] Furthermore, embodiments may be implemented by hardware, software,
firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks (e.g., a computer-program product) may be stored in a machine-readable medium. A processor(s) may perform the necessary tasks.
[0049] Systems depicted in some of the figures may be provided in various
configurations. In some embodiments, the systems may be configured as a distributed system where one or more components of the system are distributed across one or more networks in a cloud computing system.
[0050] Each of the appended claims defines a separate invention, which for
infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases, it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[0051] All methods described herein may be performed in any suitable order unless
otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification

should be construed as indicating any non-claimed element essential to the practice of the
invention.
[0052] Various terms as used herein are shown below. To the extent a term used in a
claim is not defined below, it should be given the broadest definition persons in the pertinent
art have given that term as reflected in printed publications and issued patents at the time of
filing.
[0053] The present disclosure generally relates to signal processing systems in
RADARS. More specifically, the present disclosure relates to signal processing systems in
RADARS that can afford both down conversion and pulse compression in a single filter.
[0054] An aspect of the present disclosure pertains to an enhanced signal processing
system for use in electronic applications. The system comprises an analog to digital converter
(ADC), a field programmable gate array (FPGA), a conversion means, an oscillator
mechanism, a finite impulse response (FIR) filter, a data-rate reduction means, and a
combining means. The analog to digital converter (ADC) is capable of digitizing intermediate
frequency signal at a fixed sampling rate. The FPGA configured to perform digital down
conversion and pulse compression on signals received from the ADC. The conversion means
is configured to convert the intermediate frequency signal to a baseband frequency signal.
The oscillator mechanism is capable of generating an intended frequency based on the
intermediate frequency associated with the intermediate frequency signal. The FIR filter is
configured to correlate the baseband signal received and a transmitted baseband signal. The
data-rate reduction means is configured to reduce data-rate associated with the baseband
signal. The combining means is configured to eliminate unmatched signals.
[0055] In an aspect, the eliminating function associated with the combining means
occurs after the correlation function associated with the FIR filter.
[0056] In an aspect, the data-rate reduction function associated with the data-rate
reduction means occurs after the correlation function associated with the FIR filter.
[0057] In an aspect, the correlation function associated with the FIR filter includes
four parallel stages.
[0058] In an aspect, the conversion means is a digital mixer or a multiplier.
[0059] In an aspect, the oscillator means is controlled numerically.
[0060] In an aspect, the FIR filter operates at a rate equal to a sampling rate of the
ADC.
[0061] In an aspect, the FIR filter is capable of over clocking with regards to
resources associated with the enhanced signal processing system.

[0062] In an aspect, power difference among peaks and associated sub-peaks is up to
1dB with regards to multiple target resolution.
[0063] In typical RADAR applications, Digital Down Conversion (DDC) acts as a
front end for signal processing applications and followed by Digital Pulse Compression (DPC). Both DDC and DPC are implemented in separate filters, sometimes even in separate modules. A generic architecture for DDC is shown in FIG. 1.
[0064] An ADC samples the detected analog signal and feeds into the DDC processing
chain. In DDC, a mixer is used in combination with a vector of one or more sinusoids to channelize the signal, then each channel is filtered (to provide decimation and channel selectivity) and finally demodulated (or otherwise interpreted).The Digital Pulse Compression Filter is an example of a Matched Filter where the filter is designed to identify the characteristics of the transmitted pulse as they are returned to the receiver in the form of reflected pulses. Received pulses with same characteristics as of the transmitted pulse are identified by the Matched Filter whereas other received signals pass relatively unnoticed by the receiver. It performs a complex convolution of the input against a pre-stored waveform. The transmitted pulse with bandwidth B is compressed in the DPC stage toa time resolution of 1/B sec. Note that this requires four real convolutions, two of which share a common set of coefficients. Thus, we generate four filter blocks, two FIR block process In-phase(I) data and the remaining two FIR block process Quadrature-phase (Q) data. The resulting data stream must be added or subtracted, depending on whether the real or imaginary part is being computed as shown in FIG. 2. DPC Coefficients are generated using hamming window which results in suppression of range side lobe and widening of the main lode.
[0065] In particular, to overcome the limitations of resource availability, the single-
filter approach to perform digital down conversion (DDC)and digital pulse compression (DPC) is proposed here which gives the same or better performance over the conventional method. As discussed above, DDC and DPC are integrated into a single filter. The FIR filter of the module is a complex filter which acts a low pass filter and a matched filter, which performs the compression using the co-relation technique. The Filter coefficients consist of LFM baseband waveform at a rate equal to conventional DDC sample rate. The ADC sampled data is fed to Mixer. The mixing is done to shift the signal spectrum from the selected carrier frequencies to baseband. This signal enters into the FIR filter where its convolution with pre-stored LFM waveform is performed. These coefficients are generated using the desired window to minimize the side lobes effects and enhance the peak to side-

lobe ratio. The decimation process is followed to bring the output sample rate equal to the bandwidth of LFM signal.
[0066] Comparison of two approaches: The comparison experiment was performed
considering the typical values of search radar applications which is as follows: IF=70 MHz; FS=160MHz; BW= 5MHz; PW=100µs; SNR=70 dB; Harmonics= 2nd (-40 dB) and 3rd (-60 dB).
[0067] FIG. 3 shows the spectrum of mixer output in DDC stage for 5MHz bandwidth
chirp. Chirp waveform is translated to baseband. The 2nd and 3rd harmonics are also visible
in the 1st Nyquist zone which must be filtered out by an FIR filter implemented in the DDC.
FIG. 4 represents the DDC FIR filter spectrum compared to the LFM spectrum. DDC FIR has
corner frequencies of 2.5 MHz and 3 MHz, stop band attenuation of 60 dB and pass band
ripple of 0.1 dB with an order of 817. The window used in the LFM spectrum is a hamming
window. It was observed that attenuation at stop corner frequency (3MHz) is 12 dB less in
case of LFM spectrum, but from 6MHz onwards, attenuation in the stop band is much more
in LFM spectrum as compared to DDC FIR. The attenuation margin at 80MHz is of 20 dB
which leads to better performance with respect to spurious components and noise.
[0068] The fusion of two modules in the new approach provided an efficient solution
which can be seen by comparing the two approaches based on four significant characteristics: (i) Resources ii) Range resolution iii) Doppler tolerance iv) Multiple-Target Resolution. Accordingly:
[0069] i. Resources: The integration of two modules has led to the saving of
resources. The conventional approach uses DSP resources as well as BRAMs for the filtering
process. The number of resources used for filtering increases with the increase in the order of
the filter to be used. As known, the order of filter depends on factors like the pass band
ripple, stop band attenuation and the transition band of the filter. An experiment was
performed considering the sampling frequency of 160MHz and Chirp bandwidth of 20MHz.
Order of the filter designed with pass-band attenuation of 0.1dB, transition band of 25% of
the pass-band is 5MHz, stop-band attenuation of 80dB requires 200 tap filter. Considering the
sampling frequency of 160MHz and other filter specifications same except the pass-band
width (bandwidth) as 0.5MHz. In this case, the transition band which is 0.25% of pass-band
and will extend from 0.5MHz to 0.625MHz. Order of the resultant filter is 3000.
[0070] The above experiment indicates the resource usage in FPGAs/Processors with
reference to the type of the filter. Hence applications with multiple bandwidths having both narrowband and wideband requirements consume ample amount of resources which would

not only increase the price of the processor/FPGA to be chosen but also increases the complexity in routing within the FPGA.
[0071] The resource comparison of the two methods is as follows: For resource type
FIR Order, the individual DDC FIR and the individual DPC FIR was found to be 817 and 200 respectively while Single FIR afforded 3200.For resource type ALMs, the individual DDC FIR and the individual DPC FIR was found to be 852 and 674 respectively while Single FIR afforded 1441. For resource type Registers, the individual DDC FIR and the individual DPC FIR was found to be 1118 and 1009respectively while Single FIR afforded 1952. For resource type Memory Bits, the individual DDC FIR and the individual DPC FIR was found to be 12288 and 12288respectively while Single FIR afforded 13312. For resource type DSP Blocks, the individual DDC FIR and the individual DPC FIR was found to be 14 and 25respectively while Single FIR afforded 25. The parameters for this radar considered are as follows: LFM BW=5MHz; FS=160MHz; PW=20us; IF=70MHz. The FIR is generated for startix 5 FPGA using Quartus 14. The DDC FIR is an equi-ripple filter (order 817, FS=160 MHz, corner frequencies=2.5 and 3.0 MHz, ripple=0.1 attenuation=60 dB).
[0072] Thus, the proposed approach can be carried out with less resources compared
to the conventional approach. Further the resources utilized can be reduced by using over-
clocking technique in which FIR filter runs at rate integral multiple of ADC sampling rate.
The reduction factor in the resource utilized is equal to the integral multiple used in over-
clocking technique. Thus, eliminating such intensive filters from the application would
reduce the complexity for both the hardware designer as well as the software developer.
[0073] ii. Range resolution: Range resolution is related to transmit pulse length, but
is constrained by bottlenecks through the entire system, including receiver’s characteristics such as bandwidth and sampling interval. Both band-width and sampling interval shall be considered to calculate range resolution rather than simply defining as the inverse of transmit pulse. FIG. 5 shows the range resolution calculations, where1 indicates Received pulse waveform after pulse compression,2 indicates Sampling pulse, and3 indicates Sampling interval.



[0079] Range resolution of pulse compression radar is calculated using the above
equations for the proposed method and compared with the conventional method as shown in FIG. 6. An improvement of up to 10 percent in the range resolution was achieved considering different real-time scenarios through above calculations mentioned.
[0080] iii. Doppler tolerance: LFM is known for its good Doppler tolerance. It’s the
most common used waveform in the pulsed radars. In pulsed radars, we perform matched filtering in the receiver where the cross-correlation of the received waveform and a pre-stored waveform is performed. Due to Doppler shift in the received echo, matched filter’s performance will deteriorate. Doppler tolerance defines the maximum Doppler shift for which performance of the matched filter in terms of PSLR will not de-grade beyond the specified limit. To compare the two methods, Doppler of 100 kHz was given in the input.FIG. 7 shows the output of pulse compression in both cases. It was observed that the performance in both the approaches (conventional and proposed) has shown similar results.
[0081] iv. Multiple Target resolution: The target resolution of a radar is its ability to
distinguish between targets that are very close in either range or cross-range. For particular radars like Weapon-control radar, target resolution requires great precision to an extent where the targets that are only yards apart should be easily distinguished. Search radar is usually less precise and only distinguishes between targets that are hundreds of yards or even miles apart. In this paper, only range resolution comparison is discussed. Both simulations were performed for multiple targets consideringthe following parameters. IF=70 MHz; FS=160MHz; BW=1MHz; PW=100µs; SNR=70 dB; Harmonics= 2nd (-40 dB) and 3rd (-60 dB). FIG. 8 shows the result of the two simulations which indicates that target resolution is slightly better in proposed method. This is due to the difference between the power of the adjacent range cells differ by a margin of 0.5 dB to 2 dB as shown in FIG. 9, which is a zoomed view of FIG. 8.
[0082] An embodiment provides asingle filter solution for digital down conversion and
pulse compression wherein the FIR filter module with 4 parallel stages that combines the functionality of Digital Down Conversion and Digital Pulse Compression into a single filter module.
[0083] Another embodiment provides an apparatus that comprises of: (i) an Analog to
Digital converter which digitizes the incoming intermediate frequency signal at a fixed

sampling rate; (ii) an FPGA for the performing the Digital down conversion and pulse
compression application on the signals received from ADC; (iii) a digital mixer or the
multiplier to convert the signal frequency from intermediate to baseband; (iv) a numerically
controlled oscillator for generating the intended frequency which is similar to that of the
Intermediate frequency received; (v) an FIR filter with 4 parallel stages to perform the
correlation operation of the baseband signal received and the transmitted base band signal; (vi)
a decimator stage after the correlation operation to reduce the data-rate for further application
processing; (vii) a combiner to eliminate the unmatched signal from after the correlation stage.
[0084] An embodiment provides asingle filter solution for digital down conversion and
pulse compression where the range resolution improvement obtained is up to 10 percent as compared to the conventional method.
[0085] An embodiment provides a single filter solution for digital down conversion
and pulse compression where the said FIR filter module with 4 parallel stages operates at a rate equal to the sampling rate of ADC.
[0086] An embodiment provides a single filter solution for digital down conversion
and pulse compression where the said FIR filter module with 4 parallel stages has the provision of over clocking which leads to the reduction of resources utilized.
[0087] An embodiment provides a single filter solution for digital down conversion
and pulse compression where the said single filter solution for digital down conversion and pulse compression improves the multiple target resolution, where power difference among peaks and its sub-peaks is up to1dB.
[0088] Thus, it is an object of this invention to provide an improvement in resource
optimization over the conventional pulse compression method for the search radar application. However, this may be extended to other fields where equivalent pulse compression technique is used. A further object of this invention is to minimize the complexity of digital receiver using pulse compression technique.
[0089] The present disclosure describes a novel solution to optimize the conventional
Digital Down Conversion and Digital Pulse Compression with respect to hardware complexity, speed, power dissipation and resource utilization in Radar applications. Digital Down Conversion being the front-end processing stage to extract the message signal from the reflected echo, includes the usage of sharp cut-off filtering. Most commonly followed stage after Digital Down Conversion is Digital Pulse Compression which emphasizes in correlating the transmitted message signal with the received echo. Digital Pulse Compression implementation requires several multiplier and adder operations, which is directly

proportional to bandwidth and pulse width of the transmitted signal. The optimized solution disclosed here concocts the Digital Pulse Compression and Digital Down Conversion algorithms into a single filter.
[0090] The above mentioned method is envisioned to be performed using appropriate
physical devices that may be appreciated by a person skilled in the art. As such all physical devices comprising respective various physical materials serve their respective functions and all such materials and their respective manufacturing methods are intended to be covered by this disclosure.
[0091] Thus, it will be appreciated by those of ordinary skill in the art that the
diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures can be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function can be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
[0092] While embodiments of the present invention have been illustrated and
described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.
[0093] In the foregoing description, numerous details are set forth. It will be apparent,
however, to one of ordinary skill in the art having the benefit of this disclosure, that the present invention can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention.
[0094] As used herein, and unless the context dictates otherwise, the term "coupled
to" is intended to include both direct coupling (in which two elements that are coupled to each other contact each other)and indirect coupling (in which at least one additional element is located between the two elements). Therefore, the terms "coupled to" and "coupled with"

are used synonymously. Within the context of this document terms "coupled to" and "coupled with" are also used euphemistically to mean “communicatively coupled with” over a network, where two or more devices are able to exchange data with each other over the network, possibly via one or more intermediary device.
[0095] It should be apparent to those skilled in the art that many more modifications
besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps can be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C …. and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[0096] While the foregoing describes various embodiments of the invention, other and
further embodiments of the invention can be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.
ADVANTAGES OF THE PRESENT DISCLOSURE
[0097] The present disclosure provides RADAR applications having both down
conversion block and pulse compression block in a single filter thereby affording enhanced
performance.
[0098] The present disclosure provides a simple and effective RADAR applications
having both down conversion block and pulse compression block in a single filter thereby
affording enhanced performance.
[0099] The present disclosure provides a reliable and efficient RADAR applications
having both down conversion block and pulse compression block in a single filter thereby
affording enhanced performance.

[00100] The present disclosure provides a robust RADAR applications having both
down conversion block and pulse compression block in a single filter thereby affording enhanced performance.

We claim:
1. A enhanced signal processing system for use in electronic applications, the system
comprising:
an analog to digital converter (ADC)capable of digitizing intermediate frequency signal at a fixed sampling rate;
an FPGA configured to perform digital down conversion and pulse compression on signals received from the ADC;
a conversion means is configured to convert the intermediate frequency signal to a baseband frequency signal;
an oscillator mechanism capable of generating an intended frequency based on the intermediate frequency associated with the intermediate frequency signal;
an finite impulse response (FIR) filter configured to correlate the baseband signal received and a transmitted baseband signal;
a data-rate reduction means configured to reduce data-rate associated with the baseband signal; and
a combining means configured to eliminate unmatched signals; and wherein the eliminating function associated with the combining means occurs after the correlation function associated with the FIR filter;
wherein the data-rate reduction function associated with the data-rate reduction means occurs after the correlation function associated with the FIR filter; and
wherein the correlation function associated with the FIR filter include four parallel stages.
2. The enhanced signal processing system as claimed in claim 1, wherein the conversion means is a digital mixer or a multiplier.
3. The enhanced signal processing system as claimed in claim 2, wherein the oscillator means is controlled numerically.
4. The enhanced signal processing system as claimed in claim 3, wherein the FIR filter operates at a rate equal to a sampling rate of the ADC.
5. The enhanced signal processing system as claimed in claim 4, wherein the FIR filter is capable of over clocking with regards to resources associated with the enhanced signal processing system.

6. The enhanced signal processing system as claimed in claim 5, wherein, with regards
to multiple target resolution, power difference among peaks and associated sub-peaks is up to 1dB.