1
FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
SLOW-RELEASE RELAY CIRCUIT AND TRAIN CONTROL DEVICE;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANISED
AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3,
MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 100-8310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.
2
DESCRIPTION
SLOW-RELEASE RELAY CIRCUIT AND TRAIN CONTROL DEVICE
5 Field
[0001] The present invention relates to a slow-release
relay circuit for use in trains, railway facilities, and
the like, and to a train control device.
10 Background
[0002] Slow-release relay circuits have been used for
devices installed on trains, and facilities such as railway
signals and railway crossings. For the slow-release relay
circuit, a relay operates when a direct-current voltage is
15 applied, and continues operating for a certain period of
time even after the application of the direct-current
voltage stops. The relay enters a return state after the
certain period of time. In order to continue operating for
a certain period of time even after the application of the
20 direct-current voltage stops, the slow-release relay
circuit includes a power storage circuit that stores a
direct-current voltage. In general, a power storage
circuit uses a large-capacity electrolytic capacitor, and a
discharge time varies due to such an influence as a
25 variation in capacity of the electrolytic capacitor, and a
decrease in capacity due to deterioration. For this reason,
a time during which to continue the operation of the relay
also varies, and thus it is difficult to adjust a time the
relay enters the return state. To address such a problem,
30 Patent Literature 1 discloses a technique for controlling a
switching circuit provided between a relay and a power
storage circuit with a charge/discharge circuit to thereby
control a time in which to bring the relay from an
3
operating state to a return state.
Citation List
Patent Literature
[0003] Patent Literature 1: Japanese 5 Patent No.5489820
Summary
Technical Problem
[0004] For the above conventional technique, the
10 switching circuit performs interruption when the relay is
in the operating state. For this reason, unfortunately, a
counter electromotive voltage can be generated from the
relay, and do damage to the switching circuit in a case
where the relay is an inductive load.
15 [0005] The present invention has been made in view of
the above, and an object thereof is to obtain a slowrelease
relay circuit capable of controlling a time in
which to bring a relay from an operating state to a return
state without generating a counter electromotive voltage in
20 the relay which is an inductive load.
Solution to Problem
[0006] To solve the above problem and achieve the object,
a slow-release relay circuit according to the present
25 invention comprises: a power storage circuit connected in
parallel to a relay including a coil; a discharge circuit
to release electrical charge of the power storage circuit;
and a timer circuit to, when detecting interruption of
supply of power to the relay, drive the discharge circuit
30 after a prescribed time.
Advantageous Effects of Invention
[0007] The present invention achieves an effect that the
4
slow-release relay circuit can control a time in which to
bring the relay from the operating state to the return
state without generating the counter electromotive voltage
in the relay which is the inductive load.
5
Brief Description of Drawings
[0008] FIG. 1 is a diagram illustrating an example
configuration of a slow-release relay circuit according to
a first embodiment.
10 FIG. 2 is a diagram illustrating voltages applied to a
diode, a relay, and a power storage circuit in the slowrelease
relay circuit according to the first embodiment.
FIG. 3 is a diagram illustrating a voltage discharged
from a capacitor of the power storage circuit in the slow15
release relay circuit according to the first embodiment.
FIG. 4 is a diagram illustrating a time until the
relay changes from an operating state to a return state in
the slow-release relay circuit according to the first
embodiment.
20 FIG. 5 is a circuit diagram illustrating a state when
a switch of a discharge circuit in the slow-release relay
circuit according to the first embodiment is closed.
FIG. 6 is a diagram illustrating a voltage discharged
from the capacitor of the power storage circuit when the
25 switch of the discharge circuit in the slow-release relay
circuit according to the first embodiment is closed.
FIG. 7 is a diagram illustrating a time until the
relay changes from the operating state to the return state
when the switch of the discharge circuit in the slow30
release relay circuit according to the first embodiment is
closed.
FIG. 8 is a diagram illustrating an example
configuration of the slow-release relay circuit according
5
to a second embodiment.
FIG. 9 is a diagram illustrating voltages output from
a reference voltage circuit and a discharge circuit of a
timer circuit in the slow-release relay circuit according
to the 5 second embodiment.
FIG. 10 is a diagram illustrating an example
configuration of the slow-release relay circuit according
to a third embodiment.
FIG. 11 is a flowchart illustrating an operation of
10 the timer circuit of the slow-release relay circuit
according to the third embodiment.
FIG. 12 is a diagram illustrating an example of a case
where a processing circuitry included in the timer circuit
of the slow-release relay circuit according to the third
15 embodiment is configured with a processor and a memory.
FIG. 13 is a diagram illustrating an example of a case
where the processing circuitry included in the timer
circuit of the slow-release relay circuit according to the
third embodiment is configured with dedicated hardware.
20 FIG. 14 is a diagram illustrating an example
configuration of a slow-release relay circuit according to
a fourth embodiment.
FIG. 15 is a diagram illustrating an example
configuration of a train control device according to a
25 fifth embodiment.
Description of Embodiments
[0009] Hereinafter, a slow-release relay circuit and a
train control device according to each embodiment of the
30 present invention will be described in detail with
reference to the drawings. The present invention is not
limited to the embodiments.
[0010] First Embodiment.
6
FIG. 1 is a diagram illustrating an example
configuration of a slow-release relay circuit 10 according
to a first embodiment of the present invention. A power
supply line P24A and a power supply line N24 are connected
to the slow-release relay circuit 10. A 5 power supply line
P24 and the power supply line N24 are connected to a
direct-current power supply 50. A switch SW1 connects and
disconnects the power supply line P24A and the power supply
line P24. The slow-release relay circuit 10 is connected
10 to the direct-current power supply 50 via the power supply
line P24, the switch SW1, the power supply line P24A, and
the power supply line N24. When the switch SW1 is operated
to be closed, the power supply line P24A is energized and
supply of power from the direct-current power supply 50 to
15 the slow-release relay circuit 10, that is, application of
a direct-current voltage starts. When the switch SW1 is
operated to open, the power supply line P24A is deenergized,
and the supply of power from the direct-current
power supply 50 to the slow-release relay circuit 10 stops.
20 The direct-current power supply 50 may be in the form of a
battery as illustrated in FIG. 1, or may be an alternatingcurrent
power supply and a converter that converts an
alternating-current voltage output from the alternatingcurrent
power supply into a direct-current voltage.
25 [0011] A configuration of the slow-release relay circuit
10 will be described. As illustrated in FIG. 1, the slowrelease
relay circuit 10 includes a diode D1, a relay RY1,
a power storage circuit 20, a discharge circuit 30, and a
timer circuit 40.
30 [0012] The relay RY1 includes a coil (not illustrated)
therein. That is, the relay RY1 is a relay which is an
inductive load. When a direct-current voltage is applied
to the relay RY1 of the slow-release relay circuit 10 with
7
normally open contact closed, the relay RY1 is in an
operating state. In addition, when no direct-current
voltage is applied to the relay RY1 with the normally open
contact open, the relay RY1 is in a return state.
[0013] The diode D1 is a backflow prevention 5 diode that
prevents electrical charge from leaking from the relay RY1
or the power storage circuit 20 to the power supply line
P24A.
[0014] In the slow-release relay circuit 10, the power
10 storage circuit 20 is connected in parallel to the relay
RY1, i.e., the coil of the relay RY1. A configuration of
the power storage circuit 20 will be described. The power
storage circuit 20 includes a resistor R1 and a capacitor
C1. The resistor R1 limits an inrush current flowing to
15 the capacitor C1. A resistance value of the resistor R1 is
denoted by R1, and resistors described later will be
defined in the same manner. When a voltage is applied to
the power supply line P24A, the capacitor C1 is charged
with the direct-current voltage supplied from the direct20
current power supply 50 within a range of a capacitance of
the capacitor C1. After the power supply line P24A is deenergized,
the capacitor C1 supplies the direct-current
voltage to the relay RY1 and maintains the operating state
of the relay RY1. When the capacitor C1 enters a discharge
25 state, the relay RY1 enters the return state. The
capacitance of the capacitor C1 is denoted by C1, and
capacitors described later will be defined in the same
manner.
[0015] An operation of the power storage circuit 20 will
30 be described with reference to FIGS. 2 to 4. FIG. 2 is a
diagram illustrating voltages applied to the diode D1, the
relay RY1, and the power storage circuit 20 in the slowrelease
relay circuit 10 according to the first embodiment.
8
FIG. 3 is a diagram illustrating a voltage discharged from
the capacitor C1 of the power storage circuit 20 in the
slow-release relay circuit 10 according to the first
embodiment. FIG. 4 is a diagram illustrating a time until
the relay RY1 changes from the operating 5 state to the
return state in the slow-release relay circuit 10 according
to the first embodiment. FIGS. 2 and 3 illustrate only
portions necessary for the description, and omit portions
unnecessary for the description.
10 [0016] When the switch SW1 is closed in FIG. 2, a
voltage from the direct-current power supply 50 is applied
to the power supply line P24A. Assuming that the voltage
applied to the power supply line P24A is denoted by EP24A
and a forward voltage of the diode D1 is denoted by ED1, a
15 voltage of E=EP24A-ED1 is applied to the relay RY1. In this
case, a voltage is applied to the capacitor C1 of the power
storage circuit 20 via the resistor R1. When power is
stored in the capacitor C1, no current flows through the
resistor R1. As a result, the voltage applied to the
20 capacitor C1 becomes the voltage E.
[0017] An open voltage of the relay RY1 is denoted by
EOPEN. The resistance value of the relay RY1 is RRY1. A
current IOPEN flowing through the relay RY1 when the relay
RY1 changes from the operating state to the return state
25 can be expressed by formula (1) below.
[0018] IOPEN=EOPEN/RRY1 ... (1)
[0019] The operation of the relay RY1 when the switch
SW1 is opened after the capacitor C1 of the power storage
circuit 20 is charged with the switch SW1 closed in FIG. 2
30 will be described. Assume that the voltage applied to the
capacitor C1 when the switch SW1 is opened is denoted by
E=EP24A-ED1 and a combined resistance of the resistor R1 and
the relay RY1 is denoted by R=R1+ RRY1. A current i(t)
9
flowing through the relay RY1 at a time t can be expressed
by formula (2) below.
[0020] i(t)=(E/R)exp(-t/C1•R) ... (2)
[0021] FIG. 4 is a graph of the current i(t) expressed
by formula (2). In FIG. 4, the horizontal 5 axis represents
time, and the vertical axis represents current. As
illustrated in FIG. 4, the current i(t) decreases with the
lapse of time, and when the current i(t)=IOPEN holds true,
the relay RY1 enters the return state. In a case where a
10 time until the relay RY1 enters the return state is denoted
by τ1, formula (2) can be expressed by formula (3) below.
[0022] IOPEN=(E/R)exp(-τ1/C1•R) ... (3)
[0023] A time τ1 until the relay RY1 enters the return
state after the switch SW1 is opened is determined by
15 formula (3).
[0024] Next, a configuration and an operation of the
discharge circuit 30 will be described. The discharge
circuit 30 discharges the power storage circuit 20. More
specifically, the discharge circuit 30 releases electrical
20 charge accumulated in the capacitor C1 of the power storage
circuit 20. The discharge circuit 30 includes a resistor
R2 and a switch SW2. The resistor R2 has one end connected
to one end of the capacitor C1 of the power storage circuit
20, and an opposite end connected to an opposite electrode
25 of the capacitor C1 of the power storage circuit 20 via the
switch SW2. The electrical charge accumulated in the
capacitor C1 of the power storage circuit 20 is released
via the resistor R2 when the switch SW2 is closed.
[0025] When the switch SW2 is closed, the resistor R2 is
30 connected in parallel to a series circuit made up of the
resistor R1 and the relay RY1. FIGS. 5 to 7 each
illustrate a state when the switch SW2 is closed. FIG. 5
is a circuit diagram illustrating a state when the switch
10
SW2 of the discharge circuit 30 in the slow-release relay
circuit 10 according to the first embodiment is closed.
FIG. 6 is a diagram illustrating a voltage discharged from
the capacitor C1 of the power storage circuit 20 when the
switch SW2 of the discharge circuit 30 in 5 the slow-release
relay circuit 10 according to the first embodiment is
closed. FIG. 7 is a diagram illustrating a time until the
relay RY1 changes from the operating state to the return
state when the switch SW2 of the discharge circuit 30 in
10 the slow-release relay circuit 10 according to the first
embodiment is closed.
[0026] Assume that a combined resistance of the resistor
R2 and the series circuit of the resistor R1 and the relay
RY1 is denoted by RSW2ON. The combined resistance RSW2ON can
15 be expressed by formula (4) below. Note that “//” is a
symbol indicating a parallel circuit.
[0027] RSW2ON=(R1+RRY1)//R2
=1/(1/R2+1/(R1+RRY1)) ... (4)
[0028] A voltage of the capacitor C1 when the switch SW2
20 is closed after the switch SW1 is opened in FIG. 5 is
denoted by ESW2ON. In addition, a time elapsed since the
switch SW2 is closed is denoted by t1. With the time t1
elapsed, a current iSW2ON(t1) flowing through the combined
resistance RSW2ON can be expressed by formula (5) below.
25 [0029] iSW2ON(t1)=(ESW2ON/RSW2ON)exp(-t1/C1•RSW2ON)... (5)
[0030] With the current iSW2ON(t1), a voltage eSW2ON(t1)
across the combined resistance RSW2ON can be expressed by
formula (6) below.
[0031] eSW2ON(t1)=RSW2ON•iSW2ON(t1)
30 =ESW2ON•exp(-t1/C1•RSW2ON) ... (6)
[0032] Since a voltage eRY1(t1) applied to the relay RY1
is a divided voltage based on the resistance R1 of the
resistor R1 and the resistance RRY1 of the relay RY1, the
11
voltage eRY1(t1) can be expressed by formula (7) below.
[0033] eRY1(t1)=(RRY1/(R1+RRY1))•eSW2ON(t1)
=(RRY1/(R1+RRY1))•ESW2ON•exp(-t1/C1•RSW2ON) ...
(7)
[0034] With the voltage eRY1(t1), a drive 5 current iRY1(t1)
through the relay RY1 can be expressed by formula (8) below.
[0035] iRY1(t1)=eRY1(t1)/RRY1
=(1/(R1+RRY1))•ESW2ON•exp(-t1/C1•RSW2ON) ... (8)
[0036] FIG. 7 is a graph of the drive current iRY1(t1)
10 expressed by formula (8). In FIG. 7, the horizontal axis
represents time, and the vertical axis represents current.
As illustrated in FIG. 7, when the drive current iRY1(t1)
through the relay RY1 becomes IOPEN, the relay RY1 enters
the return state. When the relay RY1 enters the return
15 state after the lapse of a time τSw2ON since the closing of
the switch SW2, formula (9) below holds true.
[0037] IOPEN=(1/(R1+RRY1))•ESW2ON•exp(-τSW2ON/C1•RSW2ON) ... (9)
[0038] Note that RSW2ON=(R1+RRY1)//R2τ3>τ4” holds true,
thereby enabling the slow-release relay circuit 10 of the
second embodiment to bring the relay RY1 to the return
state in the time τ4 after the switch SW1 is opened.
18
[0055] FIG. 9 is a diagram illustrating voltages output
from the reference voltage circuit 42 and the discharge
circuit 43 of the timer circuit 40 in the slow-release
relay circuit 10 according to the second embodiment. In
FIG. 9, the horizontal axis represents 5 time and the
vertical axis represents voltage. In FIG. 9, VZD11, which
is the voltage output from the reference voltage circuit 42,
is constant, but in practice, the voltage decreases after
the lapse of the time τ3.
10 [0056] The discharge circuit 43 can reduce the
capacitance of the capacitor C13 by increasing the
resistance of the resistor R16. For this reason, the
capacitor C13 can be easily designed with a capacitor such
as a film capacitor or a ceramic capacitor having its value
15 that initially less varies and less changes depending upon
temperature. Similarly, the resistor R16 can be achieved
selecting a resistor having its value initially less
varying and less changing depending upon temperature. The
discharge circuit 43 may be referred to as a second
20 discharge circuit.
[0057] For the slow-release relay circuit 10, as
discussed above, the voltage comparator circuit 41 compares
the voltage output from the reference voltage circuit 42
with the voltage output from the discharge circuit 43.
25 When the supply of power to the relay RY1 is interrupted
and the voltage output from the discharge circuit 43
becomes equal to or lower than the voltage output from the
reference voltage circuit 42, the discharge circuit 30 is
driven. Note that a power supply that operates the voltage
30 comparator circuit 41 is a circuit corresponding to the
capacitor C11 of the reference voltage circuit 42.
Alternatively, the capacitor C11 of the reference voltage
circuit 42 may be used as the power supply that operates
19
the voltage comparator circuit 41. The capacitor C11 of
the reference voltage circuit 42 can also be shared with as
the capacitor C1 of the power storage circuit 20.
[0058] As described above, the timer circuit 40 of the
slow-release relay circuit 10 according 5 to the present
embodiment is defined by the electrical circuit including
electrical components such as a capacitor, a resistor, and
a diode. The thus defined timer circuit 40 controls a time
for driving the discharge circuit 30, using a time of
10 discharge by the capacitor and the resistor. Consequently,
the slow-release relay circuit 10 can obtain the effect
described in the first embodiment.
[0059] Third Embodiment.
A third embodiment will be described giving an example
15 in which the timer circuit 40 is defined by a microcomputer
or the like.
[0060] FIG. 10 is a diagram illustrating an example
configuration of the slow-release relay circuit 10
according to the third embodiment. A configuration of the
20 discharge circuit 30 in FIG. 10 is similar to the
configuration thereof in the second embodiment illustrated
in FIG. 8. The timer circuit 40 includes a voltage
monitoring unit 45, a clock unit 46, and a counter unit 47.
[0061] The voltage monitoring unit 45 detects
25 interruption of supply of power to the relay RY1. More
specifically, the voltage monitoring unit 45 monitors the
voltage of the power supply line P24A and determines
whether the power supply line P24A is in an energized state
or a de-energized state. The voltage monitoring unit 45
30 causes the counter unit 47 to start counting when the power
supply line P24A changes from the energized state to the
de-energized state.
[0062] The clock unit 46 generates a clock which is a
20
period in which the counter unit 47 counts.
[0063] The counter unit 47 starts counting after the
voltage monitoring unit 45 detects the interruption of the
supply of power to the relay RY1. When the slow-release
relay circuit 10 is powered on, the counter 5 unit 47 outputs
a voltage at which to turn off the transistor TR11 of the
discharge circuit 30. When having counted a prescribed
number, the counter unit 47 outputs a voltage at which to
turn on the transistor TR11 of the discharge circuit 30,
10 that is, drives the discharge circuit 30.
[0064] The time τ1 until the power storage circuit 20
brings the relay RY1 to the return state is set to be
longer than operation periods of the timer circuit 40 and
the discharge circuit 30. That is, the operation periods
15 of the timer circuit 40 and the discharge circuit 30 are
set to be shorter than the time τ1 until the power storage
circuit 20 to bring the relay RY1 to the return state. The
slow-release relay circuit 10 brings the relay RY1 to the
return state in a time determined by the clock unit 46 and
20 the counter unit 47. It is easy to determine such a
component that provides a high degree of accuracy regarding
initial value variations and temperature characteristics of
the clock unit 46 as compared with the time τ1 determined
by the capacitor C1. For example, a crystal transmitter is
25 used as the clock unit 46.
[0065] FIG. 11 is a flowchart illustrating an operation
of the timer circuit 40 of the slow-release relay circuit
10 according to the third embodiment. In the timer circuit
40, the voltage monitoring unit 45 monitors the voltage of
30 the power supply line P24A (step S1). If the power supply
line P24A is in the energized state (step S2: Yes), the
voltage monitoring unit 45 returns to step S1 and continues
the monitoring. If the power supply line P24A is in the
21
de-energized state (step S2: No), the voltage monitoring
unit 45 instructs the counter unit 47 to start counting.
The counter unit 47 performs counting at a timing of the
clock generated by the clock unit 46 (step S3). If the
counter unit 47 does not count the prescribed 5 number (step
S4: No), the counter unit 47 returns to step S3 and
continues the counting. If the counter unit 47 has counted
the prescribed number (step S4: Yes), the counter unit 47
drives the discharge circuit 30 (step S5). In the above10
described example, the counter unit 47 outputs a voltage at
which to turn on the transistor TR11 of the discharge
circuit 30. Consequently, the discharge circuit 30 starts
discharging the power storage circuit 20.
[0066] Next, a hardware configuration of the timer
15 circuit 40 will be described. The timer circuit 40 is
implemented by processing circuitry. The processing
circuitry may be a processor that executes a program stored
in a memory and the memory, or may be dedicated hardware.
[0067] FIG. 12 is a diagram illustrating an example of a
20 case where a processing circuitry included in the timer
circuit 40 of the slow-release relay circuit 10 according
to the third embodiment is configured with a processor and
a memory. In a case where the processing circuitry is
configured with a processor 91 and a memory 92, functions
25 of the processing circuitry of the timer circuit 40 are
implemented by software, firmware, or a combination of
software and firmware. The software or the firmware is
described as a program and stored in the memory 92. In the
processing circuitry, the processor 91 reads and executes
30 the program stored in the memory 92, thereby implementing
the functions. That is, the processing circuitry includes
the memory 92 for storing programs that results in the
timer circuit 40 executing processing. In other words,
22
these programs cause a computer to execute procedures and
methods of the timer circuit 40.
[0068] The processor 91 may be a central processing unit
(CPU), a processing device, an arithmetic device, a
microprocessor, a microcomputer, a digital 5 signal processor
(DSP), or the like. The memory 92 corresponds to, for
example, a non-volatile or volatile semiconductor memory
such as a random access memory (RAM), a read only memory
(ROM), a flash memory, an erasable programmable ROM (EPROM),
10 or an electrically EPROM (EEPROM (registered trademark)), a
magnetic disk, a flexible disk, an optical disk, a compact
disc, a mini disk, or a digital versatile disc (DVD).
[0069] FIG. 13 is a diagram illustrating an example of a
case where the processing circuitry included in the timer
15 circuit 40 of the slow-release relay circuit 10 according
to the third embodiment is configured with dedicated
hardware. In the case where the processing circuitry is
configured with dedicated hardware, processing circuitry 93
illustrated in FIG. 13 corresponds to, for example, a
20 single circuit, a composite circuit, a programmed processor,
a parallel programmed processor, an application specific
integrated circuit (ASIC), a field programmable gate array
(FPGA), or a combination thereof. Functions of the timer
circuit 40 may be separately implemented by the processing
25 circuitry 93, or the functions may be collectively
implemented by the processing circuitry 93.
[0070] A part of the functions of the timer circuit 40
may be implemented by dedicated hardware and another part
thereof may be implemented by software or firmware. Thus,
30 the processing circuitry can realize each of the abovedescribed
functions by dedicated hardware, software,
firmware, or a combination thereof.
[0071] As described above, according to the present
23
embodiment, in the slow-release relay circuit 10, the timer
circuit 40 is configured with a microcomputer or the like
including the clock unit 46, and controls a time for
driving the discharge circuit 30. Consequently, the slowrelease
relay circuit 10 can obtain the effect 5 described in
the first embodiment.
[0072] Fourth Embodiment.
A fourth embodiment will be described giving an
example in which a discharge circuit of a slow-release
10 relay circuit includes a fuse.
[0073] FIG. 14 is a diagram illustrating an example
configuration of a slow-release relay circuit 10a according
to the fourth embodiment. The slow-release relay circuit
10a includes a discharge circuit 30a replacing the
15 discharge circuit 30 of the slow-release relay circuit 10
according to the first embodiment illustrated in FIG. 1.
The discharge circuit 30a is the discharge circuit 30 with
a fuse F1 added thereto. A normal operation of the slowrelease
relay circuit 10a is similar to the operation of
20 the slow-release relay circuit 10 according to the first
embodiment.
[0074] Assume that a failure occurs that secures the
switch SW2 of the discharge circuit 30 of the slow-release
relay circuit 10 of the first embodiment to a closed
25 position. In that case, a short circuit is formed across
the capacitor C1 of the power storage circuit 20. As a
result, when the switch SW1 is closed, the slow-release
relay circuit 10 allows a current to continue flowing
through a path from the power supply line P24A toward the
30 diode D1 and the resistor R1.
[0075] In the fourth embodiment, the discharge circuit
30a includes the fuse F1. The fuse F1 is blown when the
current continues flowing through the above path for a
24
prescribed time or longer, such that the current can be
interrupted. The slow-release relay circuit 10a can
interrupt the current as the fuse F1 is blown when the
current continues flowing with the switch SW2 of the
discharge circuit 30a secured to the closed 5 position due to
the failure. As a result, the slow-release relay circuit
10a can prevent a secondary failure caused by the
continuous flowing of the current as the switch SW2 of the
discharge circuit 30a is secured to the closed position due
10 to the failure. When the switch SW2 of the discharge
circuit 30a is secured to the closed position due to the
failure, in addition, the slow-release relay circuit 10a
operates the switch SW1 to bring the relay RY1 from the
operating state to the return state.
15 [0076] For the slow-release relay circuit 10a according
to the present embodiment, as discussed above, the
discharge circuit 30a includes the fuse F1, and interrupts
an internal circuit when an overcurrent flows for a
prescribed time or longer. Consequently, the slow-release
20 relay circuit 10a can prevent a secondary failure due to
continuous flowing of the current.
[0077] Fifth Embodiment.
A fifth embodiment will be described giving an example
application of the slow-release relay circuit 10. The
25 slow-release relay circuit 10 may be any of the slowrelease
relay circuits 10 of the first to third embodiments,
and the slow-release relay circuit 10a of the fourth
embodiment is also applicable.
[0078] As described in “Background” section, the slow30
release relay circuit 10 is used for devices to be
installed on trains, and facilities such as railway signals
and railway crossings. The devices to be installed on
trains are, for example, train control devices. FIG. 15 is
25
a diagram illustrating an example configuration of a train
control device 100 according to the fifth embodiment. The
train control device 100 includes the slow-release relay
circuit 10. The train control device 100 operates the
slow-release relay circuit 10 with a digital 5 out signal,
for example. In a case where a power supply is interrupted,
the train control device 100 can operate the relay RY1 of
the slow-release relay circuit 10 after the lapse of a time
prescribed by the slow-release relay circuit 10.
10 [0079] The configurations described in each embodiment
above are merely examples of the content of the present
invention and can be combined with other known technology
and part thereof can be omitted or modified without
departing from the gist of the present invention.
15
Reference Signs List
[0080] 10, 10a slow-release relay circuit; 20 power
storage circuit; 30, 30a, 43 discharge circuit; 40 timer
circuit; 41 voltage comparator circuit; 42 reference
20 voltage circuit; 44 auxiliary circuit; 45 voltage
monitoring unit; 46 clock unit; 47 counter unit; 50
direct-current power supply; 100 train control device; C1,
C11, C12, C13 capacitor; D1, D11, D12 diode; F1 fuse;
IC11 voltage comparator; N24, P24, P24A power supply
25 line; R1, R2, R11, R12, R13, R14, R15, R16, R17 resistor;
RY1 relay; SW1, SW2 switch; TR11 transistor; ZD11, ZD12
Zener diode.
26
We Claim :
1. A slow-release relay circuit comprising:
a power storage circuit connected in parallel to a
relay including a coil;
a discharge circuit to release electrical 5 charge of
the power storage circuit; and
a timer circuit to, when detecting interruption of
supply of power to the relay, drive the discharge circuit
after a prescribed time.
10
2. The slow-release relay circuit according to claim 1,
wherein
the discharge circuit is a first discharge circuit,
and
15 the timer circuit includes:
a reference voltage circuit including: a first
capacitor; and a circuit connected in parallel to the first
capacitor and including a first constant-voltage diode and
a first resistor connected in series with the first
20 constant-voltage diode, the first constant-voltage diode
obtaining a first constant voltage, the reference voltage
circuit outputting a voltage obtained at the first
constant-voltage diode; and
a second discharge circuit including: a second
25 capacitor; and a second constant-voltage diode connected in
parallel to the second capacitor, the second constantvoltage
diode obtaining a second constant voltage higher
than the first constant voltage, the second discharge
circuit outputting a voltage obtained at the second
30 constant-voltage diode, and
the timer circuit compares a voltage output from the
reference voltage circuit with a voltage output from the
second discharge circuit, and drives the discharge circuit
27
when supply of power to the relay is interrupted and the
voltage output from the second discharge circuit becomes
equal to or lower than the voltage output from the
reference voltage circuit.
3. The slow-release relay circuit according to claim 1,
wherein
the timer circuit includes:
a voltage monitoring unit to detect interruption of
10 supply of power to the relay;
a counter unit to start counting after the voltage
monitoring unit detects the interruption of the supply of
power to the relay; and
a clock unit to generate a clock that is a period
15 during which the counter unit counts, and
the counter unit drives the discharge circuit upon
counting a prescribed number.
4. The slow-release relay circuit according to any one of
claims 1 to 3, wherein
the discharge circuit interrupts an internal circuit
when an overcurrent flows for a prescribed time or longer.
5. A train control device comprising the slow-release
25 relay circuit according to any one of claims 1 to 4.