Description:RELATED APPLICATION
[0001] The present application claims priority to U.S. Non-Provisional Patent Application No. 17/561,144 filed on 23 December 2021 and titled “SOC ARCHITECTURE TO REDUCE MEMORY BANDWIDTH BOTTLENECKS AND FACILITATE POWER MANAGEMENT” the entire disclosure of which is hereby incorporated by reference.

BACKGROUND

[0002] A computing system may comprise a discrete graphics system in which a graphics processing unit (GPU) is separate from a central processing unit (CPU). A system utilizing discrete graphics may comprise a memory used by the GPU that is different from a system memory used by the CPU. A system-on-chip (SoC) is an integrated circuit that combines different components, such as those traditionally associated with a processor-based system, into a single chip or, in some applications, within a small number of interconnected chips. In some systems, a GPU may be implemented by a SoC.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] FIG. 1 illustrates a system comprising an alternative memory path to graphics memory in accordance with certain embodiments.
[0004] FIG. 2 illustrates circuitry of the graphics SoC of FIG. 1 in accordance with certain embodiments.
[0005] FIG. 3 illustrates a memory port in accordance with certain embodiments.
[0006] FIG. 4 illustrates additional circuitry of the graphics SoC of FIG. 1 in accordance with certain embodiments.
[0007] FIG. 5 illustrates a bridge endpoint in accordance with certain embodiments.
[0008] FIG. 6 illustrates a memory bridge in accordance with certain embodiments.
[0009] FIG. 7 illustrates an example computer system in accordance with certain embodiments.
[0010] FIG. 8 illustrates a block diagram of components present in a computing system in accordance with various embodiments.
[0011] FIG. 9 illustrates a block diagram of another computing system in accordance with various embodiments.
[0012] Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0013] FIG. 1 illustrates a system 100 comprising an alternative memory path to graphics memory 106 in accordance with certain embodiments. System 100 includes a discrete graphics system on chip (SoC) 102 coupled to a host processing unit 104 (e.g., a central processing unit or other suitable processor) and a graphics memory 106. The SoC 102 may implement a graphics processing unit (GPU) that is separate from (e.g., on a different chip and/or package) the host processing unit 104. Host processing unit 104 is also coupled to system memory 108. SoC 102 includes graphics circuitry 110, including a compute engine 112, (which may also be referred to as a graphics engine or a rendering engine), system-on-chip (SoC) circuitry 114, memory port 116, and memory bridge 118. In various embodiments, the discrete graphics SoC 102 may comprise a single semiconductor chip or multiple semiconductor chips, e.g., in a common package (e.g., the graphics circuitry 110 may be implemented by a first chip, the SoC circuitry may be implemented by a second chip, and the memory bridge 118 and memory port 116 may be placed on either chip, a third chip, or split between multiple chips).
, Claims:1. A system comprising:
a discrete graphics system-on-chip (SoC) to couple to a host processor unit, the SoC comprising:
a memory bridge comprising:
a first port to receive requests sent by a compute engine through a first path to the memory; and
a second port to receive requests sent by a plurality of agents of the SoC through a second path to the memory.