DESC:TECHNICAL FIELD
[0001] The present invention relates generally to an Array Power Distribution Unit (APDU) in an Active Electronically Scanned Array RADARs. More specifically such systems employ Solid state power controllers (SSPC) to distribute the power to the Quad Transmit Receive Module (QTRMs) and for protection against damage from electrical fault conditions.
BACKGROUND

[0002] SSPC technology is gaining acceptance as a modern alternative to the traditional electromechanical contactors and circuit breakers, due to its high reliability, fast response time, ability to facilitate advanced load management and measurement of critical parameters. When SSPC is turned onto a large capacitive load like QTRM, the peak inrush current can be very high, and when multiple SSPC channels are turned on simultaneously during power-up process excessive high inrush current could result in stress in electrical components, therefore reducing their operational life, causing potential electric hazards, and EMI issues.
[0003] An APDU needs to supply high peak currents during the first turn on and pulsating currents when the radar is pulsing, this poses a significant challenge to the design of SSPC based APDU, since SSPCs often contain electronic circuitry which could be damaged or upset by the excessive peak currents or resulting in undesirable over current trips due to the inrush currents.
[0004] Further, as greater number of processing functions are demanded of the microprocessor with minimum latency, faster microprocessors must be substituted. Moreover, the special data processing required, such as the processing required for rapid short circuit protection of each channel, fault diagnostics and communication required between the SSPCs and the RADAR computer demands high-speed computations.

[0005] Advances in solid state and computer technology has resulted in the development of Solid State Power Controllers that offer the potential for fully automatic control, resulting in enhanced maintainability and reliability as well as significant weight savings.
[0006] One such approach in designing a Solid State Power Controller is described in U.S. Pat. No. 5,723,915. In the protection mechanism discussed, there is provided an I2RC section that produces an analog voltage proportional to the wire temperature rise or equivalently the energy stored in the wire and produces a trip signal when the maximum temperature-rise of the wire, simulated by a reference voltage is reached. The circuit reads the current in the wire in the form of a voltage signal across a shunt resistor serially connected to the wire. The signal is scaled and converted to a current by an amplifier stage, then squared, with the resultant applied to an RC integrator. The output voltage from the RC integrator is monitored by a comparator which has a threshold set by the referenced voltage according to the energy equation. The comparator provides a signal to trip the controller when the output voltage of the RC integrator reaches the threshold level. Through this trip signal, the current flow within the wire is interrupted by turning off the MOSFETS.
[0007] While this approach is effective, the output of the RC integrator follows an accurate I2RC trip characteristic only for constant DC input signals. In case of pulsed DC inputs such as the ones that are employed in most Radar applications, the RC integrator fails to provide an accurate I2RC trip characteristic.
[0008] The patent US 7,747,879 B2 discusses a Power Distribution System using Solid State Power Controllers. The SSPC includes a MOSFET that switches power from the line to the load. A low-side gate driver is used to drive the MOSFET. In applications requiring power to be supplied to multiple loads, each gate driver would need to be supplied with a separate supply. The present invention overcomes this problem by using floating gate drivers.
[0009] The SSPC in the patent mentioned above uses an 8-bit microcontroller. It is used to control the MOSFET gate drive. It senses the voltage of at least one terminal of MOSFET through voltage sensing circuitry. The current through the MOSFET is monitored by the microcontroller using current sensing circuitry. It is also used detect an overcurrent condition through I2RMST protection, and to communicate with external devices. This requires high speed computations by the microcontroller and requires a controller with faster processing speed than the one mentioned above.
[0010] There is still a need of a technical solution which solves the above defined problems to provide a Solid State Power Controller with improved accuracy, that includes the performance characteristics of traditional thermal circuit breakers and provides an accurate I2RMST trip characteristic for both constant and pulsed DC input signals and overcomes the drawbacks of protection circuits mentioned above.
SUMMARY
[0011] This summary is provided to introduce concepts related to an Array Power Distribution Unit (APDU) in an Active Electronically Scanned Array RADARs. More specifically such systems employ Solid State Power Controllers (SSPC) to distribute the power to the Quad Transmit Receive Module (QTRMs) and for protection against damage from electrical fault conditions.
[0012] In an embodiment of the present invention, a Solid State Power Controller (SSPC) with a plurality of channels used in Array Power Distribution Unit (APDU) to distribute power to a Quad Transmit Receive Module (QTRMs) and to protect against damage from electrical fault conditions is disclosed. Each channel of the SSPC comprises a current sense resistor which is connected in series with a load and the current flowing through the load is measured as a voltage drop across the sense resistor. A plurality of MOSFETs are connected in parallel to achieve high current rating, wherein the first terminal of the current sense resistor is coupled to an external voltage input and the second terminal is connected to the drain terminals of the MOSFETs. Further, the source terminals of the MOSFETs (1) are connected to the load. A gate driver drives a plurality of power switches. Further, a current sense circuitry amplifies a voltage drop across the current sense resistor. A voltage sense circuitry comprises a differential Op-Amp which scales and converts the output voltage for measurement. A short circuit and I2RMST protection circuitry receive the resultant voltage from the current sense circuitry which is proportional to the load current in a wire and to produce a trip signal when the maximum load current of the wire, simulated by the reference voltage, is reached.
[0013] In another embodiment of the present invention, the SSPC comprises a microcontroller, a plurality of General Purpose Inputs (GPI) IC inputs, a Analog to Digital Converter (ADC) ICs, a plurality of Digital to Analog Converter (DAC) ICs, a digital isolator, a temperature sensor, a plurality of opto-isolators, wherein the digital isolator enables communication between the microcontroller and the GPIs, ADCs and DACs through isolated SPI interface.
[0014] In another embodiment of the present invention, the SSPC utilizes the ADC inputs to measure the currents of the plurality of channels and to provide software over-current protection. It further utilizes the DAC outputs to set an instant trip threshold voltage and a minimum trip threshold voltage and it utilizes the GPIs to monitor the trip signals from the plurality of channels and to generate an interrupt when any one of the channels produce an overcurrent trip.
[0015] In another embodiment of the present invention, the plurality of opto-isolators transmits isolated control signals from the microcontroller to the gate driver of each channel, enabling noise-free transmission of control signals.
[0016] In another embodiment of the present invention, the differential Op-Amp which scales and converts the output voltage for measurement is done by ADC and then by the microcontroller for output voltage monitoring.

[0017] In another embodiment of the present invention, the short circuit and I2RMST protection circuitry includes a thermal memory based on which the short circuit and I2RMST protection circuitry reduces the trip time of a given load current level due to the previous load current flow.
[0018] In another embodiment of the present invention, the SSPC includes paralleling the plurality of channels with same current rating to supply power to higher loads and to allow the current rating of each channel to be programmed individually. It also configures the I2RMST energy limit to any value.
[0019] In another embodiment of the present invention, the SSPC provides sequential turn on and turn off of the plurality of channels with programmable sequence and programmable delay between the turn on and turn off.
[0020] In another embodiment of the present invention, the SSPC monitors the output status, the load status, the trip status, the output voltage and the output current of the plurality of channels of the SSPC through external communication on a Controller Area Network (CAN) or RS-485 (2-wire).

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0021] The following detailed description of the invention refers to the accompanying figures.
[0022] Figure 1 illustrates a block diagram of the SSPC, indicating multiple channels, the different sections in each channel, and its interface with the Logic control block, in accordance with an exemplary embodiment of the present invention.
[0023] Figure 2 illustrates a block diagram indicating the different sections of a channel of SSPC, in accordance with an exemplary embodiment of the present invention.
[0024] Figure 3 illustrates a block diagram exemplifying the interface of all channel outputs of the SSPC with the microcontroller, in accordance with an exemplary embodiment of the present invention.
[0025] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present invention. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION
[0026] The various embodiments of the present invention relates to an Array Power Distribution Unit (APDU) in an Active Electronically Scanned Array RADARs. More specifically such systems employ Solid State Power Controllers (SSPC) to distribute the power to the Quad Transmit Receive Module (QTRMs) and for protection against damage from electrical fault conditions.
[0027] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.
[0028] However, the methods and apparatuses are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the presently invention and are meant to avoid obscuring of the present invention.
[0029] Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.
[0030] The appearances of the phrase “in an embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
[0031] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0032] In an embodiment of the present invention, the present invention aims to address the challenges associated with the turn on and operation of large capacitive loads like QTRMs in an Active Electronically Scanned Array RADARs. The APDU comprises multiple SSPCs paralleled to extend the number of channels that supply power to the QTRMs. It further provides a solid state power controller that has multiple channels to supply power, a microcontroller that performs computations for rapid short circuit protection of each channel, communicates the status of each channel and fault diagnostics data to the RADAR computer.
[0033] In another embodiment of the present invention, the Solid State Power Controller includes a shunt resistor which is used as the sense element and N-channel MOSFETs as Solid State switching Devices, and high-side gate driver to drive the MOSFET gates. It further includes isolated control signals for the Gate driver of each channel - the microcontroller ground is completely isolated from the channel ground using opto-isolators, resulting in an isolated, noise-free transmission of the gate-drive control signals from the processor to the gate driver of each channel. Further, it includes the sequenced turn on/off of channels overcome overload conditions when supplying power to capacitive loads, with provision to program the on/off sequence and the delay between two turn on or turn off.
[0034] In another embodiment of the present invention, the SSPC includes voltage and current sense sections that use Op-Amps in non-inverting configuration to measure the output voltage and current of a channel, respectively. Further, it includes voltage and current monitoring through Analog to Digital Converters (ADCs) and its communication to the microcontroller through isolated SPI interface.
[0035] In another embodiment of the present invention, the SSPC is configured to generate precision reference voltage signals for setting trip thresholds of each channel through Digital to Analog Converters (DACs), programmable by the microcontroller through isolated SPI interface.
[0036] In another embodiment of the present invention, the SSPC includes rapid short circuit protection to instantly remove very high current faults and I2RMST protection section to remove the high current fault timely according to the energy equation of the MOSFET. The short circuit protection and I2RMST protection are implemented using analog circuitry. The protection circuit allows generation of trip signals for inputs above a minimum trip threshold voltage which is programmable. The averaging circuit included in this section produces voltage corresponding to the square of the RMS value of load current, producing true I2RMST trip curve for the pulsating currents of the RADAR.
[0037] In another embodiment of the present invention, the SSPC includes nuisance tripping of the SSPC due to high inrush currents supplied by the APDU during the turn on is avoided by the implementation of I2RMST energy measurement and ground isolation techniques.
[0038] In another embodiment of the present invention, the SSPC includes monitoring of trip signals from each channel of SSPC through General Purpose Inputs (GPIs), along with interrupt generation and communicating the trip status to the microcontroller through isolated SPI interface and the interrupt signal through high speed opto-isolator.
[0039] In another embodiment of the present invention, the SSPC includes isolated SPI interface between the ADCs, DACs and GPIs and the microcontroller through use of Digital Isolators, enhancing the noise immunity. Further, it includes software over-current and over-voltage protection by the microcontroller by monitoring the ADC current readings. Further, it includes communication with the RADAR computer using CAN interface or RS-485 two-wire interface. The output status, load status and trip status of all channels are monitored.
[0040] Figure 1 illustrates a block diagram of the SSPC, indicating multiple channels, the different sections in each channel, and its interface with the Logic control block, according to an exemplary embodiment of the present invention. Each channel of SSPC comprises a power switch that switches the input power on and off to the load and a sense circuitry that senses the output voltage and current through the channel. The Logic Control section comprises a microcontroller. This section drives the power switch of each channel, and monitors the voltage, current, and trip statuses from the sense section. The temperature sense inputs from the sensors A, B, C, D, E and monitored by the microcontroller to check for over-temperature conditions. The Logic Control block provides isolated CAN and RS-485 half-duplex interfaces for communication with the RADAR computer. The Bias supply generates isolated supplies for different parts of the circuit including the logic control section and voltage and current sense sections.
[0041] Figure 2 illustrates a block diagram indicating the different sections of a channel of SSPC, according to an exemplary embodiment of the present invention. The Sense resistor RSENSE is connected in series with the load and the current flowing through the load is measured as a voltage drop across the sense resistor. The SSPC employs N-channel MOSFETs 1 as switching element as they have lower on resistance. Two MOSFETs are connected in parallel to achieve high current rating. The first terminal of the sense resistor RSENSE is coupled to the external voltage input from the external connector. Its second terminal is connected to the drain terminals of both the MOSFETs. The source terminals of MOSFETs are connected to the load.
[0042] Block 2 represents a fast high side gate driver that drives the power switches. It receives isolated, noise-free control signals from the microcontroller through opto-isolator 13.
[0043] The function of the current sense circuitry 3 is to amplify the voltage drop across the sense resistor RSENSE, and provide the resultant voltage, which is proportional to the load current, as input to the Short circuit and I2RMST protection circuitry.
[0044] The output voltage sense section 4 comprises a differential Op-Amp which scales and converts the output voltage for measurement by ADC 7, and then by the microcontroller for output voltage monitoring.
[0045] The short circuit and IRMS2T Protection section 5 produces an analog voltage proportional to the energy stored in the wire and produces a trip signal when the maximum energy of the wire, simulated by a reference voltage, is reached. The circuit provides delayed tripping (based on the I2RMST energy measured), isolating the fault in a timely manner by preventing an overcurrent condition that exceeds the thermal capacity of the conductor. It also proves protection circuit that provides instantaneous tripping in response to short circuit and high current faults. This protection circuit includes a multiplier, an Averaging circuit, an Op-Amp Integrator, comparator for I2RMST trip and comparator for instantaneous trip and a wired OR circuit.
[0046] The protection circuit is configured to produce trip signals above a user programmable minimum trip threshold reference. In addition to this, the I2RMST Protection section offers Thermal memory. The circuit shortens the trip time of a given load current level due to previously stored energy in the wire, as a result of previous load current flow.
[0047] Figure 3 illustrates a block diagram exemplifying the interface of all channel outputs of the SSPC with the microcontroller, according to an exemplary embodiment of the present invention. Further, the connection of channel signals with ADCs, DACs and GPIs and the interface of these with the microcontroller through a Digital Isolator is provided. Each channel’s analog voltage and current data is input to Analog to Digital Converter (ADC) IC 7. The ADC outputs a serial digital data over SPI which is processed by the microcontroller 10 to provide software overcurrent protection by sending an off command when any channel’s load current exceeds the trip threshold voltage set according to the energy equation of the MOSFET (which can be configured to any energy limit level).
[0048] The input channels of ADC are coupled to the outputs of voltage and current sense section of channels, and the SPI lines of ADC carry the converted output signals and are coupled to the SPI lines of the Digital Isolator 9.
[0049] Digital to Analog Converter (DAC) ICs 8 are used to set the instant trip threshold voltage reference, based on the channel’s current rating, above which the channel will be switched off. DAC voltage is also used to program the DC offset provided to the multiplier of the protection circuit 5 to set the minimum trip threshold voltage. By programming the DAC output voltages, different trip time v/s load-current curves can be obtained.
[0050] The input to DAC is the serial data from the SPI lines of the Isolator 9. The DAC output comprises the minimum trip threshold voltage and the instant trip threshold voltage for each channel. The minimum trip threshold output is coupled to the offset input of the multiplier in protection circuit and the instant trip threshold output is coupled to the second input of second comparator of the protection circuit.
[0051] Each channel’s trip signal output is connected to the General Purpose Inputs (GPI) IC inputs. The GPI 6 has an interrupt output that is generated when one or more channels generate a trip signal (i.e., one or more inputs change state) This interrupt is received by the microcontroller 10 which reads the serial data from the GPI and issues the channel Off command to the tripped channel. Reading the serial data clears the interrupt.
[0052] The input channels of the GPI are coupled to the trip signal outputs of each channel. The output comprises of a trip interrupt which is input to the microcontroller 10 through opto-isolator 13, and serial data of the trip statuses of each channel that is read by the microcontroller through Digital Isolator 9 on SPI interface.
[0053] The Digital Isolator 9 provides an isolated SPI interface between the microcontroller SPI with that of ADC, DAC and GPI.
[0054] The temperature sensor 11 comprises five temperature sensors that sense the temperature at five different parts of the board and provide a voltage equivalent output to the microcontroller for processing and for providing protection against over-temperature conditions.
[0055] Each SSPC is assigned an address through address bits that are set externally. The address bit inputs are connected to the microcontroller inputs through opto-isolators 13. In addition to the address bits, there may be Discrete Control Options provided in order to reset and read the trip statuses and others through external signals.
[0056] The microcontroller provides an isolated CAN interface and an RS-485 Half-Duplex interface for communication with the RADAR computer. A CAN transceiver provides a galvanically-isolated interface between a Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus. Similarly, an RS-485 transceiver provides a galvanically-isolated interface between the microcontroller UART and RS-485 two wire Data+ and Data- lines.
[0057] In an exemplary embodiment, the present invention describes the design of SSPC with ‘n’ channels. Each channel of the SSPC comprises of a current sense resistor RSENSE 12, MOSFETs, Gate driver, current sense circuitry, Output Voltage sense circuitry, Input Voltage sense and a Short circuit protection and I2RMST protection circuitry. External Analog to Digital Converters (ADC), General Purpose Inputs (GPI) and Digital to Analog Converters (DAC), are interfaced with a microcontroller through isolated SPI interface. The microcontroller is used to read the current, voltage and trip statuses and command the Gate driver circuit to turn off the MOSFETs of a particular channel in case of fault conditions. The gate driver receives isolated control signals from the microcontroller through opto-isolators. Digital Isolators are used which act as interface between the microcontroller and ADC, DAC and GPI ICs, isolating the microcontroller ground from the channel ground.
[0058] In another exemplary embodiment, the present invention describes a Solid State Power Controller with multiple channels that supplies power to the load and provides fast, isolated and accurate I2RMST protection to the load and wire using analog circuitry. Each channel of SSPC comprises of a current sense resistor, MOSFETs, Gate driver, current sense circuitry, Output Voltage sense circuitry, and a Short circuit protection and I2RMST protection circuitry. The SSPC uses a microcontroller for data processing, fault diagnostics, and communication. A Digital Isolator with SPI is used to enable communication between the microcontroller and the ADCs, DACs and GPIs, while isolating their grounds from that of the microcontroller. Opto-isolators are used to transmit isolated control signals from the microcontroller to the Gate driver of each channel, enabling noise-free transmission of control signals.
[0059] In another exemplary embodiment, a Solid State Power Controller in which the I2RMST protection feature is implemented uses an analog circuit and provides thermal memory according to which, the circuit reduces the trip time when the energy stored in the circuit is already high from the previous overloads. The SSPC uses a programmable offset voltage signals to set the minimum trip voltage level, below which no trip signal is generated and to set the instant trip threshold voltage.
[0060] In another exemplary embodiment, a Solid State Power controller uses ADC inputs to measure the currents of all channels and provide software over-current protection, uses DAC outputs to set the instant trip threshold voltage, and to set the minimum trip threshold voltage, and uses GPIs (General Purpose Inputs) to monitor the trip signals from all channels and generate an interrupt when any of the channels produce an overcurrent trip.
[0061] In another exemplary embodiment, a Solid State Power Controller provides a feature for paralleling multiple channels with same current rating to supply power to higher loads, allows the current rating of each channel to be programmed, and provides a feature to configure the I2RMST energy limit to any value.
[0062] In another exemplary embodiment, a Solid State Power Controller provides feature of sequential turn On/Off of channels with programmable sequence and programmable delay between turn On/Off, avoiding very high inrush currents that could result from simultaneous switch on of all channels.
[0063] In another exemplary embodiment, a Solid State Power Controller allows the programming of current rating and load-present-status threshold, lower and upper voltage and current rages of channels individually, provides feature for monitoring the Output Status, Load Status, Trip Status, Output voltage, and Output current of all channels of the SSPC through external communication on CAN or RS-485 (2-wire).
[0064] In another exemplary embodiment, the present invention provides a Solid State Power Controller with multiple channels used in Array Power Distribution Unit (APDU) in an Active Electronically Scanned Array RADAR to distribute the power to the QTRMs and for protection against damage from electrical fault conditions. It comprises of a current sense element, a Solid State Switching Device (SSSD) such as a MOSFET, a Gate driver that receives isolated control signals to switch the MOSFET On and Off. It comprises of a voltage sensing circuitry and a current sensing circuitry configured to measure the output voltage and the load current respectively. It comprises of a microcontroller programmed to monitor the voltage and current readings through a data convertor such as ADC, through isolated SPI interface. It comprises of an over current protection circuit which provides both rapid short circuit protection and overload protection using I2RMST protection circuitry to protect wires and loads. Nuisance tripping due to peak inrush currents encountered during turn on and pulsed operation of the RADARs is avoided using I2RMST protection circuitry and using ground isolation. Sequenced turn on of channels is implemented to avoid excessive inrush currents that can be resulted from simultaneous turn on of channels to large capacitive loads like QTRMs.
[0065] In another exemplary embodiment, the present invention provides the trip thresholds for short circuit protection and I2RMST protection are programmed in the microcontroller and input to the protection circuitry through DAC. Trip signal generated by the protection circuit is continuously monitored and an interrupt is transmitted to the microcontroller to remove the MOSFET’s gate drive and cut off the power supply to the load.
[0066] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:
1. A Solid State Power Controller (SSPC) with a plurality of channels used in Array Power Distribution Unit (APDU) to distribute power to a Quad Transmit Receive Module (QTRMs) and to protect against damage from electrical fault conditions, wherein each channel of the SSPC comprises:
a current sense resistor (12) is connected in series with a load and the current flowing through the load is measured as a voltage drop across the sense resistor;
a plurality of MOSFETs (1) are connected in parallel to achieve high current rating, wherein the first terminal of the current sense resistor (12) is coupled to an external voltage input and the second terminal is connected to the drain terminals of the MOSFETs (1);
a gate driver (2) configured to drive a plurality of power switches;
a current sense circuitry (3) configured to amplify a voltage drop across the current sense resistor (12);
a voltage sense circuitry (4) comprises a differential Op-Amp which is configured to scale and convert the output voltage for measurement; and
a short circuit and I2RMST protection circuitry (5) is configured to receive the resultant voltage from the current sense circuitry (3) which is proportional to the load current in a wire and to produce a trip signal when the maximum load current of the wire, simulated by the reference voltage, is reached.

2. The SSPC as claimed in claim 1, wherein SSPC further comprises:
a microcontroller (10), a plurality of General Purpose Inputs (GPI) IC inputs (6), a Analog to Digital Converter (ADC) ICs (7), a plurality of Digital to Analog Converter (DAC) ICs (8), a digital isolator (9), a temperature sensor (11), a plurality of opto-isolators (13), wherein the digital isolator (9) is configured to enable communication between the microcontroller (10) and the GPIs (6), ADCs (7) and DACs (8) through isolated SPI interface.

3. The SSPC as claimed in claim 1 or claim 2, wherein the SSPC is further configured to:
utilize the ADC inputs to measure the currents of the plurality of channels and to provide software over-current protection;
utilize the DAC outputs to set an instant trip threshold voltage and a minimum trip threshold voltage; and
utilize the GPIs to monitor the trip signals from the plurality of channels and to generate an interrupt when any one of the channels produce an overcurrent trip.

4. The SSPC as claimed in claim 1, wherein the source terminals of the MOSFETs (1) are connected to the load.

5. The SSPC as claimed in claim 1 or claim 2, wherein the plurality of opto-isolators (13) are configured to transmit isolated control signals from the microcontroller (10) to the gate driver (2) of each channel, enabling noise-free transmission of control signals.

6. The SSPC as claimed in claim 1 or claim 2, wherein the differential Op-Amp which is configured to scale and convert the output voltage for measurement is done by ADC (7) and then by the microcontroller (10) for output voltage monitoring.

7. The SSPC as claimed in claim 1, wherein the short circuit and I2RMST protection circuitry (5) includes a thermal memory based on which the short circuit and I2RMST protection circuitry (5) is configured to reduce the trip time of a given load current level due to the previous load current flow.

8. The SSPC as claimed in claim 1, wherein the SSPC is further configured to:
parallel the plurality of channels with same current rating to supply power to higher loads;
allow the current rating of each channel to be programmed individually; and
configure the I2RMST energy limit to any value.

9. The SSPC as claimed in claim 1, wherein the SSPC is further configured to provide sequential turn on and turn off of the plurality of channels with programmable sequence and programmable delay between the turn on and turn off.

10. The SSPC as claimed in any one of claims 1 to 9, wherein the SSPC is further configured to monitor the output status, the load status, the trip status, the output voltage and the output current of the plurality of channels of the SSPC through external communication on a Controller Area Network (CAN) or RS-485 (2-wire).