Abstract: A step-up DC to DC voltage convertor (100) comprising a primary side circuit (104) and a secondary side circuit (106) operatively connected to the primary side circuit (104). The primary side circuit (104) includes at least one current transformer (CT), at least one switch (Q) operatively connected to the current transformer (CT), and a first taped inductor (L1) operatively connected to the at least one current transformer (CT). The at least one current transformer (CT) includes a first part of a primary winding and a secondary windings. The secondary side circuit includes a second taped inductor (L1), at least one clamped diode (D1), at least one rectifier diode (D2), at least one clamped capacitor (C1), and a second part of the primary windings (CT) operatively connected between the at least one clamped diode (D1) and the at least one rectifier diode (D2). Reference figure: FIG. 3
CLIAMS:I claim:
1. A step-up DC to DC voltage convertor, where in step-up DC to DC voltage convertor comprises:
a primary side circuit, wherein the primary side circuit comprises:
at least one current transformer, wherein the at least one current transformer includes a first part of a primary winding and a secondary windings;
at least one switch operatively connected to the current transformer; and
a first tapped inductor operatively connected to the at least one current transformer; and
a secondary side circuit operatively connected to the primary side circuit, wherein the secondary side circuit comprises:
a second taped inductor;
at least one clamped diode;
at least one rectifier diode;
at least one clamped capacitor; and
a second part of the primary windings operatively connected between the at least one clamped diode and the at least one rectifier diode.
2. The step-up DC to DC voltage convertor according to claim 1, wherein the at least one clamped capacitor is chosen, such that, during the ON state of the at least one switch, the at least one clamped capacitor discharges close to zero voltage, and the second tapped inductor current waveform is sinusoidal during the at least one clamped capacitor discharge.
3. The step-up DC to DC voltage convertor according to claim 1, further comprising a output filter circuit operatively connected to the secondary side circuit, wherein the output filter circuit is configured to perform the AC to DC conversion.
4. The step-up DC to DC voltage convertor according to claim 1, further comprising a feedback circuit, wherein the input of the feedback is taken across the output of the filter circuit and output of the feedback circuit drives the at least one switch of the primary side circuit.
5. The step-up DC to DC voltage convertor according to claim 4, wherein the feedback circuit comprises a voltage feedback system, a voltage command system, current mode control pulse width modulation system and a pulse width generator.
6. The step-up DC to DC voltage convertor according to claim 1, wherein the switch can be any transistor.
7. The step-up DC to DC voltage convertor according to claim 1, wherein the first tapped inductor and the second tapped inductor form a coupled inductor, which is modeled as an ideal transformer, a magnetizing inductor, and a leakage inductor.
8. The step-up DC to DC voltage convertor according to claim 1, wherein the winding ratio of the current transformer is calculated as (NL1 +NL2) / NL1; where ‘NL1’ indicate the number of turns of the first tapped inductor and ‘NL2’ indicate the number of turns of the second tapped inductor.
9. The step-up DC to DC voltage convertor according to claim 1, further comprising a DC input circuit operatively connected to the primary side circuit, and configured to receive and processes the source power received at the input of the current mode controlled DC to DC voltage convertor.
10. A step-up DC to DC voltage convertor as herein above described in the specification with reference to figures. ,TagSPECI:F O R M 2
THE PATENTS ACT, 1970
(39 of 1970)
COMPLETE SPECIFICATION
(See section 10; rule 13)
1. TITLE OF THE INVENTION
STEP-UP DC TO DC VOLTAGE CONVERTOR
2. APPLICANTS
a. Name: SPRYLOGIC TECHNOLOGIES LTD.
b. Nationality: An Indian company
c. Address: A1, Aplab House, Wagle Estate, Thane – 400604, Maharashtra, India
Complete specification:
The following specification particularly describes the invention and the manner in which it is to be performed.
BACKGROUND
Field of the subject matter
[0001] The subject matter relates to the field of step-up DC-DC voltage conversion, more particularly but not exclusively, to a current mode controlled step-up DC-DC voltage convertor.
Discussion of related field
[0002] High step up conversion without isolation is required in applications involving renewable energy sources, such as, Photo Voltaic (PV) panels, small wind turbines and fuel cells, among others. In order to deliver 1KW and above, these power sources are generally operated in parallel. In parallel operation, these sources are built with Maximum Power Point Tracking (MPPT) micro DC-DC converters. The DC-DC converter steps up the voltage in order to keep the current low for the same power.
[0003] The size of DC-DC converters is dependent on the losses in the overall system. High frequency operation with low losses reduces the size of energy storage components, such as, inductors, capacitors, resistors, and the like. However, operating at higher frequency introduces switching losses.
[0004] Conventional boost DC-DC converters with boost switches enable operation of the DC-DC converter at high frequencies. When the switch turns ON, current flows from the input DC side and rises with time. When current reaches a specific threshold value, the switch turns OFF. The threshold value is determined by a feedback control mechanism. However, for a high step-up voltage ratio, these conventional boost DC-DC converters are inefficient due to high switching losses.
[0005] One conventional technique tried to address this problem by incorporating a soft switching property to alleviate switching losses. This type of DC-DC converter has a coupled tapped inductor with a lower voltage rated boost switch to achieve a high voltage gain. The DC-DC converter with feedback control mechanism and its operation is structured to operate the switch over a wide-range of switching frequencies. However, to protect the switch, an additional snubber circuit is used to absorb the leakage inductor energy during switching, which compromises the efficiency of the DC-DC converter. Further, it is difficult to use feedback control mechanism with current mode control.
[0006] In light of the foregoing discussion, there is a need for an improved DC-DC converter to perform a high step-up voltage conversion with minimized losses and improved efficiency.
STATEMENT OF THE INVENTION
Accordingly, the invention provides a step-up DC to DC voltage convertor comprising a primary side circuit and a secondary side circuit operatively connected to the primary side circuit. The primary side circuit includes at least one current transformer, at least one switch operatively connected to the current transformer, and a first taped inductor operatively connected to the at least one current transformer. The at least one current transformer includes a first part of a primary winding and a secondary windings. The secondary side circuit includes a second taped inductor, at least one clamped diode, at least one rectifier diode, at least one clamped capacitor and a second part of the primary windings operatively connected between the at least one clamped diode and the at least one rectifier diode.
BRIEF DESCRIPTION OF DRAWINGS
[0007] Embodiments are illustrated by way of example and not limitation in the Figures of the accompanying drawings, in which like references indicate similar elements and in which:
[0008] FIG. 1 illustrates an example block diagram of a current mode controlled DC-DC high step-up voltage convertor 100, in accordance with an embodiment;
[0009] FIG. 2 illustrates an example block diagram of a feedback circuit 110, in accordance with an embodiment;
[0010] FIG. 3 illustrates an example schematic of the current mode controlled DC-DC high step-up voltage convertor 100, in accordance with an embodiment; and
[0011] FIG. 4 illustrates an example current waveform for the schematic of the current mode controlled DC-DC high step-up voltage convertor 100 illustrated in FIG.3, in accordance with an embodiment.
DETAILED DESCRIPTION
I. Overview
II. Exemplary Block diagram
III. Exemplary Schematic
IV. Exemplary Waveforms
V. Conclusion
I. OVERVIEW
[0012] The subject matter relates to the field of high step-up DC-DC voltage conversion, more particularly but not exclusively, to a current mode controlled high step-up DC to DC voltage convertor.
[0013] Embodiments disclose an improved technique to implement DC-DC converter to perform high step-up voltage conversion.
[0014] The improved technique uses current mode control to implement the DC-DC converter. Current mode control is achieved by incorporating a current transformer to sense the current in the primary side circuitry and update it to a feedback circuit. Further, the current transformer winding in a secondary side circuit can cancel the discharge current in the secondary side circuit. Further, a clamping capacitor is provided in the secondary side circuit. The lower value of the clamping capacitor in the secondary side circuit, puts the switch in close to Zero Voltage Switching (ZVS) operation and further helps in fast and stable operation of the DC-DC converter.
[0015] The following detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrations in accordance with example embodiments. These example embodiments, which are herein also referred to as “examples” are described in enough detail to enable those skilled in the art to practice the present subject matter. The embodiments can be combined, other embodiments can be utilized, or structural, logical, and electrical changes can be made without departing from the scope of what is claimed. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope is defined by the appended claims and their equivalents.
[0016] In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one. In this document, the term “or” is used to refer to a nonexclusive “or,” such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated.
II. EXEMPLARY BLOCK DIAGRAM
[0017] FIG. 1 illustrates an example block diagram 100 of a current mode controlled DC-DC high step-up voltage convertor, in accordance with an embodiment. The current mode controlled DC-DC high step-up voltage convertor 100 includes a DC input circuit 102, a primary side circuit 104, a secondary side circuit 106, an output filter circuit 108, and a feedback circuit 110.
[0018] The DC input circuit 102 is configured to receive and process source power received at the input of the current mode controlled DC-DC high step-up voltage convertor 100. The output of the DC input circuit 102 is fed to the primary side circuit 104. The primary side circuit 104 is configured to sense the current through the primary side and communicate the same to the feedback circuit 110 for controlling the operation (turning ON and OFF) of the switch included in the primary side circuit 104.
[0019] The secondary side circuit 106 is configured to cancel a discharge current and boost the voltage to a desired level and feed it to the output filter circuit 108. The output filter circuit 108 can be a rectifier circuit to perform the AC to DC conversion. The output of the output filter circuit 108 is applied to the load and the feedback circuit 110.
[0020] FIG. 2 illustrates an example block diagram 110 of the feedback circuit, in accordance with an embodiment. The feedback circuit includes a voltage feedback system 202, a voltage command system 204, a Current Mode Control Pulse Width Modulation (CMC-PWM) system 206 and a pulse width generator 208.
[0021] The voltage feedback system 202 is configured to receive the voltage from the output of the output filter circuit 108. Further, the received voltage is attenuated and fed to the CMC-PWM system 206. The voltage command system 204 is configured to store the desired output voltage and communicate the same to the CMC-PWM system 206.
[0022] The CMC-PWM system 206 is configured to sense the magnetizing current in the primary side circuit 104 and compare the voltage from voltage command system 204 and voltage feedback system 202. Further, the CMC-PWM system 206 generates an error signal. The error signal is fed to the pulse width generator 208. The pulse width generator 208 generates a waveform based on the signal received from the CMC-PWM system 206 to modify the operation of the switch in the primary side circuit 104.
III. EXEMPLARY SCHEMATIC
[0023] FIG. 3 illustrates an example schematic of the current mode controlled DC-DC high step-up voltage convertor 100, in accordance with an embodiment. The schematic includes different components organized as depicted in FIG. 3 to implement the functionality of each of the aforementioned blocks in FIG.1. The DC input circuit 102 includes a DC power source to supply DC input voltage VIN and input current IIN, and an input filter capacitor CIN.
[0024] The primary side circuit 104 includes a tapped inductor L1, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) boost switch denoted by Q and a current transformer CT with multiple windings placed operatively before the MOSFET boost switch Q in the circuit path. If NL1 corresponds to number of turns of tapped inductor L1 and NL2 corresponds to number of turns of tapped inductor L2, then to compensate for the winding of the tapped inductors L1 and L2, the winding ratio for the current transformer CT may be given by the equation (NL1 +NL2) / NL1.
[0025] A diode connected to the secondary of the current transformer CT will choose the proper current signal for current mode control during conduction of MOSFET boost switch Q.
[0026] The secondary side circuit 106 includes tapped inductor L2, high voltage capacitor C2, clamped diode D1, rectifier diode D2, clamped capacitor C1, and extra tapped CT winding in between the clamped diode D1 and the rectifier diode D2 with turn ratio same as the turn ratio of the tapped inductors L1 and L2. The tapped inductor L2 current is denoted by IL2. The tapped inductor L1 represents the primary side and the tapped inductor L2 represents the secondary side of the coupled inductor T1.
[0027] The output filter circuit 108 includes an output diode D0 and an output filter capacitor C0. The output of the output filter circuit 108 is connected to the load R0 with an output voltage V0 and an output current I0. The output voltage V0 is sensed by the voltage feedback system 202 of the feedback circuit 110. The current sensed by the current transformer CT is updated to the CMC-PWM system 206. Further, the pulse width generator 208 generates the drive pulse TQ to drive the MOSFET boost switch Q.
IV. EXEMPLARY WAVEFORMS
[0028] FIG. 4 illustrates an example current waveform for the schematic of the current mode controlled DC-DC high step-up voltage convertor 100 illustrated in FIG.3, in accordance with an embodiment. The feedback circuit 110 provides a drive pulse TQ, which turns ON the MOSFET boost switch Q and the MOSFET boost switch Q starts conducting. The output at the secondary end of the tapped inductor L2 goes negative, which in turn forces the output of the high voltage capacitor C2 to go negative. This action sets up current from clamped capacitor C1 through rectifier diode D2.
[0029] The value of the clamped capacitor C1 is chosen such that, during the ON state of the MOSFET boost switch Q, the clamped capacitor C1 discharges close to zero voltage and the tapped inductor L2 current waveform IL2 is sinusoidal during this discharge.
[0030] The current through the tapped inductor L2 reflects in tapped inductor L1 due to the transformer action of the coupled inductors L1 and L2. Hence, the current through the MOSFET boost switch Q is sum of the currents through the tapped inductor L1 and L2 i.e. IL1 and IL2 respectively. By passing opposite polarity ampere-turns through current transformer CT the ampere-turns of the primary of the current transformer CT are canceled, leaving only the inductive current of the L1 as signal to the secondary winding of current transformer CT.
[0031] Since the extra tapped CT winding of the secondary side circuit 106 cancels the discharge current of clamped capacitor C1, the current through the current transformer CT will be the linearly rising tapped inductor magnetizing current IL1. As the value of clamped capacitor C1 is chosen such that, it can discharge close to zero voltage during the ON state of the MOSFET boost switch Q, the drain voltage of the MOSFET boost switch Q during the OFF state cannot directly rise to final value.
[0032] The drain voltage of the MOSFET boost switch Q rises to the voltage of clamped capacitor C1 and further, through the current of the tapped inductor L1, it rises to the final value. This operation helps in minimizing the switching losses of the MOSFET boost switch Q. The diode across the primary side of the current transformer CT provides magnetic reset for the CT so that it gets ready for measuring next cycle with accuracy.
[0033] The coupled inductor T1 of the current mode controlled DC-DC high step-up voltage convertor 100 is modeled as an ideal transformer, a magnetizing inductor LM, and a leakage inductor LK.
[0034] The operation of the current mode controlled DC-DC high step-up voltage convertor 100 during the ON and OFF state of MOSFET boost switch Q is explained in four periodic modes.
[0035] During the Mode 1 (t0-t1), the MOSFET boost switch Q is turned ON. Error amplifier in the CMC-PWM system 206 sets target for the current through the magnetizing inductor LM. Further, the MOSFET boost switch Q remains ON until the current reaches the desired value decided by the CMC-PWM system 206. The input source voltage VIN passes through the magnetizing inductor LM raising the magnetizing ILM current linearly.
[0036] The secondary voltage VL2 and the voltage through the clamping capacitor C1 are connected in series to charge the high-voltage capacitor C2 through the MOSFET boost switch Q and the rectifier diode D2. Thus, the magnitude of secondary current IL2 is reduced resonantly and the voltage across the high-voltage capacitor C2 is increased until the capacitor C1 voltage drops to zero. Once this clamping capacitor C1 is completely discharged, it can reduce turn OFF loss significantly.
[0037] During the Mode 2 (t1- t2), the MOSFET boost switch Q is turned off. At this time, the primary current IL1 and secondary current IL2 of the coupled inductor T1 start to charge the parasitic capacitor of the MOSFET boost switch Q. At the same time, the clamping capacitor C1 is charged through the diode D1. The total current is transferred to the capacitor C1. Since the parasitic capacitors are small, the voltage across the switch rises until complete leakage energy in primary side LK is stored into the resonant capacitor C1. The diode D1 has same voltage rating as the MOSFET boost switch Q. Therefore, low forward drop and fast recovery Schottky diode can be used to save losses.
[0038] During the Mode 3 (t2- t3), after releasing the leakage energy from the secondary side of the coupled inductor T1, the current through the inductor IL2 assumes the same direction as boost current but lower in magnitude depending on the turns ratio. This is redistribution of the magnetizing current in magnetizing inductor LM, which will change to IL2 value through secondary part of the tapped inductor L2. The current through secondary reaches to final value of IL2. The voltage at the output reverse biases the diode D2. The reverse bias voltage is VO minus voltage across capacitor C1.
[0039] During the Mode 4 (t3 –t4), at time t = t3, the reverse voltage across output diode DO decays to zero and starts to conduct, and the rectifier diode D2 is cut off. At this time, all the series voltages i.e. the input voltage VIN, voltage across the leakage inductor, primary winding voltage VLM, VC2 and VL2 charges the output capacitor C0 and supplies to the output load R0. The current for major part of the period is decided by law of conservation of magnetic energy or approximately same ampere turns appear through NL1 +NL2 to reduce the current to IL2 through the secondary windings and capacitor C2. The capacitor C2 discharges and IL2 decreases until the beginning of the next cycle.
[0040] The secondary current IL2 is a resonant current. The resonance current is significantly large but lasts for a shorter duration. The frequency of resonance is decided by primary leakage inductance LK of the transformer and capacitor C1 in series with high value capacitor C2. (Since C2 is one order higher, the value of series combination can be treated same as the value of C2). The current IL2 passes through the CT compensating secondary winding. The secondary current IL2 reflects as IL1 through tapped inductor L1 section. The ratio of currents IL1 and IL2 is same as the turn ratio of L1 and L2. The cancellation winding on CT is larger for IL2. As a result the resonant current gets cancelled. The remaining current read by the CT represents magnetizing current ILM. Thus, the current transformer CT prevents the resonant current, which affects the control action.
V. CONCLUSION
[0041] The aforementioned step-up DC-DC voltage convertor achieves current mode control by using a current transformer. Further, the soft turn OFF feature by using a lower value clamped capacitor minimizes switching losses, thereby improving the efficiency.
[0042] Although, embodiments have been described with reference to specific example embodiments, it will be evident that various modifications, arrangements of components and changes may be made to these embodiments without departing from the broader spirit and scope of the current mode controlled DC-DC voltage convertor described herein. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
[0043] Many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. It is to be understood that the description above contains many specifications, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the personally preferred embodiments of this invention. Thus the scope of the invention should be determined by the appended claims and their legal equivalents rather than by the examples given.
CLAIMS
I claim:
1. A step-up DC to DC voltage convertor, where in step-up DC to DC voltage convertor comprises:
a primary side circuit, wherein the primary side circuit comprises:
at least one current transformer, wherein the at least one current transformer includes a first part of a primary winding and a secondary windings;
at least one switch operatively connected to the current transformer; and
a first tapped inductor operatively connected to the at least one current transformer; and
a secondary side circuit operatively connected to the primary side circuit, wherein the secondary side circuit comprises:
a second taped inductor;
at least one clamped diode;
at least one rectifier diode;
at least one clamped capacitor; and
a second part of the primary windings operatively connected between the at least one clamped diode and the at least one rectifier diode.
2. The step-up DC to DC voltage convertor according to claim 1, wherein the at least one clamped capacitor is chosen, such that, during the ON state of the at least one switch, the at least one clamped capacitor discharges close to zero voltage, and the second tapped inductor current waveform is sinusoidal during the at least one clamped capacitor discharge.
3. The step-up DC to DC voltage convertor according to claim 1, further comprising a output filter circuit operatively connected to the secondary side circuit, wherein the output filter circuit is configured to perform the AC to DC conversion.
4. The step-up DC to DC voltage convertor according to claim 1, further comprising a feedback circuit, wherein the input of the feedback is taken across the output of the filter circuit and output of the feedback circuit drives the at least one switch of the primary side circuit.
5. The step-up DC to DC voltage convertor according to claim 4, wherein the feedback circuit comprises a voltage feedback system, a voltage command system, current mode control pulse width modulation system and a pulse width generator.
6. The step-up DC to DC voltage convertor according to claim 1, wherein the switch can be any transistor.
7. The step-up DC to DC voltage convertor according to claim 1, wherein the first tapped inductor and the second tapped inductor form a coupled inductor, which is modeled as an ideal transformer, a magnetizing inductor, and a leakage inductor.
8. The step-up DC to DC voltage convertor according to claim 1, wherein the winding ratio of the current transformer is calculated as (NL1 +NL2) / NL1; where ‘NL1’ indicate the number of turns of the first tapped inductor and ‘NL2’ indicate the number of turns of the second tapped inductor.
9. The step-up DC to DC voltage convertor according to claim 1, further comprising a DC input circuit operatively connected to the primary side circuit, and configured to receive and processes the source power received at the input of the current mode controlled DC to DC voltage convertor.
10. A step-up DC to DC voltage convertor as herein above described in the specification with reference to figures.
ABSTRACT
A step-up DC to DC voltage convertor (100) comprising a primary side circuit (104) and a secondary side circuit (106) operatively connected to the primary side circuit (104). The primary side circuit (104) includes at least one current transformer (CT), at least one switch (Q) operatively connected to the current transformer (CT), and a first taped inductor (L1) operatively connected to the at least one current transformer (CT). The at least one current transformer (CT) includes a first part of a primary winding and a secondary windings. The secondary side circuit includes a second taped inductor (L1), at least one clamped diode (D1), at least one rectifier diode (D2), at least one clamped capacitor (C1), and a second part of the primary windings (CT) operatively connected between the at least one clamped diode (D1) and the at least one rectifier diode (D2).
Reference figure: FIG. 3
| # | Name | Date |
|---|---|---|
| 1 | 1838-MUM-2013-POWER OF ATTORNEY-(13-06-2016).pdf | 2016-06-13 |
| 1 | 1838-MUM-2013-RELEVANT DOCUMENTS [28-09-2023(online)].pdf | 2023-09-28 |
| 2 | 1838-MUM-2013-CORRESPONDENCE-(13-06-2016).pdf | 2016-06-13 |
| 2 | 1838-MUM-2013-RELEVANT DOCUMENTS [29-09-2022(online)].pdf | 2022-09-29 |
| 3 | MSME Registration.pdf | 2018-08-11 |
| 3 | 1838-MUM-2013- ORIGINAL UR 6(1A) ASSIGNMENT-021120.pdf | 2021-10-03 |
| 4 | Form 5.pdf | 2018-08-11 |
| 4 | 1838-MUM-2013-US(14)-HearingNotice-(HearingDate-12-10-2020).pdf | 2021-10-03 |
| 5 | Form 3.pdf | 2018-08-11 |
| 5 | 1838-MUM-2013-IntimationOfGrant24-12-2020.pdf | 2020-12-24 |
| 6 | Form 28.pdf | 2018-08-11 |
| 6 | 1838-MUM-2013-PatentCertificate24-12-2020.pdf | 2020-12-24 |
| 7 | Form 26.pdf | 2018-08-11 |
| 7 | 1838-MUM-2013-AMMENDED DOCUMENTS [27-10-2020(online)].pdf | 2020-10-27 |
| 8 | Form 2.pdf | 2018-08-11 |
| 8 | 1838-MUM-2013-FORM 13 [27-10-2020(online)].pdf | 2020-10-27 |
| 9 | 1838-MUM-2013-MARKED COPIES OF AMENDEMENTS [27-10-2020(online)].pdf | 2020-10-27 |
| 9 | Drawings.pdf | 2018-08-11 |
| 10 | 1838-MUM-2013-Proof of Right [27-10-2020(online)].pdf | 2020-10-27 |
| 10 | Abst FIG. 3.jpg | 2018-08-11 |
| 11 | 1838-MUM-2013-FER.pdf | 2018-12-05 |
| 11 | 1838-MUM-2013-Written submissions and relevant documents [27-10-2020(online)].pdf | 2020-10-27 |
| 12 | 1838-MUM-2013-MARKED COPIES OF AMENDEMENTS [04-06-2019(online)].pdf | 2019-06-04 |
| 12 | 1838-MUM-2013-Response to office action [09-10-2020(online)].pdf | 2020-10-09 |
| 13 | 1838-MUM-2013-Correspondence to notify the Controller [11-09-2020(online)].pdf | 2020-09-11 |
| 13 | 1838-MUM-2013-FORM 13 [04-06-2019(online)].pdf | 2019-06-04 |
| 14 | 1838-MUM-2013-ABSTRACT [04-06-2019(online)].pdf | 2019-06-04 |
| 14 | 1838-MUM-2013-FER_SER_REPLY [04-06-2019(online)].pdf | 2019-06-04 |
| 15 | 1838-MUM-2013-AMMENDED DOCUMENTS [04-06-2019(online)].pdf | 2019-06-04 |
| 15 | 1838-MUM-2013-COMPLETE SPECIFICATION [04-06-2019(online)].pdf | 2019-06-04 |
| 16 | 1838-MUM-2013-CLAIMS [04-06-2019(online)].pdf | 2019-06-04 |
| 17 | 1838-MUM-2013-COMPLETE SPECIFICATION [04-06-2019(online)].pdf | 2019-06-04 |
| 17 | 1838-MUM-2013-AMMENDED DOCUMENTS [04-06-2019(online)].pdf | 2019-06-04 |
| 18 | 1838-MUM-2013-ABSTRACT [04-06-2019(online)].pdf | 2019-06-04 |
| 19 | 1838-MUM-2013-Correspondence to notify the Controller [11-09-2020(online)].pdf | 2020-09-11 |
| 20 | 1838-MUM-2013-Response to office action [09-10-2020(online)].pdf | 2020-10-09 |
| 21 | 1838-MUM-2013-Written submissions and relevant documents [27-10-2020(online)].pdf | 2020-10-27 |
| 22 | 1838-MUM-2013-Proof of Right [27-10-2020(online)].pdf | 2020-10-27 |
| 23 | 1838-MUM-2013-MARKED COPIES OF AMENDEMENTS [27-10-2020(online)].pdf | 2020-10-27 |
| 24 | 1838-MUM-2013-FORM 13 [27-10-2020(online)].pdf | 2020-10-27 |
| 25 | 1838-MUM-2013-AMMENDED DOCUMENTS [27-10-2020(online)].pdf | 2020-10-27 |
| 26 | 1838-MUM-2013-PatentCertificate24-12-2020.pdf | 2020-12-24 |
| 27 | 1838-MUM-2013-IntimationOfGrant24-12-2020.pdf | 2020-12-24 |
| 28 | 1838-MUM-2013-US(14)-HearingNotice-(HearingDate-12-10-2020).pdf | 2021-10-03 |
| 29 | 1838-MUM-2013- ORIGINAL UR 6(1A) ASSIGNMENT-021120.pdf | 2021-10-03 |
| 30 | 1838-MUM-2013-RELEVANT DOCUMENTS [29-09-2022(online)].pdf | 2022-09-29 |
| 31 | 1838-MUM-2013-RELEVANT DOCUMENTS [28-09-2023(online)].pdf | 2023-09-28 |
| 32 | 1838-MUM-2013-FORM FOR SMALL ENTITY [04-06-2025(online)].pdf | 2025-06-04 |
| 33 | 1838-MUM-2013-EVIDENCE FOR REGISTRATION UNDER SSI [04-06-2025(online)].pdf | 2025-06-04 |
| 1 | srchAE_10-03-2020.pdf |
| 2 | GooglePatentSearch_09-11-2018.pdf |