Description
Title of Invention: STORAGE SYSTEM AND STORAGE
APPARATUS
Technical Field
[0001] The present inve~ltionr elates to technology for operating a redundancy code stored in
a storage apparatus.
Background Art
[0002] A technology for configuring a RAID (Redundant Array of Independent Disks) and
preventing the loss of data in accordance with a storage systein controller controlling
multiple storage devices is known. For example, in a storage system, which uses RAID
5, the storage systein controller, which is equivalent to a higher-level apparatus with
respect to the storage device, creates parity from multiple data blocks.
[0003] There is a storage systein in which the respective storage devices, which are
equivalent to lower-level apparatuses, configure a RAID in order to reduce the
processing of the storage systein controller pursuailt to creating the parity ineiltiolled
hereiaabove. Each storage device, for example, is a HDD (Hard Disk Diive), and the
controller of each HDD (hereinafter, HDD controller) creates parity.
[0004] For example, in Patent Literature 1, when there is a data update request with respect
to pre-update data (old data), the HDD colltroller updates the old data to new data after
creating an interlnediate value (interinediate paiity) for creating parity from the
updated data (new data) and the pre-update data (old data). The HDD controller
transfers the created iiltennediate parity to the HDD in which an old paiity conespollding
to the old data is being stored. In the HDD, which receives the intermediate
parity, the HDD controller creates new parity from the iilterinediate parity and the old
parity, and updates the old data with the created new parity.
[0005] 111 line with the lowerii~go f flash ineinory piices in recent years, Flash SSD (Flash
Solid State Drive) has been iilcreasiilgly used in place of HDD as a storage device. In
the HDD, when there is an update request with respect to data identified by a certain
range of logical addresses, updated data (new data) is overwritten to the physical area
in which the relevant data (old data) is stored. However, ill the Flash SSD, since the
ovelwsiting of data is not possible, when there is an update request for data identified
by a logical address, the updated data is stored in a physical area, which differs from
the physical area in which the relevant data is stored, and the new physical area is
mapped to the identified logical address. In accordance with this, the physical area ill
which the old data is stored in the Flash SSD is made illvalid.
Citation List
Patent Literature
j0006) PTL 1: US5,191,584
Summary of Invention
Technical Problem
[0007] In Patent Literature 1, since the old data is overwritten with the new data after the intermediate
parity has been created, the old data ceases to exist subsequellt to the
creation of the intermediate parity. For this reason, in a case where a failure occurs
prior to parity being updated (for example, psior to transferring the interlnediate paiity
to the HDD in which the old paiity is being stored) and the intermediate parity is lost,
the old data no longer exists, and as such, intermediate parity cannot be created again.
[0008] Alternatively, in a case where the stosage device has been replaced with Flash SSD,
since data is not overwritten in the flash memory, there is the likelihood that the old
data will remain subsequent to the intermediate pa~ityh aving been created. However,
in the Flash SSD, the physical area storing the old data is invalidated when new data is
written, and the old data is deleted at a presclibed time. That is, in the Flash SSD, there
is the likelihood that the old data will no longer exist when a failure occurs, in which
case, intermediate parity will not be able to be created the same as in the Cited
Doculnent 1.
Solution to Problem
[0009] A storage system, which is one aspect of the present invention, coinplises a first
controller and a plurality of storage devices. The Plurality of storage devices configure
RAID, each of which includes one or more non-volatile memory chips providing
storage space where data from a host computer is stored, and a second controller
coupled to the non-volatile lneinoly chips. In case where the first controller receives an
update request to update first data to second data, the second controller in a first
storage device of the storage devices is configured to store the second data in an area
different from an area where the first data has been stored, in the storage space of the
first storage device; generate inforination that relates the first data and the second data;
and generate an intermediate parity based on the first and the second data. The second
controller in a second storage device of the storage devices that stores a fixst parity corresponding
to the first data is configured to receive the inter~nediatep arity, generate a
second parity based 011 the first parity and the intermediate parity, and store the second
pality in an area in the storage space of the second storage device. The second
controller in the fisst storage device is configured to delete the infoilnation after the
second parity is stored in the area in the storage space of the second storage device,
and set the area where the fisst data has been stored as a erase target area.
Brief Description of Drawings
[OOIO] [fig. 11Fig. 1 shows an exainple of the configuration of a storage system.
[fig.2]Fig. 2 shows an example of the configuration of a syste~nc ontroller 20.
Jfig.3jFig. 3 shows an exainple of the configuration of a coinputer systein related to
Example 1.
[fig.4]Fig. 4 shows an example of the configurations of a RG and a LU.
[fig.S]Fig. 5 shows an example of a RG management table 600.
[fig.G]Fig. 6 shows an exainple of a LU management table 700.
[fig.7]Fig. 7 shows an exainple of a FMPK management table 800.
[fig.8]Fig. 8 shows an exainple of an address space on a RG.
[fig.S)]Fig. 9 shows an example of an address space on a FMPK 50 belonging to a RG.
[fig.lO]Fig. 10 shows an example of page mapping in a FMPK 50.
[fig. 1 l]Fig. 1 1 shows an example of a page mapping management table 1100.
[fig. l2lFig. 12 shows an example of a parity operation f~inctionre gistration process.
[fig.l3]Fig. 13 shows an example of a method 1300 for deciding a paiity operation implementation
apparatus.
[fig. 141Fig. 14 shows an example of a systein controller 20 write process.
[fig. 151Fig. 15 shows an example of a first parity operation selection process.
[fig. 16lFig. 16 shows an example of a second parity operation selection process.
[fig. 171Fig. 17 shows an example of a third parity operation selection process.
[fig.l8]Fig. 18 shows an example of a fourth paiity operation selection process.
[fig.lB]Fig. 19 shows an example of a write method selection process 1403.
[fig.20]Fig. 20 shows an example of a first read-modify-write process.
[fig.2l]Fig. 21 shows an example of the operation of the storage controller 20 in the
first read-modify-write process.
[fig.22]Fig. 22 shows an exainple of a second read-modify-write process.
[fig.23jFig. 23 shows an example of the operation of the storage controller 20 in the
second read-modify-write process.
[fig.24]Fig. 24 shows an exainple of a third read-modify-write process.
[fig.25]Fig. 25 shows an example of the operation of the storage controller 20 in the
third read-modify-wiite process.
[fig.26]Fig. 26 shows an example of a first f~i11-stripew rite process.
lfig.271Fig. 27 shows an exainple of the operation of the storage controller 20 in the
first full-stripe write process.
[fig.28]Fig. 28 shows an exainple of a secolld f~~ll-striwperi te process.
[fig.29]Fig. 29 shows an example of the operation of the storage controller 20 in the
second filll-stripe write process.
[fig.30]Fig. 30 shows an example of a first data restoration process.
[fig.31]Fig. 31 shows an example of the operation of the storage controller 20 in the
first data restoration process.
[fig.32]Fig. 32 shows an example of a second data restoration process.
[fig.33]Fig. 33 shows an example of the operation of the storage controller 20 in the
second data restoration process.
[fig.34]Fig. 34 shows an example of the processing of a device controller 60 in accordance
with a normnal write command.
[fig.35]Fig. 35 shows an exalnple of the processing of the device controller 60 ill accordance
with an old-data-store wmite command.
[fig.361Fig. 36 shows an exalnple of the processing of the device controller 60 in accordance
with a inteilnediate parity read command.
[fig.37]Fig. 37 shows an exalnple of the processing of the device controller 60 in accordance
with a parity-update write command.
[fig.38]Fig. 38 shows an example of the processing of the device controller 60 in accordai~
cew ith a parity-create write command.
[fig.39]Fig. 39 shows an example of an old data unmap process by the device
controller 60;
[fig.4O]Fig. 40 shows an example of a Q-parity creation method.
[fig.41]Fig. 41 shows an example of a DO, Dl restoration method.
[fig.42]Fig. 42 shows an exalnple of a fourth read-modify-write process.
[fig.43]Fig. 43 shows an example of the operation of the storage controller 20 in the
fourth read-modify-write process.
Lfig.44JFig. 44 shows an example of the configuration of a computer system related to
Example 3.
[fig.45]Fig. 45 shows an example of the configuration of a computer system related to
Example 4.
Description of Einbodiments
[0011] A number of examples will be explained. The technical scope of the present
invention is iiot limited to the examples.
[0012] In the followiiig explanation. various types of information may be explained using
the expression "*** table", but the various information may also be expressed using a
data structure other than a table. To show that the various informatioil is iiot dependent
on the data str~icture",* 4:'v table" call be called "*** information".
[0013] I11 the following explanation. there inay be cases where the processing is explained
having a "program" as the doer of the action. The stipulated processing is performed in
accordance with a program being executed by a processor (for example, a CPU
(Central Processing Unit)) while using a storage resource (for example, a memory) and
a coinin~uiication control device (for example, a communicatioil port) as needed, and
as such, the processor may also be the doer of the processing. A process, which is
explained having a program as the doer of the action may be a process performed by a
lnallageineilt system. Either all or part of the program inay be realized using dedicated
hardware. For this reason, a process, which is explained having a prograin as the doer
of the action inay be a process pel-formed by a controller. The controller may comprise
a processor, and a storage resource for storing a computer program to be executed by
the processor, or may complise the above-mentioned dedicated hardware. The
coinputer program may be installed in respective computers from a program source.
The program source, for example, may be either a program delivery server or a storage
medium.
[0014] In the following explanation, a manageinent system is either one or more computers,
for example, inanageineilt computers, or a combination of a inaliageineilt computer and
a display computer. Specifically, for example, in a case where the management
computer displays display infoimation, the inailageinellt cornputer is the inanagelneilt
system. The same function as the management computer may be realized using
multiple computers to increase processing speed and reliability, and in accordance with
this, the relevant inultiple computers (may comprise a display coinputer when a display
is carried out on a display computer) are the inailagemellt system.
Example 1
[0015] First, the coilfiguratioll of a storage system, which is an exainple of the application of
the present invention, will be explained.
[0016] Fig. 1 shows an exainple of the configuration of a storage system 30. This storage
systein 30 comprises multiple storage apparatuses 50 for storing data, and a systein
controller 20, which is coupled to these m~lltiples torage apparatuses. The storage
apparatus, for example, is a FMPK (Flash Meinory Package) 50.
100171 The FMPK 50 compiises a llonvolatile memoly for stoiiilg data, and a device
coiltroller 60, which is coupled to the nonvolatile meinoly and the systein controller
20. The nonvolatile memoly, for exainple, is a NAND-type FM (Flash Memory) 55.
The nonvolatile meinoiy is not limited to a flash memory. and may be a recordable
memory (for example, a phase-change memoly). The device controller 60 comprises a
coinmul~icationin terface device, a storage device, and a control device coupled
thereto. The communication interface devices, for example, are a systein intei-face 53
and a FM interface 54. In the following explanation, interface inay be denoted as I/F.
The systein LIF 53 is coupled to the systein controller 20. The FM IIF 54 is coupled to
the FM 55.
1001 81 The storage device, for exainple, is a memory 52 and a buffer 66. The control device,
for exainple, is a CPU 5 1. The colltrol device, ill addition to a processor such as the
CPU 5 1, may comprise a dedicated hardware circuit for performing presclibed
processing (for example, compression, decompression, coding or decoding). The
dedicated hardware circuit, for example, is a parity circuit 65 for computing either
pality or a intermediate parity. The memory 52 stores a program and various types of
infoilnation for controlling the FM 55. The CPU 51 realizes various types of f~~nctions
in accordance with executing the program stored in the memory 52. The buffer 66, for
example, is a volatile memory, such as a DRAM (Dynamic Random Access Memory).
The buffer 66 temporarily stores data to be written to the FM 55, data read from the
FM 55, and data during a parity operation.
[0019] The FMPK 50 may comprise multiple FMs 55. The multiple FMs 55 may comprise
different types of storage media or may be the same type of storage media. For
example, the FM 55 may comprise multiple physical blocks. The physical blocks may
coinprise multiple physical pages. Each cell inside the FM 55 may be a SLC (Single
Level Cell) or a MLC (Multiple Level Cell). The nonvolatile memory may be another
nonvolatile memory or may be a recordable memory, such as a phase-change memory.
[0020] Fig. 2 shows the configuration of the system controller 20. The system controller 20
colnprises a communication interface device, a storage device, and a control device,
which is coupled thereto. The communicatioil interface devices, for example, are a
commuilication I/F 18 for coupling to a communication network and a disk I/F 19 for
coupling to the FMPK 50. The storage devices, for exainple, are a memory 12 and a
buffer 26. The control device, for example, is a CPU 1 1. The control device, in
addition to a processor such as the CPU 5 1, may comprise a dedicated hardware circuit
for perforlning prescribed processing (for example, compression, decompression,
coding or decoding). The dedicated hardware circuit, for example, is a pality circuit 25
for computing either parity or a intermediate parity. The memory 12 stores a program
and various types of information for controlling the FMPK 50. The CPU 5 1 realizes
various types of functions in accordance with executing the program based on the information
stored in the memory 12. The buffer 26, for example, is a volatile memory,
such as a DRAM. The buffer 26 temporarily stores data to be written to the FMPK 50,
data read from the FMPK 50, and data during a parity operation. When each FMPK 50
connected to the system controller 20 has the
parity circuit 65, the systeln controller 20 does not have to comprise a parity circuit
25.
LO0211 The f~lnctionsp rovided by a prior art system controller equivalent to the system
controller 20 include a pal-ity operation, a snapshot, data compression, and duplicate
elimination, but these functions can be realized by the FMPK 50 or other such storage
medium. In tliis example, a parity operation function will be explained.
LO0221 Since the system controller 20 and the device controller 60 form a hierarchy, the
systein controller 20 call be defined as the higher-level controller, and the device
contsoller 60 can be defined as the lower-level controller.
Next, a computer system, which is an example of the applicatioil of a storage system
30 in a case where the system controller 20 is a controller suppol-ting RAID
(Redundant Array of Independent Disks) functions, will be explained.
Fig. 3 shows an example of the configuration of a colnputer system related to
Example 1. This coinputer system comprises a host coinputer 10 and a storage system
30. The host coinputer 10 and the storage system 30 are coupled via a comm~~nication
network, for example, a SAN (Storage Area Network 1. The computer system may
comprise multiple host computers 10. In this case, the storage system 30 is coupled to
the multiple host computers 10 via the SAN 1.
The storage systein 30 comprises multiple FMPKs 50, and a system controller 20 for
colltrolling these FMPKs 50. The storage apparatus, for example, is the FMPK 50. In
this example, the systein controller 20, for example, is a RAID controller. 111 addition,
in this example, the storage systein 30 comprises multiple system controllers 20. Each
system controller 20 is coupled to the host computer 10 via the SAN 1. Each of the
multiple FMPKs 50 is coupled to the multiple system controllers 20. The storage
systein 30 may colnplise only one system colltroller 20.
The configuration of the systein controller 20 is the same as the configuration shown
in Fig. 2. The memory 12 also stores a program and various types of infollnatioil for a
RAID f~inctionw, hich uses the multiple FMPKs 50. In this example, the system
colltroller 20 compiises a parity circuit 25, but need not colnprise a parity ciscuit 25.
The host coinputer 10 may be a management system.
A case where the systein controller 20 perforlns RAID 5 control will be explained
hereinbelow.
The systein controller 20 is associated with a RG (RAID Group), a LU (Logical Unit,
may also be called a logical volume), and a FMPK 50. Fig. 4 shows an example of the
configurations of the RG and LU. The systein colltroller 20 allocates a number of
FMPKs 50 to the RG, and allocates either all or part of the RG storage area to the LU.
F~~rtherinorteh,e logical volume may be a vil-tual volume in which the capacity of the
volume has been vistualized in accordance with thin provisioning technology. A
physical storage area for storing data is not allocated to the virtual volume beforehand.
A physical storage area is allocated to a relevant viltual volume in prescribed units in
accordance with a write request to the relevant vil-tual volume.
Fig. 5 shows an example of a RG management table 600. Fig. 6 shows an example of
a LU management table 700. Fig. 7 shows an example of a FMPK management table
800. The system controller 20 wlites the relationships of the RG (RAID Group), the
LU (Logical Unit), and the FMPK 50 to the RG management table 600, the LU
management table 700, and the FMPK management table 800 in the memory 12.
LO03 11 The RG management table 600 comprises a record for each RG. One RG record
shows a RG number 601, which denotes the RG, a FMPK number 602, which denotes
the FMPK 50 allocated to the RG, and a RAID level 603 of the RG.
[0032] The LU lnanageinent table 700 complises a record for each LU. One LU record
shows a LU number 701, which denotes the LU, an RG number 702, which denotes the
RG allocated to the LU, a stripe size 703, which is the size of the stripe block allocated
to the LU, a LU start address 704, which is the logical start address of this LU, a LU
size 705, which is the size of the LU, and an I 0 characteristic 706 of the LU. The I 0
characteristic 706 is a trend of an I 0 pattern carried out with respect to the LU, and
denotes which is stronger, a sequential trend or a rando~ntr end.
[0033] The I 0 characteristic 706 may be specified beforehand by a user, or may be determined
by the system controller 20. Or a combination thereof, in which the initial
value of the 10 characteristic 706 may be specified beforehand by the user, and, after
the passage of a presclibed time, the system controller 20 may optimize the initial
value in accordance with a determination. As a method for deter~niningth e 10 characteristic
706, for example, the system controller 20 may collect a command statistic for
a certain LU at each unit of time, and inay determine the higher of a random I 0 pattell1
and a sequential 10 pattern as the 10 charactelistic 706 of the relevant LU. The types
of colninands include a randoln wlite and a sequential write. The coinparison of the
percentage of random writes with the percentage of sequential writes may be done by
comnparing the fsequency of these commands. The amount of data written in accordance
with these commands inay also be compared. In addition, the system
controller 20 inay monitor the I 0 characteristic 706 on a fixed cycle in accordance
with the above-mentioned detei~ninationm ethod, and may update the LU management
table 700 in a case where a change is necessary.
100341 The FMPK management table 800 comprises a recod for each FMPK 50. One
FMPK 50 record comprises a FMPK number 801, which denotes the FMPK 50, col-sespoilding
RG nuinber 802, which denotes the RG to which the FMPK 50 belongs. and
pality operation function support information 803, which denotes the parity operation
function of this FMPK 50. The parity operation function support information 803, for
example, is a flag denoting whether or not this FMPK 50 compl-ises a parity operation
f~~nctiosnu,c h as a parity circuit 65.
[0035] Fig. 8 shows an example of an address space on a RG. Fig. 9 shows an example of an
address space on a FMPK 50 belonging to the RG. I11 this example, the system
controller 20 allocates FMPK #0 through FMPK #3, which are four FMPKs 50, to a
RAID 5 RG #0. In addition, the system co~~troll2e0r allocates successive areas from
the address space on the RG #0 to a LU #O, and allocates different successive area to a
LU #1. The systeiii controller 20 allocates a stripe line spanning the address spaces on
the FMPK #0 through the FMPK #3, and allocates stripe blocks and parity in the order
of the stripe lines and FMPK numbers. At this point, the system controller 20 shifts the
FMPK number, which allocates a stripe block and parity, for each stripe line. At this
time, the system controller 20 wlites infoimation related to the RG #0, the LU #O and
the LU #I to the RG manage~nenta ble 600, the LU management table 700, and the
FMPK inanagelnent table 800.
[0036] Fig. 10 shows an example of page inapping in a FMPK 50. A logical address space
on a FMPK 50 is partitioned into multiple logical pages. Alternatively, a physical
address space on the FMPK 50 is pal-titioned into in~~ltipplhey sical blocks, and, in
addition, each physical block comprises a prescribed block size, and is allocated to
multiple physical pages. Each logical page and each physical page compiises a
presciibed page size.
[0037] A physical block or some other physical area may be used instead of the physical
page. In addition, a logical unit or some other logical area may be used instead of the
logical page.
COO381 Fig. 11 shows an example of a page mapping management table 1100. The device
controller 60 associates a logical page with a physical page, and writes this relationship
to the page mapping management table 1 100 in the ~neinoly5 2. The page mapping
management table 1100 coinprises a record for each logical page. One logical page
record denotes a logical page number 1101, which denotes the logical page, a physical
page nuinber 1102, which denotes a current physical page, which is the physical page
cul~entlya llocated to the logical page, and an old physical page numnber 1103, which
denotes an old physical page, which is the physical page that was allocated to the
logical page previous to the current physical page. That is, the old physical page associated
with a cel-tain logical page denotes the current physical page, which had been
associated with the logical page in the previous generation. The old physical page,
which is associated with the logical page, is regarded as a valid page, and this association
is maintained until the association with the logical page is cancelled. Since an
old physical page, for which the association has been cancelled, transitions to an
invalid page, the data inside the old physical page is erased at a prescribed timing in
accordance with a reclainatioii process or the like. In a flash memory in which the
memory characteristics are such that data cannot be overw~ittent,h e reclamation
process refers to a process, which erases invalid data (data stored in an invalid page)
and sets the page in which this invalid data was stored to a wlitable state once again.
Since data is erased in block units in the tlash memory, in a case where there are both a
valid page(s) and an invalid page(s) iiiside a target block, the FM controller 1447
erases the invalid data stored in the target block after inoving the data inside the valid
page(s) to another block. In this example, the FM controller 1447 dete~lninesth at the
physical page I 102, which is associated with the logical page, and the old physical
page 1 103 are valid pages, and executes reclalnation processing.
LO0391 A specific example of a management method for an old physical page will be
explained. The device controller 60 determines whether or not an old physical page
shown in the page mapping manageinent table 1100 is no longer necessaiy, and in a
case where the deter~ninationi s that a cestain old physical page is no longer needed,
may cancel the association between this old physical page and the logical page. For
example, an upper limit for the number of old physical pages managed by the device
controller 60 is configured beforehand, and the device controller 60 deletes the old
physical pages from the page mapping management table 1100 in order from the
oldest. The device controller 60 may also delete an old physical page from the page
mapping management table 1100 in accordance with an instruction froin the system
controller 20. An example of determination criteria is detelminatioll as to whether
parity update resulting from data update has been accomplished or not.
In addition, the system controller 20 may determine whether or not the data of the old
physical page is needed, and in a case where the determination is that the old physical
page is not needed, inay instruct the device controller 60 corsesponding to the old
physical page to delete the old physical page from the page mapping management table
1100. Either the system controller 20 or the device controller 60 may delete an old
physical page from the page inapping mallagemeilt table 1100 in a case where the used
capacity of the FM 55 has become equal to or larger than a fixed value. In a case where
a request to read data from an old physical page has been issued, and, in addition, the
old physical page remains in the page napping management table 1100, the device
controller 60 can read the data from the old physical page.
[0040] Next, the operation of the system controller 20 will be explained.
LO041 J Fisst, a write method at data update time will be explained.
(00421 The write methods, for example, are a read-modify-write and a full-stripe write. The
read-modify-write of this example is a process for updating the data of one stripe block
specified within a single stl-ipe line. Alternatively, the full-stripe write of this example
is a process for updating all the data in a single stripe line. The read-modify-write
coinputes a intermediate parity fi-om old data in a specified stripe block and new data,
and computes a new parity from the intermediate parity and an old parity. The f~lllstlipe
write computes a new parity based on all new data. As used here, old data refers
to pre-update data, new data refers to post-update data, old parity refers to a pre-update
parity, and new parity refers to a post-update parity. A intermediate paiity is parity part
way through a parity operation, and denotes the difference between an old parity and a
new parity.
Next, a parity operation function will be explained.
The parity operation function, for example, is the parity circuit 25 and the parity
circuit 65, and computes an exclusive OR between the data of two stripe blocks in a
single stripe line. The parity operation function also computes an exclusive OR
between old data and new data as a intellnediate parity. In addition, the pality
operation function computes an exclusive OR between an old parity and a intermediate
parity as a new parity. Supposing that old data is Di, new data is Di-new, and an old
parity is P, a new parity P-new is expressed using the following equation.
P-new = P + (Di + Di-new)
The operator "+" here represents the exclusive OR, and (Di + DI-new) represents the
intermediate parity. The intermediate parity is equivalent to an exclusive OR between
all data other than the Di.
Another redundancy code, such as a Hamming code, may be used instead of parity.
Next, a pality operation function registration process for the systein controller 20 to
register parity operation function support information 803 in the FMPK management
table 800 will be explained.
Fig. 12 shows an example of a parity operation function registration process. The
system controller 20 pel-forms a parity operation function registration process when a
new FMPK 50 is installed, and at system controller 20 ramp up.
Fixst, the systein controller 20 issues a parity operation function support confirmation
comnand to the FMPK 50 device controller 60, and receives a response thereto
( 1201). The device controller 60, which receives the parity operation f~~nctiosunp port
confirination command at this time, sends a response to the systein controller 20
denoting whether or not the device contmller 60 itself comprises a pality operation
function. Next, the system controller 20, based on the response, registers the information
demoting whether or not the device controller 60 comprises a parity
operation function in the parity operation function suppost information 803 of the
FMPK management table 800 (1202), and ends this flow of processing.
The user may register the parity operation f~~nctiosunp port information 803 beforehand
instead of carrying out a parity operation function registration process.
Next, a method for deciding a parity operation iinplementation apparatus for
pelforming a parity operation will be explained.
Fig. 13 shows an example of a parity operation implementation apparatus decision
method 1300. The system controller 20 determines either the system controller 20 or
the device controller 60 as the parity operation implementation apparatus in accordance
with the decision method 1300. The system controller 20 detel~ninese ither
the system controller 20 or the device controller 60 as the parity operation implementation
apparatus based 011 information, which denotes whether or not the system
controller 20 comprises a parity operation function, such as the parity circuit 25, and
the parity operation f~lnctions upport information 803 of the FMPK management table
800. Four cases for deciding the parity operation implementation apparatus are
defined. Each case shows a case number 1301, system function infollnation 1302,
which denotes whether or not the systein controller 20 comprises a parity operation
function, device function infosinatioil 1303, which denotes whether or not the device
controller 60 comprises a parity operation function, pa~ityo peration implementation
infoilnation 1304, which denotes the parity operation implementation apparatus, and
an option 1305.
[0054] Case #I is a case where the system controller 20 comprises a parity operation
function, and, in addition, the device controller 60 also comprises a parity operation
function. According to the parity operation implementation information 1304, in this
case, the systeln controller 20 can select either the system controller 20 or the device
controller 60 as the parity operation iinplementation apparatus. 111 this case, the system
contsoller 20 pe~foimsa write process, which will be explained further below, based
on the option 1305.
[0055] Case #2 is a case where the system controller 20 colnplises a parity operation
function, but the device controller 60 does not comprise a parity operation function.
According to the parity operation implementation information 1304, in this case, the
system controller 20 selects the systein controller 20 as the parity operation implementation
apparatus.
COO561 Case #3 is a case where the system controller 20 does not comprise a parity operation
f~lnctionb, ut the device controller 60 does complise a pality operation function.
According to the pality operation implementation information 1304, in this case, the
system controller 20 selects the device controller 60 as the parity operation implementation
apparatus.
100571 Case #4 is a case where the system controller 20 does not comprise a parity operation
f~lnctiona, nd, in addition, the device controller 60 does not comprise a parity operation
f~lnctionA. ccording to the parity operation implementation information 1304, in this
case, the systein controller 20 is unable to select either the system controller 20 or the
device controller 60 as the parity operation implementation apparatus.
100581 The parity operation f~lnctionr egistration process and the parity operation implementation
apparatus decision may be omitted. For example, in a case where the system
controller 20 and all the device controllers 60 comprise parity operation functions, the
systein controller 20 may omit the pality operation function registration process and
the parity operation implementation apparatus decision, and peifonn the write process
in case #1, which will be explained hereinbelow. These processes can also be omitted
in a case where the parity operation impleinentation apparatus has been installed beforehand
by an admillistrator or the like.
roo591 Next, the write process of the system controller 20 in cases #I to #3 will be
explained.
LO0601 Fig. 14 shows an example of a write process of the system controller 20. First, the
system controller 20 receives a write request as an 10 request fmin an external host
(1401). The external host, for example, is a host computer 10 coupled to the systeln
controller 20 via the SAN 1. Next, the system controller 20 pel-folms a parity operation
selection process for selecting one of the system controller 20 or the device controller
60 as the parity operation ilnplemelltatioll apparatus for performillg a parity operation
(1402). In the cases #2 and #3, since the parity operation implementation apparahls is
alseady selected, the process in Step 1402 is omitted. Next, the system contmller 20
perfolms a write method selection process for selecting the write method based on the
received command (1403). The wlite method is one of either the read-modify-write or
the full-stripe write. Next, the system controller 20 pelfolms a data update process for
updating, data and parity in the device controller 60 ill accordance with the selected
write method (1404).
[0061] Next, a number of specific examples of the parity operation selection process 1402
will be explained.
LO0621 First, a first parity operation selection process, which is a specific example of a
process in which the system colltroller 20 selects a parity operation implementation
apparatus based on the I 0 characteristic 706 of each LU, will be explained.
[0063] Fig. 15 shows an example of a first parity operation selection process. First, the
systeln controller 20 determines whether or not the 10 characteristic 706 of the LU
targeted for the relevant write is random based on the LU manageinent table 700
(1501). In a case where the relevant LU 10 characteristic 706 denotes raildoln (1501:
Yes), the system controller 20, in accordance with selecting the device controller 60 as
the parity operation implemeiltatio~la pparatus, decides to iilstruct the device controller
60 to perfonn a parity operatio11 (1502), and ends this flow of processing. Alternatively,
in a case where the relevant LU I 0 characteristic 706 does not show randoin
(1501: No), more specifically, in the case of sequential write to be described later, the
system controller 20, in accordance with selecting the system controller 20 as the
pal-ity operation implementation apparatus, decides that the system contluller 20 will
iinpleinent the parity operation (1503), and ends this flow of processing.
[0064] That is, 011 the occasion of an 10, the system controller 20 references the 10 characteristic
706 of the LU lnailagelnent table 700, and in a case where the 10 characteristic
706 shows that the number of random writes is greater than the number of sequential
writes with respect to writes to the relevant LU, instructs the device controller 60 to
create parity. Altenlatively, in a case where the I 0 characteristic 706 shows that
randoin wiites are fewer than sequential wlites with respect to writes to the relevant
LU, the systein controller 20 iinple~nentsp arity creation.
100651 Next, a second parity operation selection process, which is a specific exainple of a
process in which the systein colltroller 20 detects the hardware load of the systein
colltroller 20 and selects the parity operation implementatioll apparatus based on this
load, will be explained.
LO0661 Fig. 16 shows a11 example of a second parity operation selection process. The
hardware, for example, is the CPU 1 1, the memory 12. and the parity circuit 25. First,
the system controller 20 determines whether or not its own hardware load is higher
than a reference (1601). In a case where the determination is that the hardware load is
higher than a reference (1 601 : Yes), the systein controller 20 selects the device
controller 60 as the parity operation iinplementation apparatus, i~lstructst he device
controller 60 to perform a parity operation (1602) and ends the flow of processing. Alternatively,
in a case where it is determined that the hardware load is not higher than a
reference (1601: No), the system controller 20 selects the system controller 20 as the
parity operation implementation apparatus (1603), and ends the flow of processing.
[0067] The system controller 20, for example, measures the load on the system controller 20
hardware here, and in a case where the measureinent result exceeds a presclibed
threshold, determines that the hardware load is high. The measurement results, for
example, are the CPU 11 utilization rate, the amount of memory 12 used, and the
ainount of data inputted to the parity cil-cuit 25.
LO0681 Next, a third parity operation selection process, which is a specific example of a
process in which the system colltroller 20 selects the parity operatioil implemelltatioll
apparatus based on the 10 pattern of the relevant wiite, will be explained.
[0069] Fig. 17 shows an example of a third parity operatioil selectio~pl rocess. First, the
systein controller 20 determines whether or not the I 0 pattern of the relevant 10
request is a random write (1701). In a case where it is deteriniiled that the 10 pattern is
a raildoln write (1701: Yes), the systein colltroller 20 selects the device controller 60 as
the parity operation iinplementation apparatus, instructs the device controller 60 to
pel-form a pality operation (1702), and ends this flow of processing. Alternatively, in a
case where it is determined that the I 0 pattern is not a random write, that is, in a case
where it has been determined that the 10 pattern is a sequential write (1701: No), the
system controller 20 selects the system controller 20 as the parity operatio11 implementation
apparatus (1703), and ends the flow of processing.
[0070] Next, a fourth parity operation selection process, which is a specific example of a
process in which the system controller 20 selects the parity operation implementation
apparatus based on the I 0 patteln of the relevant write and the hardware load of the
systein controller 20, will be explained.
[0071] Fig. 18 shows an example of a fourth parity operation selection process. First, the
system controller 20 determines whether or not the TO pattern of the relevant write is a
randoin wiite (1801). In a case where it is deterinined that the I 0 pattern is a randoln
write (1801: Yes), the system controller 20 selects the device controller 60 as the parity
operation ilnplelnentation apparahls, inst~uctsth e device controller 60 to perform a
parity operation (1802), and ends the flow of processing. Alternatively, in a case where
it is deteimiiled that the 10 pattein is not a randoin write (1801: No), the system
controller 20 determines whether or not the hardware load is high (1803). In a case
where it is deterinined that the hardware load is high (1803: Yes), the system controller
20 inoves the flow of processing to 1802. Alternatively, in a case where it is determined
that the hardware load in not high (1 803: No), the systein controller 20
selects the systein controller 20 as the parity operation ilnplelnentation apparatus
(1804), and ends the flow of processing.
[0072] The system controller 20 may also select a parity operation iinplementatioi~ apparatus
in accordance with combining the multiple types of parity operation selection
processes 1402 described hereinabove.
[0073] In accordance with the system controller 20 pei-forining a paiity operation at the time
of a sequential write and a full-stripe wlite, it is possible to prevent an increase in the
amount of data transferred from the system controller 20 to the device controller 60.
This makes it possible to prevent a drop in write speed.
100741 Next, a specific example of a write method selection process 1403 will be explained.
[0075] Fig. 19 shows an example of a write method selection process 1403. The write
inethod choices, for example, are read-modify-write and ftill-stripe write. First, the
system controller 20 determines whether or not the 10 pattern of a write, which is the
relevailt 10 request, is a random write (1901). In a case where it is deteilnilled that the
I 0 pattern is a random write (1901: Yes), the systein controller 20 selects a readmodify-
write as the write method (1902), and ends the -flow of processing. Alternatively,
in a case where it is determined that the I 0 pattern is not a random wiite
(1901: No), that is, a case where it is determined that the 10 pattern is a sequential
write, the system controller 20 selects the fill-sttipe wiite as the write method (1903),
and ends the flow of processing.
100761 Next, a number of specific exainples of a data update process 1404, which corresponds
to the selection result of the parity operation implementation apparatus and
the selection result of the wiite method. will be explained.
LO0771 First, a first read-modify-write process, which is a specific example of the data
update process 1404 in a case where the device controller 60 has been selected as the
parity operation ilnpleinelltation apparatus and the read-modify-write has been selected
as the write method, will be explained.
[0078] Fig. 20 shows an example of the first read-modify-write process. Fig. 21 shows an
example of the operation of the system controller 20 in the first read-modify-write
process. In this example, four FMPKs 50, i.e., FMPKs #0, #I, #2, and #3, respectively
store the data DO, Dl, D2 and a parity P in one stripe line. It is supposed here that an
initial state is a state in which the system controller 20 has received new data for
updating the old data of DO in accordance with a write command. In the followillg explanation.
of the FMPKs #O, #1, #2, and #3, the FMPK #O, which stores the data to be
updated, may be called the data FMPK. I11 addition, of the FMPKs #0, #1, #2, and #3,
the FMPK #3, which stores parity, may be called the parity FMPK.
COO791 First, the system controller 20 selects the FMPK #O (the data FMPK) corresponding
to the DO from among the FMPKs #0, #1, #2 and #3, and transfers new data to the
FMPK #O in accordance with issuing the FMPK #O an old-data-store write command,
which instr~ictsth at the old data be stored and the new data be written (2101). The
device controller 60 of the FMPK #0, which receives this conmand, writes the new
data from the system controller 20 to a different physical page from the physical page
of the old data in the FMPK #O. With a normal write command, the old physical page
becomes illvalid when a new physical page is allocated to the logical page, and the old
data stored in the old physical page becomes the target of an erase. Consequently, the
system col~trolle2r 0 uses an old-data-store write command instead of a normal write
command to make sure the old data is retained until the parity update is complete. In
subsequent explanation, the write command means a normal write command.
[0080] Next, the system controller 20 acquires a intermediate parity from the FMPK #0 in
accordance with issuing the FMPK #0 a inteiinediate parity read command requesting
the inteimediate parity (2102). The mid-operation pality is a intermediate operation
result for prod~icinga new parity in accordance with a parity operation on the old
parity. The device controller 60 of the FMPK #O, which receives this command,
computes the intelinediate parity based on the old data stored in the FMPK #0 and the
new data stored ill the FMPK #0, and sends the intermediate parity to the system
controller 20 as a response. The FMPK #0 device controller 60 may write the
computed intermediate parity to the buffer 66 here, or may write the computed intermediate
parity to a different physical page from either the old data physical page or
the llew data physical page in the FM 55 of the FMPK #O.
[0081] Next, the system controller 20 selects the FMPK #3 (the paiity FMPK), which corresponds
to the P from among the FMPKs #O, #1, #2 and #3, and transfers the intermediate
pality received from the FMPK #0 to the FMPK #3 in accordance with
issuing the FMPK #3 a parity-update write command instmcting that parity be updated
(2103). Thc FMPK #3, which receives this command, computes a new parity based on
the old parity in the FMPK #3 and the intermediate parity from the system controller
20, and writes the new pality to the FMPK #3. The FMPK #3 device controller 60
writes the new parity to the FMPK #3 and notifies the systeln controller 20 of the
completion response for the parity update write. At this point, the FMPK #3 device
controller 60 may write the intermediate parity from the systeln controller 20 to the
buffer 66, or may write the inte~lnediatep arity to a physical page. which differs from
both the old parity physical page and the new parity physical page in the FM 55 inside
the FMPK #3.
[0082] Next, the system controller 20, upon receiving a completioll response from the
FMPK #3, issues the FMPK #O a unmap-old-data command inst~~ictinthga t the old
data be invalidated (2104), and ends this flow. The device controller 60 of the FMPK
#0, which receives this command, deletes the physical page mapped to the logical page
identified by the unmap-old-data command from the mapping management table 1100
in order to invalidate the stored old data.
[0083] Ful-thermore, the system controller 20, in a case where the colnpletioll response has
not been received fmm the FMPK #3 within a prescribed period of time subsequent to
the issuing of the parity update write command, may detelrnine that the parity update
has failed, re-acquire the intermediate parity from the FMPK #0, and re-execute the
pality update process by re-transfell-ing this inteilnediate parity to the FMPK #3.
[0084] Specifically, the system controller 20, in a case where the completioi~r esponse has
not been received from the FMPK #3 within a prescribed period of time following the
issuing of the parity update w~itec ommand, re-issues the intellnediate parity read
command to the FMPK #0, and receives the intermediate parity re-computed in accordance
with this command. Then, the systein controller 20 writes the re-computed
intermediate pality to the FMPK #3 in accordance with re-issuing the pality update
write colmnand to the FMPK #3.
[0085] According to this processing, the transfer of data between the system controller 20
and the device controller 60 in the ~lpdatingo f data in a single stripe block is as
follows.
[0086] (1) Post-update data is transferred from the systeln controller 20 to the device
colltroller 60 of the data FMPK.
(2) Interlnediate parity is transferred from the device controller 60 of the data FMPK
to the system controller 20.
(3) Intermediate parity is transfei~edfr om the system controller 20 to the device
controller 60 of the parity FMPK.
[0087] This makes it possible to hold down on the transfer of data between the systein
controller 20 and the device controller 60. Alternatively, in a case where the system
controller 20 pesforins the pahty operation here, the transfer of data between the
system controller 20 and the device controller 60 is as follows.
(1) Pre-update data is transferred from the device controller 60 of the data FMPK to
the system controller 20.
(2) Pre-update parity is transfel~edfr om the device controller 60 of the parity FMPK
to the systeln controller 20.
(3) Post-update data is transferred from the system controller 20 to the device
controller 60 of the data FMPK.
(4) Post-update parity is transfessed fi-oin the system controller 20 to the device
contsolles 60 of the parity FMPK.
Less data is transfei~edin the first read-modify-wlite process than in a case where the
system controller 20 pelforms this kind of parity operation.
Also, the buffer 66, which the data FMPK device controller 60 used to peifoirn an
operation on the mid-operation parity can be pared down in accordance with the data
FMPK storing both the pre-update data and the post-update data in the FM 55.
In addition, storing the old data until parity is updated even after new data has been
written also makes data restoration possible in a case where a failure has occurred prior
to parity being updated. Furtheirnose, making the old data invalid and targeting the old
data for an erase subsequent to parity being updated makes it possible to reduce the
amount of storage area being used by old data.
Next, a second read-modify-write process, which is another specific example of a
different data update process 1404 in a case where the device controller 60 has been
selected as the parity operation implementation apparatus and read-modify-write has
been selected as the write method, will be explained.
Fig. 22 shows an example of the second read-modify-write process. Fig. 23 shows an
example of the operation of the system controller 20 in the second read-modify-write
process. The initial state in this example is the same as the initial state of the first readmodify-
write process. First, the system controller 20 acquires the old data from the
FMPK #0 in accordance with issuing a read command to the FMPK #0 corresponding
to the DO (the data FMPK) (2301). The device controller 60 of the FMPK #0, which
receives this command, reads the old data in the FMPK #0 and sends the old data to the
system controller 20 as a response.
Next, the system controller 20 transfers the old data and new data to the FMPK #3 in
accordance with issuing a parity-update write cormnand to the FMPK #3 comesponding
to the P (the parity FMPK) (2302). The device controller 60 of the FMPK #3,
which receives this command. computes a new parity based on the new data from the
systeln controller 20, the old data from the systeln controller 20, and the old parity in
the FMPK #3, and writes the new pal-ity to the FMPK #3.
Next, the systeln controller 20 transfers the new data to the FMPK #0 in accordance
with issuing a write command to the FMPK #O (2303). The device controller 60 of the
FMPK #0, which receives this command, writes the new data to the FMPK #O.
According to this processing, the transfer of data between the system controller 20
and the device controller 60 in the updating of data in a single stripe block is as
follows.
(1) Pre-update data is transferred to the system controller 20 from the data FMPK
device controller 60, and post-update data is transferred from the systein controller 20
to the data the device controller 60 of the data FMPK.
(2) Pre-update data and post-update data are transferred from the systein controller
20 to the parity FMPK device controller 60.
This makes it possible to hold down on the transfer of data between the system
controller 20 and the device controller 60.
In 2302, the system controller 20 transfers new data and old data to the parity FMPK
using a single parity-update write command. The ainount of transfer data at this time is
two times the ainount of data transfeil-ed in the case of the first read-modify-wiite
process when the intermediate parity is transferred to the pasity FMPK from the system
controller 20. However, since there is only one transfer, it is possible to prevent an
increase in the data transfer overhead. In a case where the data transfer is performed in
accordance with a high-speed inte~facesu ch as a 6GB SAS (Serial Attached Small
Computer Interface), the merit of the small number of transfers outweighs the demerit
of the increase in the amount of data transfem~ed.
In addition, storing the old data until pakty is updated even after new data has been
written also makes data restoration possible in a case where a failure has occurred prior
to parity being updated. Furtheimore, making the old data invalid and targeting the old
data fos an erase subsequent to parity being updated makes it possible to reduce the
amount of storage area being used by old data.
In a case where the device controller 60 has been selected as the parity operation implementation
apparatus, and the read-modify-write has been selected as the write
method, either the first read-modify-write process or the second read-modify-write
process may be performed.
Next, a third read-modify-wiite process, which is a specific example of the data
update process 1404 in a case where the systein controller 20 has been selected as the
parity operation iinplelnentation appamtus and read-modify-write has been selected as
the write method, will be explained.
Fig. 24 shows an example of the third read-modify-write process. Fig. 25 shows an
exa~npleo f the operation of the system controller 20 in the third read-modify-wlite
process. The initial state in this example is the same as the initial state of the first readmodify-
write process. First, the systein controller 20 acquires old data from the FMPK
#0 in accordance with issuing a read command requesting the DO to the FMPK #O corresponding
to the DO, and acquires old parity from the FMPK #3 in accordance with
issuing a read command to the FMPK #3 corresponding to the P (2501). The FMPK
#0, which receives this read command, reads the old data of the FMPK #O, and sends
this old data to the systeln controller 20 as a response. Also, the device controller 60 of
the FMPK #3, which receives this read command. reads the old parity of the FMPK #3
and sends this old parity to the system controller 20 as a response.
[0104] Next, the system controller 20 computes a new pasity based 011 the old data, the old
parity, and the new data (2502). Next, the system controller 20 sends the new data to
the FMPK #0 in accordance with issuing a write command to the FMPK #O, sends the
new parity to the FMPK #3 in accordance with issuing a write command to the FMPK
#3 corresponding to the P (2503), and ends this flow of processing. The device
controller 60 of the FMPK #0, which receives this wlite command, wiites the new data
to the FMPK #O. In addition, the FMPK #3, which receives this wlite command, wlites
the new parity to the FMPK #3.
[0105] According to this processing, the transfer of data between the system coi~trolle2r 0
and the device controller 60 in the updating of the data in a single stripe block is as
follows.
[0106] (1) Pre-update data is transferred from the device controller 60 of the data FMPK to
the system controller 20 and post-updata data is transferred from the system controllel-
20 to the device controller 60 of the data FMPK.
(2) Pre-update parity is transferred from the device controller 60 of the parity FMPK
to the systeln controller 20.
(3) Post-update parity is transferred from the system controller 20 to the device
controller 60 of the parity FMPK.
[0107] This makes it possible to hold down on the transfer of data between the system
controller 20 and the device controller 60.
[0108] Next, a number of specific examples of a full-stripe write will be explained.
r01091 First, a first full-stripe write process, which is a specific example of another data
update process 1404 in a case where the device controller 60 has been selected as the
parity operation implementation apparatus and fill-stripe write has been selected as the
write method.
LO1 101 Fig. 26 shows an example of the first full-stripe write process. Fig. 27 shows an
example of the operation of the system controller 20 in the first full-stripe write
process. In this example, the FMPKs #0, #1, #2, and #3 respectively store DO, Dl, D2
and P. It is supposed here that the initial state is a state in which the system controller
20 has received new data for updating the old data of DO. Dl, and D2 in accordance
with a write command. In the following explanation, of the FMPKs #0, #1, #2 and #3,
the FMPKs #0, #I and #2, which are storillg the data to be updated, may be called the
data FMPK.
[OI 111 First, the systeln controller 20 partitions the received data into new data for DO, Dl,
and 0 2a nd respecti~~eltrya nsfers the new data of DO, Dl, and D2 to the FMPKs #O,
#1, and #2 in accordance with issuing a write command to the FMPKs #O, #1 and #2
(the data FMPKs) respectively corresponding to the DO, the Dl, and the D2 (2701).
The device controllers 60 of the FMPKs #0, #I, and #2, which receive this write
cormnand, respectively write the new data from the systeln controller 20 to the FMPKS
#0, #1 and #2.
[0112] Next, the system controller 20 transfers the new data of the DO, the Dl, and the D2 to
the FMPK #3 in accordance with issuing the FMPK #3 corresponding to the P (the
parity FMPK) a parity-create write coininand instructing the creation and writing of a
pality (2702), and ends the flow of processing. The device controller 60 of the FMPK
#3, which receives this write command, computes a new parity based on the new data
of the DO, the Dl, and the D2, and writes this new parity to the FMPK #3.
101 131 According to this processing, the transfer of data between the system controller 20
and the device controllers 60 in the updating of data in a single stlipe line is as follows.
[0114] (1) Post-update data is transfersed from the system controller 20 to the data FMPK
device controllers 60.
(2) Post-update parity data is transfened from the system controller 20 to the parity
FMPK device controller 60.
101 151 This makes it possible to hold down on the transfer of data between the system
controller 20 and the device controller 60.
[0116] Next, a second f~ill-stripew rite process, which is a specific example of another data
update process 1404 in a case where the system controller 20 has been selected as the
pality operation implementation apparatus and the full-stripe write has been selected as
the write process, will be explained.
101 171 Fig. 28 shows an exainple of the second full-stiipe write process. Fig. 29 shows an
example of the operatioil of the system controller 20 in the second full-stripe write
process. The initial state in this example is the same as the initial state of the first fullstripe
wiite process. First, the systeln controller 20 computes a new parity from the
new data of the DO, the Dl. and the D2 (2901). Next, the systeln controller 20 respectively
transfers the new data of the DO, the Dl, and the D2 to the FMPKs #0, #1,
and #2 in accordance with issuing a write coinmand to the FMPKs #0, #1, and #2 correspollding
to the DO, the Dl, and the D2, transfers the computed new parity to the
FMPK #3 in accordance with issuing a write command to the FMPK #3 corresponding
to the P (2902), and ends this flow of processing. The device contlr~llers6 0 of the
FMPKs #0, #I, and #2, which receive this write command, respectively write the new
data fmm the system controller 20 to the FMPKS #O, #1 and #2. In addition, the device
controller 60 of the FMPK #3, which receives the write command, writes the new
parity from the system controller 20 to the FMPK #3.
According to this processing, the transfer of data between the system controller 20
and the device controllers 60 in the updating of the data in a single stripe line is as
follows.
(1) Post-update data is transferred from the system controller 20 to the data FMPK
device controllers 60.
(2) Post-update parity is transferred from the system controller 20 to the parity
FMPK device controller 60.
This makes it possible to hold down on the transfer of data between the system
controller 20 and the device controller 60.
Next, a nuinber of specific exainples of a data restoration process in accordance with
the parity operation implementation apparatus selection result will be explained.
First, a first data restoration process, which is a specific example of a data restoration
process in a case where the device controller 60 has been selected as the pruity
operation implementation apparatus, will be explained.
Fig. 30 shows an example of the first data restoration process. Fig. 3 1 shows an
example of the operation of the system contmller 20 in the first data restoration
process. 111 this example, the FMPKs #0, #I, #2, and #3 respectively store the DO, the
Dl, the D2, and the P. It is supposed here that the initial state is a state in which a
failure has occurred in the FM 55 inside the FMPK #I, and this FM 55 has been
replaced with a new FM 55. In the following explanation, of the FMPKS #0, #1, #2,
and #3, the FMPK #1, which is storing the data to be restored, may be called the
restoration-in-progl-ess FMPK.
Fhst, the system controller 20 acquires the DO, the D2, and the P respectively stored
in the FMPKs #0, #2, and #3 in accordance with issuing a read colnlnand to the
FMPKs #0, #2 and #3, which exist in the RG to which the FMPKs #0, #1, #2, and #3
belong (3101). The device controllers 60 of the FMPKs #0, #2, and #3, which receives
this read command, respectively read the DO, the D2, and the P, and transfer the read
DO, D2, and P to the system controller 20. Data and parity may be read here.
Next, the system controller 20 transfers the DO, the D2, and the P, which have been
read, to the FMPK #I in accordance with issuing a write command denoting the
creation of parity to the FMPK #I, which is being restored (the restoration-in-progress
FMPK) (3102), and ends this flow of processing. The device controller 60 of the
FMPK #1, which receives this write command, creates Dl restored data in accordance
with computing the Dl based on the DO, the D2, and the P, and writes the Dl restored
data to the FMPK #l.
According to this processing, the transfer of data between the system colltroller 20
and the device controller 60 in the restoration of data in a single stripe block is as
follows.
(1) Data of a FMPK 50 other than the restoration-in-progress FMPK is transferred
from the corresponding device controller 60 to the system controller 20.
(2) Transferred data is transferred from the systein controller 20 to the restorationin-
progress FMPK device controller 60.
This inakes it possible to hold down on the transfer of data between the systein
controller 20 and the device controller 60.
Next, a second data restoration process, which is a specific example of a data
restoration process in a case where the system controller 20 has been selected as the
parity operation implementation apparatus, will be explained.
Fig. 32 shows an example of the second data restoratioil process. Fig. 33 shows an
example of the operation of the system controller 20 in the second data restoratioil
process. The initial state in this example is the same as that of the first specific
example. First, the system controller 20 reads the DO, the D2, and the P from the
FMPKs #0, #2, and #3 in accordance with issuing a read coinmand to the FMPKs #O,
#2 and #3, which exist in the RG to which the FMPKs #0, #1, #2, and #3 belong
(3301). The device controllers 60 of the FMPKs #0, #2, and #3, which receive this read
command, respectively read the DO, the D2, and the P, and transfer the read DO, D2,
and P to the systeln controller 20. Data and parity may be read here.
Next, the systein controller 20 creates Dl restored data in accordance with computing
the Dl based on the DO, the D2, and the P (3302). Next, the systeln controller 20
writes the restored Dl to the FMPK #1 in accordance with issuing a write coinlnand to
the FMPK #1 (3303), and ends this flow of processing. The device controller 60 of the
FMPK #1, which receives this write command, writes the received D 1 to the FMPK
#I.
According to this processing, the transfer of data between the system controller 20
and the device controller 60 in the restoration of data in a single stripe block is as
follows.
(1) Data of a FMPK 50 other than the restoration-in-progsess FMPK is transferred
from the corresponding device controller 60 to the systein controller 20.
(2) The transferred data is transfen-ed fsom the system controller 20 to the
restoration-in-progsess FMPK device controller 60.
This inakes it possible to hold down on the transfer of data between the system
controller 20 and the device controller 60.
Next, the operation of the device controller 60 will be explained.
First, a normal write process, which is a specific example of a process of the device
controller 60 in a case where a normal wi-ite command has been received, will be
explained.
In this normal write process, the device controller 60 does not need to store old data.
Fig. 34 shows an example of a norinal write process. First, the device controller 60
receives a norinal write command (3401). Next, the device controller 60 determines a
logical page number from the logical address specified in this write command, and
makes the logical page of this logical page nulnber the write-destination logical page
(3402). Next, the device controller 60 acquires a new free page, and allocates the
acquired physical page as a write-destination physical page (3403). Next, the device
controller 60 wiites write-data received in accordance with the write command to the
write-destination physical page (3404).
Next, the device coiltroller 60 associates the wlite-destination physical page with the
write-destination logical page in the page mapping management table 1100, and
registers the number of the write-destination physical page as the physical page
number (3405). Next, the device controller 60 sends a response denoting the command
has been completed to the system controller 20 (3406), and ends this flow of
processing.
In 3403, the device controller 60 may acquire a free physical page by perforlning
processing, such as secul-ing an unused physical page, and erasing a physical block and
securing a physical page inside this physical block. In order to erase the physical block
at this time, the device controller 60 may cancel the association of an old physical page
with another logical page in the page mapping management table 1100.
Next, an old-data-store write command process, which is a specific example of a
process of the device controller 60 in a case where an old-data-store write coininand
has been received, will be explained.
This old-data-store write process, for example, is used in the fisst read-modify-write
process described hereinabove.
Fig. 35 shows an example of the old-data-store write plucess. First, the device
controller 60 receives an old-data-store wlite command (3501). Next, the device
controller 60 detelmines a logical page nulnber on the basis of the logical address
specified in this write command, and treats the logical page of this logical page number
as the write-destination logical page (3502). Next, the device controller 60 determines
whether or not a physical page is allocated to the write-destination logical page by referencing
the page mapping management table 1100 (3503).
In a case where a physical page is allocated to the write-destination logical page
(3503: Yes). the device contn)ller 60 registers the physical page number associated
with the write-destination logical page as the old physical page number in the page
inapping management table 1 100 (3504).
In a case where a physical page is not allocated to the write-destination logical page
(3503: No), or after 3504, the device controller 60 acquires a new free page and
allocates the acquired physical page as a write-destination physical page (3505). Next,
the device controller 60 writes write-data received in accordance with the write
comlnalld to the write-destination physical page (3506).
[0146] Next, the device controller 60 associates the write-destination physical page with the
write-destination logical page in the page mapping management table 1 100, and
registers the number of the wl-ite-destination physical page as the physical page
nuinber (3507). Next, the device controller 60 sends a response denoting that the
co~mnalldh as been colnpleted to the systeln controller 20 (3508), and ends this flow of
processing.
101471 According to this processing, the data FMPK is able to store pre-update data at the
time of a data update. In addition, the data FMPK device controller 60 is able to
associate an updated logical page, an old physical page for storing old data, and a
physical page for storing new data. This makes it possible for the data FMPK to store
both pre-update data and post-update data in nonvolatile memory at data update time.
The data FMPK device controller 60 is also able to read both the pre-update data and
the post-update data without using volatile memory. I11 addition, the system controller
20 is able to let the data FMPK device controller 60 store both the pre-update data and
the post-update data.
LO1481 Next, a intermediate parity process, which is a specific example of a process of the
device controller 60 in a case where a inteilnediate parity command has been received,
will be explained.
[0149] This intermediate parity process creates and returns a intermediate parity in accordance
with peif01ming a parity operation on the old data of the specified address
and new data. This intermediate parity process, for example, is used in the first readmodify-
write process described hereinabove.
[0150] Fig. 36 shows an example of the intermediate parity process. First, the device
controller 60 receives a intermediate parity command (3601). Next, the device
controller 60 deteilnines a logical page number on the basis of the logical address
specified by this read command, and treats the logical page of this logical page nuinber
as the read-destination logical page (3602). Next, the device controller 60 determines
whether or not an old physical page corresponding to the read-destination logical page
is registered by referencing the page mapping management table 1100 (3603).
101 5 11 In a case where at1 old physical page corresponding to the read-destination logical
page is registered (3603: Yes), the device controller 60 reads data of the old physical
page corresponding to the read-destination logical page, and data of the cussent
physical page, and computes the inteilnediate parity fsom the read data (3604). Next,
the device controller 60 transfers the intermediate parity to the systeln controller 20
(3606) and ends this flow of processing.
101521 I11 3603, in a case where an old physical page corresponding to the read-destination
logical page is not registered (3603: No), the device controller 60 repoi-ts to the system
controller 20 with a colnmand result denoting that there is no old data in the readdestination
logical page (3605), and ends this flow of processing.
[0153] The system controller 20, which receives the result in 3605 denoting that there is no
old data in the read-destination logical page, for example, may read all the data in the
same stripe line as the new data, compute a new parity on the basis of the read data,
and issue a write command for writing the new parity to the device controller 60 corresponding
to the parity. Or, in accordance with this, the systeln controller 20, for
example, may read all the data in the same stripe line as the new data, and issue a
parity-create write command for computing a new parity on the basis of the read data
to the device controller 60 coi-responding to the parity.
[0154] According to this processing, the data FMPK device controller 60, upon receiving an
instruction for a inteimediate parity operation from the system controller 20, can read
pre-update data and post-update data and create a intermediate parity based on the read
data. In addition, the system controller 20 can let the data FMPK device controller 60
create the intermediate pality, and can acquire the intermediate parity from the device
controller 60.
[0155] Hypothetically, it is supposed that the data FMPK device controller 60 has created a
intermediate parity asynchronously with the operation of the system controller 20. In
this case, the pei-foimance of this device controller 60 drops as a result of the operation
of the intelinediate parity putting a burden on the buffer 66 of the device controller 60.
Tn a case where the power shuts off in a state in which the data required in the intermediate
paiity operation is stored in the buffer 66, this data could be lost and data
restoration could become impossible. Alternatively, according to this example, a drop
in performance in the storage systeln 30 can be prevented by the data FMPK device
controller 60 creating a inteimediate parity upon receiving the intermediate paiity read
command. It is also possible to prevent the loss of data required in the inteiinediate
parity operation, and to enhance the reliability of the storage systeln 30.
101561 Next, a parity-update write process, which is a specific exainple of a process of the
device controller 60 in a case where a pal-ity-update write cornnand has been received,
will be explained.
[0157] This parity-update write process creates a new parity and wiites this new parity to the
FM 55 in accordance with perfolining a parity operation on a transferred intermediate
paiity and a specified old parity. This parity-update write coininand, for example, is
used in the first read-modify-write process described hereinabove.
LO1581 Fig. 37 shows an exainple of the pahty-update write process. First, the device
controller 60 receives a parity-update wiite coininand (3701). Next, the device
controller 60 determines a logical page number on the basis of a logical address
specified in accordance with this write command, and treats the logical page of this
logical page number as the read-destination logical page (3702). Next, the device
controller 60 detellnines a physical page number coil-esponding to the read-destination
logical page in accordance with referencing the page ~nappiilgm anagement table 1100,
and reads data from the physical page denoted by this physical page number (3703).
The read data, for example, is the old paiity. Next, the device controller 60 acquires a
new free page, and allocates the acquired physical page as a result-storage-destination
physical page (3704). Next, the device controller 60 pel-forms a parity operation using
the read data and the received data, and writes the operation result to the resultstorage-
destination physical page (3705).
101591 Next, the device controller 60 associates the result-storage-destination physical page
with the write-destination logical page in the page inapping management table 1100,
and registers the lluinber of the result-storage-destiilation physical page as the physical
page number (3706). Next, the device controller 60 sends a response denoting that the
cominand has bee11 completed to the system controller 20 (3707), and ends this flow of
processing.
[O160] According to this processing, the parity FMPK device controller 60 can compute a
post-update parity on the basis of the post-update data from the system co~ltrolle2r 0
and the pre-update parity stored in the parity FMPK, and send the post-update parity to
the parity FMPK. In addition, the system controller 20 can let the parity FMPK device
controller 60 create and store the post-update parity.
[0161] Next, a parity-create write process, which is a specific example of a process of the
device co~ltroller6 0 in a case where a paiity-create write coininand has been received,
will be explained.
[0162] This parity-create wiite process is a command for creating parity using data, which
has been transferred froin multiple stiipe blocks, and writing this parity to a specified
address. This parity-create write process, for example, is used in the first full-stripe
write process and the data restoration process described hereinabove.
LO1631 Fig. 38 shows an example of the processing of the device controller 60 in accordance
with a parity-create write command. Fisst, the device controller 60 receives a pa~itycreate
write co~ninand(3 801). Next, the device controller 60 determines a logical page
number on the basis of a logical address specified by this write cominand, and treats
the logical page of this logical page number as a wiite-destination logical page (3802).
Next, the device controller 60 acquires a new free page, and allocates the acquired
physical page as a write-destination physical page (3803). Next, the device controller
60 writes write-data received in accordance with the write coinmand to the wiitedestination
physical page (3804).
[OI 641 Next, the device controller 60 associates the write-destination physical page with the
write-destination logical page in the page inapping management table 1100, and
registers the number of the write-destination physical page as the physical page
number (3805). Next, the device controller 60 sends a response denoting the command
has been completed to the system controller 20 (3806), and ends this flow of
processing.
[0165] According to this processing, the parity FMPK device controller 60 is able to
compute a post-update parity on the basis of post-update data from the system
controller 20, and to write the post-update parity to the parity FMPK. In addition, the
system controller 20 call let the parity FMPK device controller 60 create and store the
post-update parity.
LO1661 Fig. 39 shows an example of a unmap-old-data process in accordance with the device
controller 60. First, the device contluller 60 receives a unmap-old-data command from
the system controller 20 (3901). Next, the device controller 60 determines the logical
page number from the logical address specified in this unmap-old-data command, and
deletes the old physical page number corresponding to this logical page number from
the page mapping management table 1100 (3902). The device controller 60 does not
invalidate the old data until the unmap-old-data command has been received. That is,
the device controller 60 is able to store the old data without fail until parity has been
updated (the unmap-old-data command has been received) even after new data has
been written. Thus, keeping the old data until parity is ~lpdatedm akes data restoration
possible even in a case where a failure has occui-sed piior to parity updating. Also, invalidating
and targeting the old data for an erase subsequent to parity being updated
makes it possible to reduce the amount of storage area being used by old data.
Example 2
LO1671 In this example, a case where the systeln controller 20 perforins RAID 6 control will
be explained.
[0168] The configuration of a computer systeln in this example is the same as the configuration
of the computer system it1 Example 1. Consequently, the differences with
Example I will be explained below.
101691 The system controller 20 performs RAID 6 control. Consequently, the difference
between a RAID 5 and a RAID 6 will be explained first.
[O170] In order to expand the RAID 5 explained hereinabove to a RAID 6, either the parity
circuit 25 or the parity circuit 65 pelforms an additional parity operation with a coefficient.
It is supposed here that five FMPK 50 are respectively stoiing the data DO,
Dl. D2, and parity P and Q. I11 a case where AO, Al, and A2 are used as the coefficients
for creating Q, P and Q are created in accordance with the following equations.
P=DO+D1 +D2
Q=AO*DO+Al *Dl+A2*D2
Fig. 40 shows a11 example of a method for creating Q parity. The parity operation implementation
apparatus stores AO, A 1, and A2 in lnelnoly beforehand. Q is computed
on the basis of DO, Dl, D2, AO, Al, and A2. A computing unit, which is shown as a
black diamond shape in the drawing, multiplies the coefficient attached thereto.
Solving for the P creation equation and the Q creation equation as a system of
equations makes it possible to restore arbitrary data and parity when data is lost. For
example, when restoring DO and P, DO and P can be created using the following
equations.
DO = Al/AO * Dl + A2IAOD2 + 1/AO * Q
P=DOi-D1+D2
For example, when res to~ingD O and D 1, it is possible to create DO and D 1 using the
following equations.
DO = (A1 + A2)/(AO + Al) * D2 + Al/(AO + Al) * P + l/(AO + Al) Q
Dl = (A0 + A2)/(AO + Al) * D2 + AO/(AO + Al) * P + l/(AO + Al) * Q
Fig. 41 shows an example of a method for restoring DO and D 1. As shown in [0165]
DO and Dl can each be expressed as the lineal- equation aaD2 + bbP + rrQ of D2, P
and Q. The coefficients aa, bb and rr here are values based on AO, A1 and A2.
The parity operation iinplelnentation apparatus inay store aa, bb and rs, which are
based on AO, A 1, and A2, in memory beforehand. The DO is computed on the basis of
aa, bb and rr, which are based on D2, P, Q, and AO, Al, and A2.
This example is strictly for putting fosth a concept. and is actually designed for increasing
processing speed and reducing the ainoLult of memory used.
Next, a fourth read-modify-write process, which is a specific example of a data
update psocess 1404 in a case where the device controller 60 has been selected as the
parity operation implelnentation apparatus and the read-modify-wiite has been selected
as the write method, will be explained.
Fig. 42 shows an example of the fo~u-thr ead-modify-write process. Fig. 42 shows an
example of the operation of the system controller 20 in the fourth read-modify-write
process. I11 this example, the FMPKs #O, #I, #2, #3, and #4 respectively store the DO,
the Dl, the D2, the P, and the Q. It is supposed here that the initial state is a state in
which the system controller 20 receives new data for updating the old data of DO in accordance
with a wlite command. In the following explanation, the FMPK #O storing
the DO, which is the data to be updated, may be called the data FMPK of the FMPKs
#0, #1, #2, #3, and #4. Also, the FMPK #3, which is storing the P, may be called the Pparity
FMPK of the FMPKs #0, #1, #2, #3, and #4. In addition, the FMPK #4, which is
stol-ing the Q, may be called the Q-parity FMPK of the FMPKs #O, #1, #2, #3, and #4.
First, the system controller 20 writes new data to the FMPK #O in accordance with
issuing an old-data-store write co~nlnandto the FMPK #0 corresponding to the DO (the
data FMPK) (4101). The device controller 60 of the FMPK #0, which receives this
conmand. writes the new data from the system controller 20 to a physical page that is
different from the old data physical page in the FMPK #O.
Next, the systeln controller 20 acquires a intermediate parity from the FMPK #O in
accordance with issuing a intermediate parity read command to the FMPK #0 (4102).
The device controller 60 of the FMPK #0, which receives this command, colnputes the
intermediate parity on the basis of the old data and the new data stored in the FMPK
#0, and sends the intelmediate parity to the systeln controller 20 as a response.
Next, the system controller 20 sends the intermediate parity to the FMPK #3 in accordance
with issuing the same parity-update write command as in the case of RAID 5
to the FMPK #3 corresponding to the P (the P-parity FMPK) (4103). The device
controller 60 of the FMPK #3, which receives this command, colnputes a new parity
on the basis of the old pality in the FMPK #3 and the intermediate paiity from the
systeln controller 20, and wlites the new parity to the FMPK #3.
The colnputation of a new pality P-new in a case where i is any one of 0, 1, or 2, and
data Di in the relevant RG is updated to Di-new, will be explained. The same as in
RAID 5, the device controller 60, which receives the parity-update write command,
cornputes P-new on the basis of a inteiinediate pality (Di + Di-new) and a11 old parity
P using the following equation.
P-new = P + (Di + Di-new)
The data FMPK device controller 60 colnputes (Di + Di-new) in accordance with the
intermediate parity read command. The P-parity FMPK device controller 60 colnputes
P + (Di + Di-new) in accordance with the parity-update write command.
Next, the system controller 20 tsansfers the intermediate parity to the FMPK #4 (the
Q-parity FMPK) in accordance with issuing a Q-parity-update wlite command, which
is a parity-update co~nrnandf or updating the Q, to the FMPK #4 corresponding to the
Q (4104), and ends this flow of processing. The device controller 60 of the FMPK #4,
which receives this command, computes a new parity on the basis of the old parity in
the FMPK #4, the intemediate parity from the systeln controller 20, and the coefficient,
and writes the new parity to the FMPK #3.
According to this processing, the transfer of data between the system controller 20
and the device controllers 60 in the updating of data of a single stripe block is as
follows.
(1) Post-update data is transferred from the systeln controller 20 to the data FMPK
device controller 60.
(2) Intermediate parity is transferred from the data FMPK device controller 60 to the
system controller 20.
(3) Tnteilnediate parity is transfel-red from the systein controller 20 to the P-parity
FMPK device controller 60 and the Q-pa~ityF MPK device controller 60.
This makes it possible to hold down the transfer of data between the systein
controller 20 and the device controller 60.
The processing of the device controller 60, which receives the Q-parity-update write
command, differs from that in the case of the parity-update wlite coln~nandin that a
coefficient Ai, which is configmed in the device controller 60 beforehand, is used. In a
case where the data Di in the relevant RG is updated to Di-new, the device controller
60, which receives the Q-parity-update write comma~ldc, omputes a new parity Q-new
on the basis of the intermediate parity (Di + Di-new), the old parity Q, and the Ai
using the following equation.
Q-new = Q + Ai * (Di + Di-new)
The data FMPK device controller 60 computes (Di + Di-new) in accordance with the
intermediate parity read command. The Q-parity FMPK device controller 60 computes
Q + Ai * (Di + Di-new) in accordance with the Q-parity-update wlite command.
According to the parity-update wiite command, the P-pa~ityF MPK device controller
60 can compute a post-update P paiity on the basis of post-update data from the system
controller 20 and the pre-update P parity stored in the P-parity FMPK, and write the
post-update P parity to the P-parity FMPK. I11 addition, the system controller 20 can let
the P-parity FMPK device controller 60 create and store the post-update P parity.
According to the Q-parity-update write command, the Q-paiity FMPK device
controller 60 can compute a post-update Q parity on the basis of post-update data from
the system controller 20, the pre-update Q pa~itys tored in the Q-pality FMPK, and a
prescsibed coefficient, and write the post-update Q parity to the Q-parity FMPK. In
addition, the system controller 20 can let the Q-parity FMPK device controller 60
create and store the post-update Q parity.
Example 3
In this example, a computer system, which is an example of a storage system 30 application
in a case where the system controller 20 does not comprise a parity operation
function, will be explained.
Fig. 44 shows an example of the configuration of a computer system related to
Example 3. In the computer systein of this example, an element, which has been
assigned the same reference sign as an element of the storage system 30, denotes either
the same or an equivalent eleinent as the element of the storage system 30. The
computer systein of this exa~nplec oinprises a host computer 41a, a host computer 41b,
and multiple FMPKs 50 coupled to the host computer 41b. The host coinputer 41a and
the host computer 41b, for example, are coupled via a LAN (Local Area Network) 2.
The host coinputer 41a comprises a host controller 42a, and multiple FMPKs 50
coupled to the host controller 42a. The host controller 42a comprises a NIC (Network
Interface Card) 13 for coupling to a communication network such as the LAN 2, a
memory 12, a CPU 1 I, and a buffer 26.
The host computer 41b coinprises a NIC 13 for coupling to a communication
network such as the LAN 2, a HBA (Host Bus Adapter) 15 for coupling to a FMPK 50,
a memory 12, a CPU 11, and a buffer 26.
In the host controller 42a and the host coinputer 4 lb, the melnoly 12 stores a
program and various types of information for controlling the FMPK 50. The CPU 11
realizes various types of functions in accordance with executing the program based on
the information stored in the memory 12. Each of the host controller 42a and the host
computer 41b inay pel-form RAID control using the multiple FMPKs 50 coupled to
itself.
One of the host controller 42a or the host computer 41b inay cai-ry out an I 0 request
to the other via the LAN 2, or may carry out an 10 request to its own FMPK 50.
In this example, the systein controller 20 inay by an aspect of either the host
controller 42a or the host computer 41b.
Each of the host controller 42a and the host computer 41b col-respond to either case
#3 or case #4 of the method 1300 for deciding the parity operation impleinentation
apparatus.
Example 4
Next, a third computer system, which is an example of a storage system 30 application
in a case where the system controller 20 compl.ises a parity operation
function, will be explained.
Fig. 45 shows an example of the configuration of a computer systein related to
Example 4. In the computer system of this example, an element, which has been
assigned the same reference sign as an element of the computer system of Example 3,
denotes either the same or an equivalent element as the element of the computer
system of Example 3. The computer system of this example comprises a host computer
41c, a host computer 41d, and multiple FMPKs 50 coupled to the host coinputer 41d.
The host computer 41c and the host cornputer 41d, for example, are coupled via a communication
network, for example, a LAN 2.
The host computer 41c comprises a host cont~.oller4 2c, and multiple FMPKs 50
coupled to the host controller 42c. The host controller 42c, in addition to the elements
of the host controller 42a, comprises a parity circuit 25.
The host coinputer 41d, in addition to the elements of the host coinputer 41b,
cornprises a parity circuit 25.
In the host col~trolle4r 2c and the host computer 41d, the memoly 12 stores a
program and various types of iilfoiinatioll for coiltrollillg the FMPK 50. The CPU 1 I
realizes various types of functions in accordance with executing the program based on
the information stored in the memory 12. Each of the host controller 42c and the host
computer 41d may pel-folm RAlD coiltrol using the multiple FMPKs 50 coupled to
itself.
One of the host colltroller 42c or the host computer 41d inay carry out an 10 request
to the other via the LAN 2, or may carry out an I0 request to the device controller 60
of its own FMPK 50.
Each of the host controller 42a and the host computer 41 b correspond to either case
#1 or case #2 of the method 1300 for deciding the parity operation implemelltation
apparatus.
In this example, the system controller 20 inay be an aspect of either of the host
colltroller 42c or the host computer 41d.
The computer system may be a combination of the elements of any of the examples
described hereinabove. A system coiltroller 20, which coinprises a paiity operation
function, and a system controller 20, which does not compiise a parity operation
f~inctionm, ay co-exist in a single coinputer system.
According to the respective examples deschbed hereinabove, the trailsfer of data
between the systeln controller 20 and the device controller 60 can be held in check.
This makes it possible to enhance the speed of the storage systeln 30. A data transfer,
for example, is expressed as a number of data transfers, or as a11 amount of data
transfersed.
According to the respective examples described hereinabove, in addition to holding
down the trailsfer oS data between the systeln contl-oller 20 and the device contluller
60, the present illventioil can also reduce the amount of volatile memory that is used in
the device controller 60.
The sequence of the respective processes in the operation of the system colltroller 20
may be switched. For example, 1402 and 1403 call be switched. The sequence of the
respective psocesses in the operation of the device co~ltrolle6r 0 may also be switched.
For example, 3703 and 3704 call be switched.
Reference Signs List
10 Host computer
20 System controller
25 Parity circuit
26 Buffer
30 Storage system
41a, 41b, 41c, 41d Host coinputer
42a, 42c Host controlles
50 FMPK (Flash ineinory package)
55 FM (Flash memory)
60 Device colltroller
65 Parity circuit
66 Buffer
Claims
[Claiin 11
[Claiin 21
[Claim 31
A storage system complising:
a first controller; and
a plurality of storage devices configuring RAID, each of which
includes one or more non-volatile Inelnosy chips providing storage
space where data from a host computer is stored, and a second
controller coupled to the non-volatile memory chips,
wherein, when the first controller receives an update request to update
first data to second data from the host coinputer,
the second controller in a first storage device of the storage devices is
configured to store the second data in an area different from an area
where the first data has been stored, in the storage space of the first
storage device; generate infoilnation that relates the first data and the
second data; and generate an intermediate parity based on the first and
the second data,
wherein, the second controller in a second storage device of the storage
devices that stores a first parity coi~espondingto the first data is
configured to receive the intermediate parity, generate a second parity
based on the first paiity and the inter~nediatep arity, and store the
secoild parity in an area in the storage space of the second storage
device,
wherein the second contl-ollel- in the first storage device is configured to
delete the information after the second parity is stored in the area in the
storage space of the second storage device, and set the area where the
first data has been stored as a erase target area.
The storage system according to claim 1,
wherein, the first controller is configured to send a generation request
of the intermediate parity to the second controller in the first storage
device,
wherein, the second controller in the first storage device is configured
to, in response to the generation request, generate the intermediate
parity, and send the generated inteilnediate pality to the first controller.
The storage system according to claim 2,
wherein, the first controller is configured to send a generation request
of the second parity with the intermediate parity to the second
controller in the second storage device,
wherein, the second controller in the second storage device is
[Claiin 41
[Claiin 51
[Claiin 61
configured to store the second parity ill the area in the storage space of
the second storage device, and send a completion notice to the first
controller.
The storage system according to claim 3,
wherein, if not receiving the completion notice in a predetermined time,
the first controller is configured to resend the generation request of the
intermediate parity to the second controller in the first storage device,
and resend the generation request of the second parity with the intermediate
parity generated in response to the resent generation request
to the second controller in the second storage device.
The storage system according to claim 4,
wherein, if 110 charactelistics of the update request are sequential
writes, the fisst controller is configured to generate the second pa~ity
based on write data of the update request without issuing the generation
requests of the intel-mediate parity and the second parity, and send the
second parity or a pait of the write data to the storage devices,
wherein, the secoild controller of each of the storage devices is
configured to store the received second parity or the received past of
the write data in an area in the storage space thereof.
In a storage system coinprising a first controller and a plurality of
storage devices configusing RAID, each of which includes one or inore
non-volatile inemory chips providing storage space where data from a
host coinputer is stored, and a second controller coupled to the nonvolatile
ineinory chips, a method comprising:
receiving, at the first controller, an update request to update first data to
second data from the host computer; and sending the second data to the
second controller in a first storage device of the storage devices,
storing, at the second controller in the first storage device, the second
data in an area different from an area where the first data has been
stored, in the storage space of the first storage device; generating information
that relates the first data and the second data; and generating
an interinediate parity based on the first and the secoild data;
receiving, at the second controller in a second storage device of the
storage devices that stores a first parity corresponding to the first data,
the intermediate parity; generating a second parity based on the first
parity and the inte~~nediaptaer ity; and storing the second parity in an
area in the storage space of the second storage device,
deleting, at the second controller in the first storage device, the in[
Claiin 71
[Claim 81
[Claim 91
[Claiin 101
formation after the second parity is stored in the storage areas of the
second storage device; and setting the area where the first data has been
stored as a erase target area.
The method according to claim 6, fui-ther comnprising:
sending, at the fisst controller, a generation request of the intelmediate
parity to the second controller in the first storage device,
generating, at the second controller in the first storage device, the intermediate
pality, in response to the generation request, and sending the
generated intermediate parity to the first controller.
The method according to claim 7, ful-ther comprising:
sending, at the first controller, a generation request of the second parity
with the intermediate parity based 011 the first controller to the second
controller in the second storage device,
stoiing, at the second controller in the second storage device, the
second parity in the area in the storage space of the second storage
device; and sending a completioil notice to the first controller.
The method according to claim 8, fui-ther comprising:
resending, at the first controller, the generation request of the inteimediate
paiity to the second controller in the first storage device, if
the completion notice is not received in a predetermined time; and
resending the generation request of the second pality with the intermediate
parity generated in response to the ~-esengt eneration request
to the second controller in the second storage device.
The method according to claim 9, f~lsthecr omprising:
generating, at the first controller, the second parity from write data of L
the update request without issuing the generation request of the second
parity, if 110 characteristics of the update request are sequential writes;
and sending the second parity or a part of the write data to the storage
devices,
storiing, at the second controller of each of the storage devices, the
received second parity or the received part of the write data in an area
in the storage space thereof.