Description:TECHNICAL FIELD
[1] The present disclosure generally relates to a supercapacitor device. In particular, the present disclosure relates to a supercapacitor device with improved electrochemical capacitance and smaller form factor.

BACKGROUND
[2] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[3] The increasing popularity of wearable gadgets and other miniaturized electronic devices has led to a surge in demand for smaller, more efficient energy storage systems. To meet this demand, work is being conducted on developing on-chip solid-state energy storage devices that can be integrated into these devices. One promising approach is the use of electrochemical capacitors, which are a type of energy storage device that can provide high power density and long cycle life. However, one of the challenges of miniaturizing these devices is that conventional electrode geometries and materials like porous carbon and metal oxides can limit electron mobility and overall performance.
[4] To overcome this limitation, new techniques and materials for creating more efficient and effective energy storage systems may be required. The field of two dimensionsal (2D) materials is rapidly evolving, and they have emerged as promising candidates for energy storage applications due to their unique properties. Some of the important properties required for high-performance energy storage devices include high surface area, fast ion diffusion, electronic conductivity and intercalation sites. Different 2D materials, such as graphene, transition metal dichalcogenides (TMDCs), and black phosphorus, exhibit different combinations of these properties. For example, graphene has high electronic conductivity but low intercalation sites, while TMDCs such as MoS2 and WS2 have abundant intercalation sites but relatively low electronic conductivity. However, the challenge is to provide an integrated device that may provide high power density and long cycle life.

OBJECTS OF INVENTION
[5] An object of the present invention is to provide a supercapacitor device for energy storage.
[6] Another object of the present invention is to provide a supercapacitor device with a small form factor that has a high energy density.

SUMMARY
[7] The present disclosure generally relates to a supercapacitor device. In particular, the present disclosure relates to a supercapacitor device with improved electrochemical capacitance and smaller form factor.
[8] In an aspect, the present disclosure provides a supercapacitor device. The supercapacitor device includes a substrate. The supercapacitor device further includes a first set of electrodes disposed on the substrate. The first set of electrodes includes first, second, and third current collectors disposed adjacent to each other on a top plane of the substrate. Each of the first, second, and third current collectors extends along a first direction on the top plane of the substrate. The first set of electrodes further includes a first heterostructure layer including a first set of materials. The first heterostructure layer is disposed on the first, second, and third current collectors. The supercapacitor device further includes a second set of electrodes disposed on the substrate. The second set of electrodes is separated from the first set of electrodes by a predefined first distance along a second direction on the top plane of the substrate. The second set of electrodes includes fourth, fifth, and sixth current collectors disposed adjacent to each other on the top plane of the substrate. Each of the fourth, fifth, and sixth current collectors extends along the first direction. The second set of electrodes further includes a second heterostructures layer including the first set of materials. The second heterostructure layer is disposed on the fourth, fifth, and sixth current collectors. The supercapacitor device further includes an electrolyte disposed on the substrate, on the first and second sets of electrodes. The electrolyte is adapted to electrochemically couple the first and second sets of electrodes. The first set of materials includes two-dimensional (2D) materials.
[9] In some embodiments, the substrate includes a first layer including silicon. The substrate further includes a second layer disposed on top of the first layer. The second layer includes silicon dioxide.
[10] In some embodiments, the first and second sets of electrodes include a set of metals selected from any or a combination of chromium, nickel, gold, platinum, and silver.
[11] In some embodiments, the first and second sets of electrodes are deposited on the substrate using a combination of electron-beam lithography, and electron-beam evaporation.
[12] In some embodiments, the predefined first distance is between about 2.8 micrometers (m) and about 20 (m).
[13] In some embodiments, the first, second, and third current collectors are disposed parallel to each other. Further, the fourth, fifth, and sixth current collectors are disposed parallel to each other.
[14] In some embodiments, the first, second and third current collectors are separated from each other along the second direction by a predefined second distance. Further, the fourth, fifth, and sixth current collectors are separated from each other along the second direction by the predefined second distance. The predefined second distance is between about 2 m and about 8 m.
[15] In some embodiments, each of the first, and second heterostructure layers includes a first 2D material layer disposed on the respective first, second, and third current collectors, and the fourth, fifth and sixth current collectors. Each of the first, and second heterostructure layers further includes a second 2D material layer disposed on the first 2D material layer. The first 2D material layer includes a transition metal dichalcogenide (TMDC). The second 2D material includes any one or a combination of graphene, black phosphorus, and carbon nanotubes.
[16] In some embodiments, the first 2D material layer further includes a plurality of layers of the TMDC obtained by exfoliation from a bulk crystal of the TMDC.
[17] In some embodiments, the second 2D material layer includes a plurality of layers of graphene exfoliated from a bulk crystal of graphene.
[18] In some embodiments, the electrolyte includes any one or a combination of a solid-state electrolyte including polyvinyl alcohol (PVA) and sulfuric acid, and a liquid electrolyte.
[19] In some embodiments, an areal capacitance of the supercapacitor device is between about 1.8 milli Farad per square centimeter (mF/cm2) and about 55 mF/cm2 based on a back gate voltage supplied to the supercapacitor device being varied respectively between about -30 volts (V) and about +30 V.
[20] In some embodiments, the areal capacitance of the supercapacitor device is about 55 mF/cm2 when the back gate voltage supplied to the supercapacitor device is about -25 V.
[21] In some embodiments, a capacitance enhancement of the supercapacitor device is between about 200% and about 3000% based on a back gate voltage supplied to the supercapacitor device being varied respectively between about -5 V and about -40 V.
[22] In some embodiments, the capacitance enhancement of the supercapacitor device is about 1600% when the back gate voltage supplied to the supercapacitor device is about -25 V.
[23] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF DRAWINGS
[24] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[25] FIG. 1 illustrates a schematic representation of a supercapacitor device, in accordance with an embodiment of the present disclosure;
[26] FIG. 2 illustrates an exemplary plot depicting galvanostatic charge-discharge (GCD) curves for the supercapacitor device;
[27] FIG. 3A illustrates an exemplary plot depicting a results of cyclic voltammetry (CV) measurements performed on the supercapacitor device;
[28] FIG. 3B illustrates an exemplary plot depicting percentage capacitance enhancement in the supercapacitor device;
[29] FIG. 4A illustrates an exemplary plot depicting a variation in calculated areal capacitances of the supercapacitor device; and
[30] FIG. 4B illustrates an exemplary plot depicting GCD curves from which the areal capacitances of the plot of FIG. 4A.

DETAILED DESCRIPTION
[31] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such details as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[32] FIG. 1 illustrates a schematic representation of a supercapacitor device 100, in accordance with an embodiment of the present disclosure. The supercapacitor device 100 may interchangeably be referred to as “the device 100”. The device 100 includes a substrate 102. The substrate 102 may include one or more layers. In some embodiments, the substrate 102 includes a first layer 102-1 including silicon. In some embodiments, the substrate 102 further includes a second layer 102-2 disposed on top of the first layer 102-1. The second layer 102-2 may include silicon dioxide. In some embodiments, the second layer 102-2 may have a thickness of about 300 nanometers (nm). The substrate 102 may extend along first and second directions 192, 194. The first and second directions 192, 194 may be along a plane of the substrate 102. Further, the first and second directions 192, 194 may be orthogonal to each other.
[33] The device 100 further includes first and second sets of electrodes 110, 130. The first and second sets of electrodes 110, 130 may be disposed on a top plane 190 of the substrate 102. The first and second sets of electrodes 110, 130 may be separated from each other along the second direction 194 by a predefined first distance d1. In some embodiments, the predefined first distance d1 may be between about 2.8 micrometers (m) and about 20 m. In some examples, the predefined first distance d1 may be about 20 m.
[34] The first set of electrodes 110 includes first, second, and third current collectors 112, 114, 116 disposed on the top plane 190 of the substrate 102. The first, second, and third current collectors 112, 114, 116 are disposed adjacent to each other. The first, second, and third current collectors 112, 114, 116 are configured as strips (or fingers) and are arranged to extend along the first direction 192 on the substrate 102. Each of the first, second, and third current collectors 112, 114, 116 may have a width of about 4 m. In some embodiments, the first, second, and third current collectors 112, 114, 116 are arranged parallel to each other. Further, in some embodiments, the first, second, and third current collectors 112, 114, 116 are separated from each other along the second direction 194 by a predefined second distance d2. In some embodiments, the predefined second distance d2 may be between 2 m and about 8 m. In some examples, the predefined second distance d2 may be about 2 m.
[35] In some embodiments, the first set of electrodes 110 may include a metal. The metal may be any one or a combination of, without limitations, chromium, nickel, gold, platinum, and silver. In some examples, each of the first, second, and third current collectors 112, 114, 116 may include a combination of chromium and gold. In such examples, each of the first, second, and third current collectors 112, 114, 116 may include a first layer of chromium and a second layer of gold. The first layer of chromium may have a thickness of about 5 nm, and the second layer of gold may have a thickness of about 50 nm. Further, the first set of electrodes 110 may be deposited on the substrate 102 by a suitable metal deposition technique. For example, the first set of electrodes 110 may be deposited on the substrate 102 using a combination of electron-beam lithography, and electron-beam evaporation.
[36] The first set of electrodes 110 further includes a first heterostructure layer 118 deposited on the first, second, and third current collectors 112, 114, 116. The first heterostructure layer 118 includes a first set of materials. In some embodiments, the first set of materials includes two-dimensional (2D) materials. In some embodiments, the first heterostructure layer 118 includes a first 2D material layer disposed on the first, second, and third current collectors 112, 114, 116. The first heterostructure layer 118 further includes a second 2D material layer disposed on the first 2D material layer. In some embodiments, the first 2D material layer may include a transition metal dichalcogenide (TMDC). Further, in some embodiments, the first 2D material layer may include a plurality of layers of the TMDC. The plurality of layers of the TMDC may be obtained by exfoliation of a bulk crustal of the TMDC. In some embodiments, the TMDC may include, without limitations, MoS2, WS2, etc. In some examples, the TMDC includes MoS2.
[37] In some embodiments, the second 2D material may include any one or a combination of graphene, black phosphorus, and carbon nanotubes. In some examples, the second 2D material layer may include a plurality of layers of graphene. The plurality of layers of graphene may be obtained by exfoliation of a bulk crustal of the graphene.
[38] In an instance of implementation, a few layers of MoS2 may be mechanically exfoliated from the bulk crystal, and then directly transferred over each of the first, second, and third current collectors 112, 114, 116. Subsequently, flakes of a few-layer graphene may be transferred on the deposited MoS2 to create the first heterostructure layer 118.
[39] The second set of electrodes 130 includes fourth, fifth, and sixth current collectors 132, 134, 136 disposed on the top plane 190 of the substrate 102. The fourth, fifth, and sixth current collectors 132, 134, 136 are disposed adjacent to each other. The fourth, fifth, and sixth current collectors 132, 134, 136 are configured as strips (or fingers) and are arranged to extend along the first direction 192 on the substrate 102. Each of the fourth, fifth, and sixth current collectors 132, 134, 136 may have a width of about 4 m. In some embodiments, the fourth, fifth, and sixth current collectors 132, 134, 136 are arranged parallel to each other. Further, in some embodiments, the fourth, fifth, and sixth current collectors 132, 134, 136 are separated from each other along the second direction 194 by the predefined second distance d2. In some examples, the predefined second distance d2 may be about 4 m.
[40] In some embodiments, the second set of electrodes 130 may include a metal. The metal may be any one or a combination of, without limitations, chromium, nickel, gold, platinum, and silver. In some examples, each of the fourth, fifth, and sixth current collectors 132, 134, 136 may include a combination of chromium and gold. In such examples, each of the fourth, fifth, and sixth current collectors 132, 134, 136 may include a first layer of chromium and a second layer of gold. The first layer of chromium may have a thickness of about 5 nm, and the second layer of gold may have a thickness of about 50 nm. Further, the second set of electrodes 130 may be deposited on the substrate 102 by a suitable metal deposition technique. For example, the second set of electrodes 130 may be deposited on the substrate 102 using a combination of electron-beam lithography, and electron-beam evaporation.
[41] The second set of electrodes 130 further includes a second heterostructure layer 138 deposited on the fourth, fifth, and sixth current collectors 132, 134, 136. The second heterostructure layer 138 includes the first set of materials. In some embodiments, the first set of materials includes two-dimensional (2D) materials In some embodiments, the second heterostructure layer 138 includes a first 2D material layer disposed on the fourth, fifth, and sixth current collectors 132, 134, 136. The second heterostructure layer 138 further includes a second 2D material layer disposed on the first 2D material layer. In some embodiments, the first 2D material layer may include the TMDC. Further, in some embodiments, the first 2D material layer may include a plurality of layers of the TMDC. In some examples, the TMDC includes MoS2.
[42] In some embodiments, the second 2D material may include any one or a combination of graphene, black phosphorus, and carbon nanotubes. In some examples, the second 2D material layer may include a plurality of layers of graphene.
[43] In an instance of implementation, a few layers of MoS2 may be mechanically exfoliated from the bulk crystal, and then directly transferred over each of the fourth, fifth, and sixth current collectors 132, 134, 136. Subsequently, flakes of a few-layer graphene may be transferred on the deposited MoS2 to create the second heterostructure layer 138.
[44] Once the first and second sets of electrodes 110, 130 are deposited on the substrate 102, the device 100 may annealed in an inert environment to remove organic residue. In some embodiments, the device 100 may be annealed at about 100 degrees centigrade (C) for about 4 hours in a nitrogen (N2) environment.
[45] The device 100 further includes an electrolyte 140 deposited on the substrate 102, on the first and second sets of electrodes 110, 130. The electrolyte 140 may be adapted to electrochemically couple the first and second sets of electrodes 110, 130. In some embodiments, the electrolyte 140 may be a solid-state electrolyte. In some examples, the electrolyte 140 is obtained from a gel mixture of polyvinyl alcohol (PVA) and sulfuric acid. The electrolyte 140 may provide a solid-state interface between the first and second sets of electrodes 110, 130, allowing for the transfer of ions and electrons therebetween.
[46] In an instance of implementation, about 2 grams (g) of PVA may be mixed in about 20 milliliters (mL) of deionized water at about 90 C for about 3 hours. Once the PVA is dissolved, a 1 molar (M) solution of sulfuric acid is added to the PVA solution. The mixture is stirred for about 1 hour at room temperature to obtain a homogenous and conductive gel. The gel may be drop-casted on the substrate 102, such that the first and second sets of electrodes 110, 130 are covered.
[47] In some other embodiments, the electrolyte 140 may be a liquid electrolyte. In some embodiments, the electrolyte 140 may further be a combination of the solid-state electrolyte and the liquid electrolyte.
[48] Electrochemical and electrical tests may be performed on the device to evaluate a performance of the device 100. The third and sixth current collectors 116, 136 may be used as cathode and anode, respectively, for electrochemical measurements using a potentiostat. The electrochemical measurements may be performed using a two-electrode system connected to an electrochemical workstation. Further, the first and second current collectors 112, 114, and the fourth and fifth current collectors 132, 134 may be used for electrical measurements to evaluate a performance of the first and second heterostructure layers 118, 138 using a semiconductor analyzer. Furthermore, galvanostatic charge-discharge (GCD) measurements may conducted on the device 100 at different current densities. The electrochemical and electrical measurements performed may provide insights into the energy storage performance of devices 100.
[49] FIG. 2 illustrates an exemplary plot 200 depicting GCD curves for the device 100. The GCD curves are obtained for different current densities. The plot 200 depicts curves 202, 204, 206, 208, 210 obtained at respective current densities of 0.2 milli Amperes per square centimeter (mAcm-2), 0.25 mAcm-2, 0.3 mAcm-2, 0.4 mAcm-2, and 0.5 mAcm-2. An areal capacitance (CA) may be measured using,

where td is a discharge time, and I is current.
[50] The CA varies from about 2.5 milli Farad per square centimeter (mFcm-2) at a current density of 0.2 mAcm-2 to 1.86 mFcm-2 at a current density of 0.5 mAcm-2.
[51] FIG. 3A illustrates an exemplary plot 300 depicting a results of cyclic voltammetry (CV) measurements performed on the device 100. The plot 300 shows two voltammograms 302, 304 depicting electrochemical performance of the device 100, a similar reference device. However, the reference device may not include the graphene layer in the first and second heterostructure layers 118, 138. The CV is performed by measuring current for a potential range of 0 volt (V) to 0.8 V at a scan rate of 50 millivolts per second (mVs-1). Gate controlled electrochemical capacitance is also evaluated. The voltammograms show a dominant diffusion-controlled response of charge storage that varies with the applied gate potential.
[52] FIG. 3B illustrates an exemplary plot 350 depicting percentage capacitance enhancement in the device 100. The percentage capacitance enhancement may be a function of gate-to-source voltage Vgs.
[53] Referring now to FIGs. 3A and 3B, the CA at no back gate voltage condition is measured to be 1.81 mFcm-2, when the Vgs is varied from 0 V to -40 V. From the plot 350, it may be seen that the device 100 shows a capacitance enhancement of 3000% at a Vgs of -25 V.
[54] The capacitive enhancement may be attributed to polarization charges between interlayers of MoS2 along with graphene, which results in attraction of more positive ions (H+) from the electrolyte 140. As a result, an electric double layer (EDL) may be formed not only on the surface of the first and second sets of electrodes 110, 130, but also between interlayers of the MoS2 and graphene. The EDL may effectively increase a surface area available for charge storage, thereby enhancing the capacitance of the device 100. As can further be seen from the plot 350, the capacitive enhancement varies with varying Vgs, suggesting that the gate voltage may play a critical role in modulating the EDL and the resulting capacitance.
[55] FIG. 4A illustrates an exemplary plot 400 depicting a variation in calculated areal capacitances of the device 100 for different values of Vgs. The areal capacitances are calculated at a current density of 0.4 mAcm-2.
[56] FIG. 4B illustrates an exemplary plot 450 depicting GCD curves from which the areal capacitances of the plot 400 are calculated. The plot 450 depicts curves 452, 454, 456, 458, 460, 462, 464, 466, 468 obtained at respective Vgs values of -30 V, -25 V, -20 V, -10 V, 0 V, 10 V, 20 V, 25 V and 30 V.
[57] Referring now to FIGs. 4A and 4B, the plot 450 shows that the GCD curves change as a function of the applied Vgs. Specifically, the device 100 shows a large increment in the charging and discharging times for negative Vgs, indicating the influence of the gate voltage on the charge storage behavior. The corresponding areal capacitance values are calculated and show in the plot 400. A maximum capacitance enhancement of about 1677% may be observed at a Vgs of -25 V.
[58] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprise” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refer to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc. The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.
[59] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions, or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF INVENTION
[60] The present invention provides a supercapacitor device for energy storage.
[61] The present invention provides a supercapacitor device with a small form factor that has a high energy density.
, Claims:1. A supercapacitor device (100), comprising:
a substrate (102);
a first set of electrodes (110), disposed on the substrate (102), the first set of electrodes (110) comprising:
first, second, and third current collectors (112, 114, 116) disposed adjacent to each other on a top plane (190) of the substrate, each of the first, second, and third current collectors (112, 114, 116) extending along a first direction (192) on the substrate (102); and
a first heterostructure layer (118) comprising a first set of materials, disposed on the first, second, and third current collectors (112, 114, 116);
a second set of electrodes (130) disposed on the substrate (102) and separated from the first set of electrodes (110) by a predefined first distance (d1) along a second direction (192) on the substrate (102), the second set of electrodes (130) comprising:
fourth, fifth, and sixth current collectors (132, 134, 136) disposed adjacent to each other on the top plane (190) of the substrate (102), each of the fourth, fifth, and sixth current collectors (132, 134, 136) extending along the first direction (192); and
a second heterostructures layer (138) comprising the first set of materials, disposed on the fourth, fifth, and sixth current collectors (132, 134, 136); and
an electrolyte (140) disposed on the substrate (102), on the first and second sets of electrodes (110, 130), and adapted to electrochemically couple the first and second sets of electrodes (110, 130),
wherein, the first set of materials comprises two-dimensional (2D) materials.

2. The supercapacitor device (100) as claimed in claim 1, wherein the substrate (102) comprises:
a first layer comprising silicon; and
a second layer disposed on top of the first layer, and comprising silicon dioxide.

3. The supercapacitor device (100) as claimed in claim 1, wherein the first and second sets of electrodes (110, 130) comprise a set of metals selected from any or a combination of chromium, nickel, gold, platinum, and silver.

4. The supercapacitor device (100) as claimed in claim 1, wherein the first and second sets of electrodes (110, 130) are deposited on the substrate (102) using a combination of electron-beam lithography, and electron-beam evaporation.

5. The supercapacitor as claimed in claim 1, wherein the predefined first distance (d1) is between about 2.8 micrometers (m) and about 20 (m).

6. The supercapacitor as claimed in claim 1, wherein,
the first, second and third current collectors (112, 114, 116) are disposed parallel to each other, and
the fourth, fifth, and sixth current collectors (132, 134, 136) are disposed parallel to each other.

7. The supercapacitor device (100) as claimed in claim 6, wherein,
the first, second and third current collectors (112, 114, 116) are separated from each other along the second direction (194) by a predefined second distance (d2),
the fourth, fifth, and sixth current collectors (132, 134, 136) are separated from each other along the second direction (194) by the predefined second distance (d2), and
the predefined second distance (d2) is between about 2 m and about 8 m.

8. The supercapacitor device (100) as claimed in claim 1, wherein each of the first, and second heterostructure layers (118, 138) comprises:
a first 2D material layer disposed on the respective first, second, and third current collectors (112, 114, 116), and the fourth, fifth and sixth current collectors (132, 134, 136); and
a second 2D material layer disposed on the first 2D material layer,
wherein,
the first 2D material layer comprises a transition metal dichalcogenide (TMDC), and
the second 2D material comprises any one or a combination of graphene, black phosphorus, and carbon nanotubes.

9. The supercapacitor device (100) as claimed in claim 8, wherein the first 2D material layer further comprises a plurality of layers of the TMDC obtained by exfoliation from a bulk crystal of the TMDC.

10. The supercapacitor device (100) as claimed in claim 8, wherein the second 2D material layer further comprises a plurality of layers of graphene exfoliated from a bulk crystal of graphene.

11. The supercapacitor device (100) as claimed in claim 1, wherein the electrolyte (140) comprises any one or a combination of an electrolyte comprising polyvinyl alcohol (PVA) and sulfuric acid, and a liquid electrolyte.

12. The supercapacitor device (100) as claimed in claim 1, wherein an areal capacitance of the supercapacitor device (100) is between about 1.8 milli Farad per square centimeter (mF/cm2) and about 55 mF/cm2 based on a back gate voltage supplied to the supercapacitor device (100) being varied respectively between about -30 volts (V) and about +30 V.

13. The supercapacitor device (100) as claimed in claim 12, wherein the areal capacitance of the supercapacitor device (100) is about 55 mF/cm2 when the back gate voltage supplied to the supercapacitor device (100) is about -25 V.

14. The supercapacitor device (100) as claimed in claim 1, wherein a capacitance enhancement of the supercapacitor device (100) is between about 200% and about 3000% based on a back gate voltage supplied to the supercapacitor device (100) being varied respectively between about -5 V and about -40 V.

15. The supercapacitor device (100) as claimed in claim 14, wherein the capacitance enhancement of the supercapacitor device (100) is about 1600% when the back gate voltage supplied to the supercapacitor device (100) is about -25 V.