[0001] A memory, such as a random access memory (SRAM) and read only memory (ROM), includes a number of memory cells arranged in multiple rows called as word lines and several columns known as bit lines, bach memory cell stores one bit of data. In order to perform a read operation for these memory cells, a variety of sense amplifiers such as balanced sense amplifiers and unbalanced or single-ended sense amplifiers are used |0002| Typically, the sense amplifiers (SA) perform the read operation by determining the differential voltage between its two sensing nodes, for this, the sensing nodes of balanced SA are coupled to two complementary bit lines, for example bit line true (111. 1 ) and bit line false (BLF'). On the other hand, one sensing node of unbalanced SA is coupled to a single bit line, such as BLT, while the other node is coupled to a power supply. Moreover, the bit lines, or in other words primary bit lines, in a memory are directly connected to pass transistors and are then multiplexed to secondary bit lines, and so on. The bit lines arc selected, during operation, with the help of the pass transistors, which are operated by an output of a multiplexer driver circuit. applied at the gate of the pass transistors. Also, (he bit lines undergo various levels of multiplexing to produce secondary bit lines, due to which there is an inherent coupling between the gates of the pass transistors and the multiplexed bit lines. In other words, she power supply is coupled to the multiplexed bit lines [0003| When there is a high power demand for read and write operations of the memory. there are unwanted fluctuations and oscillations in the power supply. These fluctuations and oscillations arc caused due to inductive and capacitive reactance on account of charging and discharging of a variety of components of the memory such as capacitors, transistors, and so on. Since a power-supply-coupled bit line and a separate power supply are coupled to the sensing nodes of unbalanced SA. therefore due to such variations in the power supply, errors are introduced in the operation of SA. However, to prevent such errors few solutions have been implemented, J0004] In one solution, noise margin of SA is increased to segregate operational voltage of SA beyond the produced disturbances in the supply voltage However, an increase in the noise margin, increases power consumption of unbalanced SA due to an extended charging and discharging of associated capacitors to change the stale of SA. Moreover, this extended charging and discharging of the capacitors slow down the operation of SA. In another solution, a large decoupling capacitor having a very high capacitance is directly connected to the power mesh. which is coupled to the supply voltage, over which a memory circuit is fabricated. I he power mesh satisfies power requirements of a memory chip. However, such a large decoupling capacitor is area intensive and for a full compiler range area penalty is too high. [0005) Therefore, there exists a need for an efficient single-ended sensing scheme, which is resistant to noise from the supply voltage without an escalation of power requirements for performing a reliable read operation. Moreover, such single-ended sensing scheme should not suffer from space constraints. |0006] This summary is provided to introduce concepts related to a supply noise tolerant single-ended sensing scheme, which is further described below in the detailed description, fhis summary is not intended to identify essential features ol the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject mailer. [0007] In an implementation, the supply noise tolerant single-ended sensing scheme (SNT-SSS) includes a single-ended sense amplifier (SSA). a first reference line (FRIT) and a second reference line (SREF). SNT-SSS further includes a first decoupling transistor, a second decoupling transistor, a first sampling transistor, a second sampling transistor, and a power supply. The first and the second decoupling transistors and the first and the second sampling transistors can be realized with the help of p-channel MOSFFTs (hereinafter referred to as pMOSs). The power supply is directly connected to the drain of these pMOSs. (0008] SSA has two sensing nodes, namely sense amplifier true (SAI) node and sense- amplifier false (SAP) node. The SAT node is coupled to a bit line in a memory, while the SAI node is coupled to FRF I-'. FRFF is directly connected lo sources of ' two pMOSs referring to the first decoupling transistor and the first sampling transistor. FRF. I is shared across all input and output lines (l()s) of the memory. |0009j further, the bit lines in the memory may undergo several levels ol multiplexing to produced multiplexed bit lines which are coupled to the SAI node of the respective SSAs. These bit lines are selected by operating associated pMOSs, which are directly connected to the bit lines, by applying supply voltage from the power supply through CMOS multiplexer drivers. The CMOS multiplexer drivers are directly connected to SREF and therefore, the power supply to the CMOS multiplexer drivers is provided from SREF. Additionally, SREF is directly connected to the second decoupling transistor and the second sampling transistor. The first and the second decoupling transistors are operated by applying a pre-charge ON signal at the gates of the respective pMOSs. The first and the second sampling transistors are operated by applying a pre-charge OFF signal at the gates of the respective pMOSs. These pre-charge ON and pre-charge-OFF signals are generated by a clock generation circuitry of the memory. Also. FREF and SREF' are extended globally and are taken into a control block of the memory Due to availability of space in the control block, large capacitors having high capacitances can be directly connected to FREF and SREF. [00010] In this way, FREF and SREF provide immunity to SNT-SSS from power supply noise. FREF and SRFT: are kept separate to prevent transfer of charge from FRFT: to SREF. or vice versa, due to leakage of charge from FREF and SREF. However, if the leakage of charge from FREF and SREF is appropriately controlled, then a single reference line can be used for reliable operation of SNT-SSS. [00011] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to relerence like features and components. [00012] Fig. 1 illustrates a typical single-ended sensing scheme 100 for a memory [00013] Fig. 2 illustrates an exemplary single-ended sensing scheme 200 for a memory. [00014] Fig. 3 illustrates an exemplary block diagram of a memory chip 300 tor the single-ended sensing scheme 200 in Figure 2. [00015] The disclosed subject matter relates to a single-ended sensing scheme for a memory. More particularly, the subject matter relates to a power supply noise tolerant single-ended sensing scheme. The power supply noise tolerant single-ended sensing scheme can be implemented in a memory, such as a read only memory (ROM), a static random access memory (SRAM), a dynamic random access memory (DRAM), and so mi Devices having the memory that can implement the disclosed write circuitry include., but are not limited to. set-lop boxes. computing devices, televisions, mobile phones, laptops, personal digital assistants (PDAs), and so on. which can be employed in a variety of applications such as streaming, conferencing, surveillance, etc, [00016] The power supply noise tolerant single-ended sensing scheme can be thus advantageously used to prevent unreliable read operation in a memory due to noise from a power supply without compromising on space available on a memory chip Additional!}, the power supply noise tolerant sensing scheme ensures that there is no high power consumption and any unwanted delay during general operation of the sensing scheme. Ex e nip 1 ary ..System s [00017] Fig. 1 illustrates a typical single-ended sensing scheme 100 lor a memory. the single-ended sensing scheme 100 includes one or more primary bit lines. 102-1. 102-2. 102-3. ...102-N and 104-1, 104-2. I04-3....104-N. which are coupled to plurality ol memory cells, and a single-ended sense amplifier (SSA) 106. 'I'he bit lines 102-1, 102-2. 102-3....102-N (hereinafter collectively referred to as bit lines 102) are directly connected to p-channel MOSFI. is 108-1. 108-2. 108-3,...108-N (hereinafter referred to as pMOSs 108) respectively. 1 he bit lines 104-1. 104-2. 1()4-3,...104-N (hereinafter collectively referred to as bit lines 104) are direct!} connected to pMOSs 110-1. 110-2, 1 10-3....I 10-N (hereinafter collectively referred to as pMOSs 110) respectively. The pMOSs 108 and 1 10 behave as pass transistors for selection of the bit lines 102 and 104 respectively. [00018] Further, the bit lines 102 and 104. which can be termed as primary bit lines 102 and 104. undergo a first level multiplexing to produce secondary bit lines l!2-i and 112-2 respectively. The secondary bit line 112-1 is directly connected to a pre-charge device and a pass transistor, which are implemented with the help ot pMOSs i 14 and 1 16 respectively. 1 he secondary bit line I 12-2 is also directly connected to a pre-charge device and a pass transistor. which are implemented with the help of pMOSs 1 18 and 120 respectively. The pMOSs I 14 and I 18 are supplied with a pre-charge ON signal 122. which is a clock signal, at the gates, while a power supply 124 is applied at the drain of the pMOS I 14 and ! 18. I'pon receiving the pre- charge ON signal 122. the pMOS 1 14 and I 18 are activated. Since m the given architecture of the single-ended sensing scheme 100 the bit lines I 12-1 and I 12-2 remain to ground at the starting of a read cycle, therefore, activation of the pMOSs 114 and 118 pre-charges the respective bit lines 112-1 and 112-2 prior to a read operation. The power supply 124 is also applied at the gate of the pMOSs 108. 1 10. I 16. and 120 through a multiplexer driver (not shown in the figure). [00019] Moreover, generally, there is an inherent coupling between the gate of the pMOSs 108-1 and the multiplexed bit line 112-1 through a capacitor 126. while the gate of the pMOS I 10-1 is coupled with the multiplexed bit line 112-2 through a capacitor 128. Also, the secondary bit lines 112-1 and 1 12-2 undergo a second level multiplexing to produce a single bit line 130, which is coupled to the SSA 106. [00020] The SSA 106 is similar to a latch circuit and can be realized with the help of two cross-coupled complementary metal oxide semiconductor (CMOS) inverters. One CMOS inverter is implemented using a pMOS 132 and an n-channel MOSIT. 1 (nMOS) 134. while the other CMOS inverter is implemented using a pMOS 136 and an nMOS 138. Further, the SSA 106 has two input nodes 140 and 142 and two output nodes, or in other words sensing nodes. namely a sense amplifier true (SAT) node 144 and a sense amplifier false (SAF) node 146, The SAT node 144 is coupled to the bit line 130 through a pass transistor, which is implemented using a pMOS 148, while the SAF node 146 is coupled to the power supply 124 through a pass transistor, which is implemented using a pMOS 150. The power supply 124 provides a reference voltage for the voltage on the bit line 130. so that the SSA 106 can determine a differential voltage across the SAT node 144 and the SAF node 146. The SSA 106 is also direct I \ connected to the power supply 124 at the drain of the pMOSs. !32 and I 36. and is grounded through a pass transistor, which can be realized with the help of an nMOS 152 [00021 ] Generally, a clock generation circuitry (not shown in the figure) in the memory alternatively produces four signals, namely, a pre-charge ON signal 122 having a low voltage, a pre-charge OFF signal having a high voltage, a sense ON signal 154 having a high voltage, and a sense OFF signal 156 having a low voltage, and in this order. In operation, the sense-ON signal 154 is applied at the gate of the nMOS 152. while a complementary sense-ON signal, which is equivalent to the sense OFF signal 156. is applied at the gate of the pMOS 150 and 148. When the sense OFF signal 156, which has a logic level zero, activates the pMOSs 148 and 150. Simultaneously, the sense-ON signal 154 activates the nMOS 152. As a result, the sense ampliiier 130 is activated to perform the read operation, lor this, the sense amplifier 130 senses a differential voltage between the bit line 130 and the power supply 124, which is expected to be set at constant voltage, across the SAT node 144 and the SAF node 14