FORM 2
THE PATENTS ACT, 1970 (39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
SWITCHING ELEMENT DRIVING CIRCUIT;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANIZED AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 1008310 JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.

DESCRIPTION
Field
[0001] The present invention relates to a drive circuit for a switching element that executes drive control targeted at a switching element. The type of switching element can include an IGBT (Insulated Gate Bipolar Transistor) and a FET (Field Effect Transistor).
Background
[0002] In recent years, motor controllers have become indispensable because of the widespread use of inverter devices for operating motors at variable speeds. A motor controller includes a power conversion device that converts DC power into AC power or AC power into DC power. The power conversion device uses a switching element such as an IGBT or a MOSFET (Metal-Oxide-Semiconductor FET) and achieves power conversion with the switching element. [0003] The drive circuit for a switching element includes only a gate resistor for VGE charging of the switching element to perform switching of the switching element.
[0004] Switching of the switching element described above is controlled and driven by accumulating or releasing charge in or from a gate terminal in order to charge or discharge a gate-emitter voltage. At that time, however, switching loss occurs due to a gate current IG or a collector current Ic and EMI (Electro Magnetic Interference) noise simultaneously occurs due to the current changing rate di/dt, which depends on the charging time. The switching loss adversely affects peripheral

devices as well as the drive circuit itself. [0005] In order to solve the problem described above, a conventional drive circuit for a switching element is configured to have a circuit for adjusting the switching speed. The switching speed is reduced by this circuit so that any sudden rise of the gate current IG or the collector current Ic is suppressed, and thus the EMI noise is reduced. However, the disadvantage of this operation is the trade-off relation wherein as the switching speed is reduced, the loss in the miller period increases, which means making adjustments is difficult.
[0006] To solve the problems described above, a drive circuit that adjusts the ON/OFF switching timing of a gate (see Patent Literature 1, for example) and a constant-current drive circuit that causes a constant gate current to continuously flow through a gate terminal (see Patent Literature 2, for example) are proposed.
Citation List
Patent Literatures
[0007] Patent Literature 1: Japanese Patent Application
Laid-open No. 2004-253582 (page 1, FIG. 1)
Patent Literature 2: Japanese Patent No. 4954290 (page 13, FIG. 8)
Summary
Technical Problem
[0008] The invention of Patent Literature 1 described above has a problem in that a plurality of drive circuits are provided and the ON/OFF timings of the gates in the respective drive circuits need to be adjusted. In the invention in Patent Literature 2, the switching loss can be decreased without increasing the current changing rate

di/dt. However, there is a problem in that the loss in the miller period is increased because the gate current is caused to continuously flow for a certain time. Furthermore, the inventions described in Patent Literatures 1 and 2 require a complicated circuit and the drive circuit is increased in size due to the increase in the number of constituent parts.
[0009] The present invention has been achieved in view of the above problems, and an objective of the present invention is to provide a drive circuit for a switching element that can reduce switching loss and EMI noise while avoiding the need for the drive circuit to have a complicated configuration.
Solution to Problem
[0010] In order to solve the problem and to achieve the objective mentioned above, the present invention relates to a drive circuit for a switching element that includes a drive-voltage generation circuit that generates a driving voltage for a switching element; and a filter circuit that filters the driving voltage. The filter circuit forms a circuit having a step response represented by a second-order transfer function together with an internal gate resistor of the switching element and an input capacitor between a gate terminal and an emitter terminal of the switching element. The circuit has a circuit constant that is set to make an attenuation coefficient of the transfer function be a value within a certain range.
Advantageous Effects of Invention
[0011] The drive circuit for a switching element according to the present invention can reduce switching loss and EMI noise while avoiding the need for the drive

circuit to have a complicated circuit configuration.
Brief Description of Drawings
[0012] FIG. 1 is a diagram illustrating an example
configuration of a drive circuit for a switching element.
FIG. 2 is a diagram illustrating a drive circuit for a switching element when the input capacitor between the gate and the emitter of the switching element is being charged.
FIG. 3 is a diagram illustrating the drive circuit for a switching element in a miller period.
FIG. 4 is a diagram illustrating an example configuration of a drive circuit for a switching element in a case where the filter circuit is an RC filter.
. FIGS. 5 are explanatory diagrams of an operation of the drive circuit for a switching element.
FIG. 6 is a diagram illustrating an example of step responses of a gate voltage.
Description of Embodiments
[0013] Exemplary embodiments of a drive circuit for a switching element according to the present invention will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments.
[0014] Embodiment
FIG. 1 is a diagram illustrating an example of the circuit configuration of a drive circuit for a switching element according to the present invention. The drive circuit for a switching element (hereinafter, simply "drive circuit") according to an embodiment of the present invention is a circuit that controls a switching element 16 that is a target. Further, the drive circuit includes a control circuit 1, switches 3 and 4, and a filter circuit

20. The switching element 16 is, for example, a power semiconductor element such as an IGBT or a FET. The switching element 16 has a feedback diode 17 connected between a collector 14 and an emitter 15. The switching element 16 also has an internal gate resistor 10, an input capacitor (Cgc) 12 between a gate 11 and the collector 14, and an input capacitor (Cge) 13 between the gate 11 and the emitter 15. The switching element 16 is applied to, for example, a power conversion device such as an inverter. [0015] The control circuit 1 determines whether the switching element 16 is ON or OFF and generates a voltage command (Vref) 2 corresponding to the determined result. The switch 3 is, for example, an NPN transistor and the switch 4 is, for example, a PNP transistor. Bases and emitters of the switches 3 and 4 are connected to each other, and the voltage command Vref 2 is input to both of the bases. The collector of the switch 3 is connected to a positive power source 5 (a positive electrode of a switching-element driving power source (not illustrated)) and the collector of the switch 4 is connected to a negative power source 6 (a negative electrode of the switching-element driving power source (not illustrated)). Together with the control circuit 1, these switches 3 and 4 form a drive-voltage generation circuit 18 that generates a gate voltage 7 that is the driving voltage for the switching element 16 and outputs the generated gate voltage 7. The gate voltage 7 is generated in accordance with the voltage command Vref, which is a pulse signal input from the control circuit 1. For example, when the voltage command Vref is ON (at a level designating ON for the switching element 16), the switch 3 is turned ON and the switch 4 is turned OFF so as to output the potential of the positive power source 5 as the gate voltage 7. When the voltage

command Vref is OFF (at a level designating OFF for the switching element 16), the switch 3 is turned OFF and the switch 4 is turned ON so as to output the potential of the negative power source 6 as the gate voltage 7. The gate voltage 7 is applied to the gate 11 of the switching element 16 via the filter circuit 20. The gate voltage 7 charges the input capacitor (Cge) 13 between the gate 11 and the emitter 15 of the switching element 16 and the input capacitor (Cgc) 12 between the gate 11 and the collector 14 of the switching element 16 so as to cause there to be a conductive state between the collector 14 and the emitter 15.
[0016] FIG. 2 is a diagram illustrating a drive circuit when driving of the switching element 16 is started. When driving of the switching element 16 is started, i.e., when a positive gate voltage 7 (the potential of the positive power source 5) is applied to the gate 11, the input capacitor Cge 13 of the switching element 16 is first charged with the gate voltage 7 as illustrated in FIG. 2. Charging of the input capacitor Cge 13 is performed until voltages on both ends of the input capacitor Cge 13 exceed a threshold voltage at which a collector current starts flowing from the collector 14 to the emitter 15. [0017] FIG. 3 is a diagram illustrating a drive circuit in a miller period after the charging of the input capacitor Cge 13 described above ends. In the miller period after the charging of the input capacitor Cge 13 ends, the flow of the gate current IG into the gate 11 of the switching element 16 becomes constant and a voltage Vce between the collector 14 and the emitter 15 gradually decreases.
[0018] In the drive circuit configured as described above, the internal gate resistor 10 and the input

capacitor Cge 13 of the switching element 16 and the filter circuit 20 are considered as one block 19 so that this block 19 can be handled as a transfer function from the voltage command Vref to the gate 11 of the switching element 16.
[0019] In this example, because the internal gate resistor 10 and the input capacitor Cge 13 of the switching element 16 form a filter, the circuit of the block 19 has a configuration in which filters are connected in series. [0020] The filter circuit 20 is an RC filter including a resistor 21 and a capacitor 22 as illustrated, for example, in FIG. 4.
[0021] In the drive circuit configured as illustrated in FIG. 4, a step response of the block 19 can be expressed by a second-order lag transfer function and can be represented by the following general expression (expression (1)).
G(s)=con2/(s2+2^cons+G)n2) •••(!) [0022] A peak value of the gate current can be adjusted by adjusting the attenuation coefficient £. That is, the EMI noise can be reduced by adjusting the attenuation coefficient £ so as to set the peak value of the gate current smaller. Furthermore, by configuring the circuit of the block 19 so as to include the filter circuit 20, i.e., configuring the circuit of the block 19 so as to have a step response expressed by a second-order lag transfer function, the gate current value in the miller period can be set larger than that in a conventional drive circuit that does not include the filter circuit 20. When the gate current value in the miller period is increased, the miller period is shortened and thus a reduction in switching loss can be realized. It is preferable that the attenuation coefficient £ described above satisfies 0.7<^<1.0. By setting the attenuation coefficient £ to have a value

included in the above range, the EMI noise and the switching noise can be reduced when compared to those of the conventional drive circuit. For this reason, the filter circuit 20 is configured to fall within the coefficient I range described above.
[0023] The voltage command (Vref) 2 and the gate voltage 7 are supplied as pulses. An operation in response to a step input, when set ON, is described for both a case where the present embodiment is applied and a case where the present embodiment is not applied. Each step response in a case where the filter circuit 20 is included (the case where the present embodiment is applied) and a case where the filter circuit 20 is not included is illustrated in FIGS. 5.
[0024] FIGS. 5 are explanatory diagrams of an operation of the drive circuit according to the present embodiment and are timing charts illustrating examples of voltage waveforms and current waveforms of constituent parts of the drive circuit and the switching element 16. The horizontal axis represents the time and the vertical axis represents the voltage value or the current value. FIG. 5(a) illustrates a timing chart of a circuit not including the filter circuit 20, which corresponds to a conventional drive circuit (hereinafter, "conventional circuit"), and FIGS. 5(b) and 5(c) illustrate timing charts of the drive circuit according to the present embodiment. FIG. 5(b) is a timing chart in a case where the filter circuit 20 is configured as illustrated in FIG. 4. FIG. 5(c) is a timing chart in a case where the filter circuit 20 is configured to include two stages of RC filters in series, in which each RC filter includes the resistor 21 and the capacitor 22 illustrated in FIG. 4. When two stages of the RC filters are included in series, the step response of the

circuit of the block 19 is expressed by a third-order lag transfer function. In the conventional circuit not including the filter circuit 20, a circuit corresponding to the block 19 includes a gate resistor and a step response thereof is expressed by a first-order lag transfer function. Hereinafter, for convenience of description, the drive circuit having the configuration illustrated in FIG. 4 is referred to as a "second-order lag drive circuit"; and the drive circuit including the filter circuit 20 configured to include two stages of the RC filters in series, in which each RC filter includes the resistor 21 and the capacitor 22 illustrated in FIG. 4, is referred to as a "third-order lag drive circuit".
[0025] A third-order lag transfer function that gives the step response illustrated in FIG. 5(c) is described below.
[0026] The third-order lag transfer function G(s) is represented by the following expression (2). [0027] [Expression 1]

[0028] A general expression of a third-order lag transfer function G(s) is given by the following expression (3) . [Expression 2]

[0029] In the case of a drive circuit having a step response represented by the expression (3), it is known that no overshoot generally occurs when the condition is true such that Pr is smaller relative to a real part of a conjugate complex number of S2+2 * £ -con+con2. Therefore, a

condition in which no overshoot occurs is given by the following expression (4) and a marginal condition in which no overshoot occurs is given by the following expression (5) .

[0030] On the basis of the expressions (2) to (5) described above, a parameter that causes no overshoot is given by the following expression (6). [0031] [Expression 3]

[0032] When £ and con are eliminated from the expression (6), the following expression (7) is obtained. [0033] [Expression 4]

[0034] By setting kpi and kp2 so as to satisfy the above expression (7), a drive circuit for a third-order lag causing no overshoot is obtained.
[0035] As also described in the descriptions of the second-order lag transfer function, it is preferable that the attenuation coefficient £ satisfies 0.7<^<1.0. Therefore, it is preferable that the attenuation coefficient £ of a third-order lag transfer function satisfies 0. 7<^