SYNTHESIZABLE DLL ON SYSTEM-ON-CHIP Technical Field
The present disclosure relates to emulation of system-on-a-chip (SoC) devices for debugging, and, more specifically, to provide emulation capability for analog delay locked loops on SoCs.
Background
System-On-Chip (SoC) with embedded cores, such as DSP (Digital signal processing) core or ARM (Advanced RISC Machine) core, typically has the capability for emulation. Emulation is a process used in debugging hardware/software interactions or interfaces, as well as debugging software failures. The standard hardware used for this purpose is called emulators. A software tool chain (available from emulator vendor) analyses the HDL (Hardware Description Language) design, synthesizes and optimizes the design. The emulation database thus created is used by a user to emulate his design and verify its functionality by at a much faster pace than the conventional PC (personal computer) based simulators. The emulation hardware engines may have different architectures. Typically they may be FPGA (Field Programmable Gate array), LUT (Look-Up-Table) or high performance CPU (Central Processing Unit) array based structures.
At present, the role of emulation is growing rapidly in the integrated circuit design. Simulation of close to real chip scenarios and timely fixing of design bugs in the design cycle further drives the need for availability of emulation platform at very early stage in the design cycle. Though, the mapping of a design on emulator has many advantages, most important being design speedup yet there are several issues while mapping process of a mixed signal design on a SoC, especially with the analog components such as PLLs (Phase Locked Loops), DLLs (Delay Locked Loops), audio/video DACs (Digital-to-Analog Converters)/ADCs (Analog-to-Digital Converters). The analog components present on the SoC are not synthesizable in the normal emulation flow.
Considering memory architectures such as DDRSDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) standard, where reading a DDRSDRAM memory requires a finite delay on several signals such as clock, data strobes etc. The delay is
provided on these signals by the DDR controller and pad logic architecture present on the chip. However, in case of SoCs delay is inserted by an on chip delay element such as DLL (Delay locked loop). The DLLs, used for such analog applications, are not synthesizable for emulation platforms.
Delays inserted by behavioral statements in HDL (verilog/vhdl) for such analog components are also ignored by emulation synthesis tools. Synthesis tools for emulators may optimize multiple driven or undriven nets. Hence, utmost care is taken while coding HDL as this may lead to deviation from expected behavior. Another possible technique may be the delay is inserted manually in the desired signal path for emulation. But this technique again is not suitable and decreases the efficiency of the emulation platforms.
In certain cases, a digital DLL is used which works on digital locking technique and replaces analog DLLs but again the emulation process is affected by other non synthesizable components like digital phase detectors etc. These implementations also require additional jitter control circuitries, which have no meaning for emulation systems.
Brief Description of the Drawings
The present disclosure explains the various embodiments of the instant disclosure in the following description, taken in conjunction with the accompanying drawings, wherein:
FIGURE 1 illustrates a system-on-a-chip which discloses an integration of analog delay logic and synthesizable delay logic according to an embodiment of the present disclosure.
FIGURE 2 illustrates internal architecture of synthesizable delay logic according to an embodiment of the present disclosure.
FIGURE 3 illustrates the simulation results of the synthesizable delay logic according to the present disclosure.
FIGURE 4 illustrates a flow chart of a method for emulation in a system-on-a-chip according to the present disclosure.
While the disclosure will be described in conjunction with the illustrated embodiment, it will be understood that it is not intended to limit the disclosure to such embodiment. On the contrary, it is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims.
Detailed Description
The embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments. The present disclosure can be modified in various forms. Thus, the embodiments of the present disclosure are only provided to explain more clearly the present disclosure to the ordinarily skilled in the art of the present disclosure. In the accompanying drawings, like reference numerals are used to indicate like components.
The present disclosure describes a system-on-a-chip (SoC) used for debugging the hardware/software interaction. The system-on-a-chip (SoC) includes an analog delay locked loop module configured with a synthesizable delay logic module in parallel. Inputs of the analog delay locked loop module and synthesizable delay logic module are coupled with each other. Further, selection logic is provided to select any one of the module at a time.
Another embodiment of the present disclosure illustrates, system-on-a-chip comprising: an analog delay locked loop module; a synthesizable delay logic module having its input coupled to the input of said analog delay locked loop module; and a selection logic operatively coupled to the output of said analog delay locked loop module and synthesizable delay logic module configured to provide required one of said outputs. Further, the synthesizable delay logic comprises a plurality of delay gates coupled in front-to-back arrangement and the outputs of the delay gates are coupled to a multiplexer. The selection line of the multiplexer is programmed to select the required outputs of the gates.
Another embodiment of the present disclosure illustrates, a DDRSDRAM memory comprising: an analog delay locked loop module; a synthesizable delay logic module having its input coupled to the input of said analog delay locked loop module; and a selection logic operatively coupled to the output of said analog delay locked loop module and synthesizable
delay logic module configured to provide required one of said outputs. Further, the synthesizable delay logic comprises a plurality of delay gates coupled in front-to-back arrangement and the outputs of the delay gates are coupled to a multiplexer. The selection line of the multiplexer is programmed to select the required outputs of the gates.
Another embodiment of the present disclosure illustrates, a method for emulation in a system-on-a-chip comprising: providing an analog delay locked loop module; providing a synthesizable delay logic module; and selecting said analog delay locked module during normal operation and said synthesizable module during emulation.
Figure 1 illustrates a system-on-a-chip which discloses an integration of analog delay logic and synthesizable delay logic according to an embodiment of the present disclosure. An analog delay logic module represented as 101 is coupled in parallel to synthesizable delay logic module represented as 102. The data strobe signal coming from memory is made as a common input to both analog delay logic module and synthesizable delay logic module. Further, the outputs of the analog delay logic module and synthesizable delay logic module are multiplexed as an input to selection logic represented as 103. The selection logic 103 is a type of 2-in-l multiplexer. The select pin or mode pin of the multiplexer is programmed to function accordingly.
Figure 2 illustrates internal architecture of synthesizable delay logic according to an embodiment of the present disclosure. The synthesizable logic 102 is a chain of delay gates (or D Flip-Flops) 201, coupled in a cascade mode (or in front-to-back arrangement). The output of each delay gates are further multiplexed to a multiplexer 202. The selection line of the multiplexer is programmed to select the required output from the delay gates.
Further, the present disclosure provides a required controllable delay to the strobe signal (from the memory) with respect to the clock while performing emulation. In the present architecture, the synthesizable delay logic 102 is configured in parallel with analog delay logic 101 and is programmed respectively to provide delay solutions for emulation platforms. In addition to this, the real silicon continues to use analog DLL for other functions because of its inherent stability and accuracy. The present synthesizable delay logic accepts an input signal which passes through a chain of D flip flops (i.e. shift register) and is delayed by specific number
of clock cycles (m). The required delay in number of clock cycles (m) is controlled by a DLLPRGSEL signal (DLLPRGSEL is a signal which specifies the amount of delay required in terms of clock cycles on the input signal). For example, if we use an 'n' bit shift register along with a multiplexer, the maximum delay is 'n' clock cycles and minimum delay is zero. The signal is delayed at various tap points in the circuit and is available at the multiplexer input. The selection of the multiplexer is done by programming input bits depending on the value ofDLL_PRG_SEL.
According to the present disclosure, the pin details of synthesizable delay logic are mentioned in the following Table 1. There are four input pins namely DLLCLK, DLLSIGIN, DLL_RESETN, DLLPRGSEL [4:0], and one output signal DLL_SIGOUT. The input pin DLLCLK receives clock input. The input pin DLLSIGIN receives the signal which is to be delayed. The input pin DLLRESETN receives an active low signal to reset the design. The input pin DLLPRGSEL is a delay select line. The pin DLLSIGOUT provides the final output as a delayed signal.
TABLE 1

(Table Removed)
According to the present disclosure, the delay values for pin DLLPRGSEL of synthesizable delay logic are mentioned in the following Table 2.
TABLE 2

(Table Removed)
Figure 3 illustrates the simulation results of the synthesizable delay logic according to an embodiment of the present disclosure. The present design maintains output signal at zero till the reset signal (DLLRESETN) is deasserted. When the design clock is in running state and DLL_RESETN is in deasserted state, then the DLLPRGSEL value is at "00" state. DLL_SIGOUT follows the DLL_SIGIN without any delay as shown in Region 301. When the DLL_PRG_SEL value is switched to "01" then the DLL_SIGOUT, being a function of DLLSIGIN, is delayed by one clock cycle as shown in Region 302. When the DLLPRGSEL value is switched to "04" then the DLLSIGOUT is a function of DLL_SIGIN is delayed by 4 clock cycles as shown in Region 303. Hence, when the DLLPRGSEL signal value is 'k' in hexadecimal, then the output signal DLLSIGOUT, being a function of input signal DLLSIGIN, is delayed by 'k' clock cycles.
Embodiments of the method for emulation in a system-on-a-chip are described in Figure 4. The methods are illustrated as a collection of blocks in a logical flow graph, which represents a sequence of operations that can be implemented in hardware, software, or a combination thereof. The order in which the process is described is not intended to be construed as a limitation, and any number of the described blocks can be combined in any order to implement the process, or an alternate process.
Figure 4 illustrates a flow chart of a method for emulation in a system-on-a-chip according to an embodiment of the present disclosure. The step 401 provides an analog delay locked loop module. The step 402 provides a synthesizable delay logic module. And the step 403
states selection of said analog delay locked module during normal operation and said synthesizable module during emulation.
The present disclosure provides an emulator mapping process for the SoC. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence helps in reducing overall project cycle time. The design is fully digital and fully synthesizable. The total delay available is controllable by run time command (programming bits) and granularity (minimum delay) is controllable by clock frequency change which is also under user control for emulation systems.
The present disclosure is applicable to various kinds of electronic architectures for improving the function and performance of conventional analog DLLs. Analog DLLs have been proposed for various types of memories and circuits. Such DLLs are used for various applications like clock recovery, synchronizing the data from memory with system clock etc.
The present disclosure is applicable to all types of on-chip and off chip memories used in various in digital electronic circuitry, or in hardware, firmware, or in computer hardware, firmware, software, or in combination thereof. Apparatus of the present disclosure can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and methods actions can be performed by a programmable processor executing a program of instructions to perform functions of the present disclosure by operating on input data and generating output. The present disclosure can be implemented advantageously on a programmable system including at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language or in assembly or machine language, if desired; and in any case, the language can be a compiled or interpreted language.
Suitable processors include, by way of example, both general and specific microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data file; such devices include magnetic disks and cards, such as internal hard disks, and removable disks and cards; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of volatile and
non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; CD-ROM and DVD-ROM disks; and buffer circuits such as latches and/or flip flops. Any of the foregoing can be supplemented by, or incorporated in ASICs (application-specific integrated circuits), FPGAs (field-programmable gate arrays) and/or DSPs.
It will be apparent to those having ordinary skill in this art that various modifications and
variations may be made to the embodiments disclosed herein, consistent with the present
disclosure, without departing from the spirit and scope of the present disclosure.
Other embodiments consistent with the present disclosure will become apparent from
consideration of the specification and the practice of the description disclosed herein.
Although the instant disclosure has been described in connection with the embodiment of the present disclosure illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the disclosure.

We claim:
1. A system-on-a-chip comprising:
an analog delay locked loop module;
a synthesizable delay logic module having its input coupled to the input of said analog delay locked loop module; and
a selection logic operatively coupled to the output of said analog delay locked loop module and synthesizable delay logic module configured to provide required one of said outputs.
2. The system-on-a-chip as claimed in claim 1, wherein said selection logic is a multiplexer.
3. The system-on-a-chip as claimed in claim 1, wherein said synthesizable delay logic comprises:
a plurality of delay gates coupled front-to-back; and
a multiplexer coupled to the output of said each delay gate.
4. The system-on-a-chip as claimed in claim 2 and 3, wherein said multiplexer has a selection line bus signal coupled to a programmed signal.
5. A DDRSDRAM memory comprising:
an analog delay locked loop module;
a synthesizable delay logic module having its input coupled to the input of said
analog delay locked loop module; and
a selection logic operatively coupled to the output of said analog delay locked loop
module and synthesizable delay logic module configured to provide required one of
said outputs.
6. The memory as claimed in claim 5, wherein said selection logic is a multiplexer.
7. The memory as claimed in claim 5, wherein said synthesizable delay logic comprises:
a plurality of delay gates coupled front-to-back; and
a multiplexer coupled to the output of said each delay gate.
8. The memory as claimed in claim 6 and 7, wherein said multiplexer has a selection line bus signal coupled to a programmed signal.
9. A method for emulation in a system-on-a-chip comprising:
providing an analog delay locked loop module;
providing a synthesizable delay logic module; and
selecting said analog delay locked module during normal operation and said synthesizable
module during emulation.
10. A system-on-a-chip substantially as herein described with reference to and as illustrated in the accompanying drawings
11. A DDRSDRAM memory substantially as herein described with reference to and as illustrated in the accompanying drawings
12. A method for emulation in a system-on-a-chip substantially as herein described with reference to and as illustrated in the accompanying drawings