Claims:
1. A MTP (Multiple-Time Programmable) memory using an OTP (One-Time Programmable) memory array for functioning as an MTP memory, the MTP comprising:
storing, by an OTP memory (102), a single bit of input data;
storing, by at least a single bit of count register (200), a program count each time when starting a new count of programming the OTP memory (102) and a block size;
generating, by the OTP memory (102), a block address bit based on count stored in the count register (200), and an input address to access different blocks of the OTP memory (102);
identifying, by the OTP memory (102), bits of the input data failed while storing; and
storing, by the OTP memory (102), the bits of the failed input data into previous block redundant OTP memory as a backup data.

2. The method as claimed in claim 1, wherein the block address is generated by adding the address bit requested with an offset of block size multiplied by the count number.

3. The method as claimed in claim 1, wherein identifying the failed input data includes comparing the stored input data with the failed input data stored as the back-up data in the OTP memory array.

4. The method as claimed in claim 1, wherein the single bit of the input data is stored by selecting at least two memory cells.

5. A system to function as an MTP (Multiple-Time Programmable memory, the system comprising:
a processor (602); and
an MTP memory operatively connected to the processor (602), the MTP memory comprising:
at least a single bit of count register (200) configured to store a program count and a block size; and
an OTP (One-Time Programmable) memory (102) having a plurality of OTP blocks, wherein the OTP memory (102) is configured to:
store a single bit of input data;
generate a block address bit based on count stored in the count register, and an input address to access different blocks of the OTP memory;
identify bits of the input data that failed while storing in the OTP memory; and
store the bits of the failed input data into previous block redundant OTP memory as a backup data.

6. The system as claimed in claim 4, wherein the count register (200) is programmed at least once to store the program count each time when starting a new count of programming the OTP memory array.

7. The system as claimed in claim 4, wherein the OTP blocks are of a fixed size.
, Description:FORM – 2

THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003

COMPLETE SPECIFICATION
(SEE SECTION 10, RULE 13)

SYSTEM AND METHOD FOR A RELIABLE MTP USING OTP MEMORIES

BHARAT ELECTRONICS LIMITED

WITH ADDRESS AT OUTER RING ROAD, NAGAVARA,
BANGALORE,
KARNATAKA, 560045

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED 

TECHNICAL FIELD
[0001] The present invention relates generally to programmable memory devices. The invention, more particularly, relates to a system and method for an MTP (Multiple-Time Programmable) using OTP (One-Time Programmable) memories.
BACKGROUND
[0002] One-Time Programmable, memory is a device that can be programmed once and only once. The OTP can be a fuse that has low resistance state initially to be programmed into a high resistance state. The OTP can be an anti-fuse that has high resistance state initially to be programmed into a lower resistance state. The OTP can also be a charge-trapping device. By determining certain parameters about whether there is sufficient charge stored in a floating gate or oxide/nitride spacer, a proper initial and programmed state can be determined. The fuse can be an interconnect fuse, such as silicided polysilicon, metal, or metal-gate fuse, or a contact/via fuse. The anti-fuse can be a gate-oxide breakdown fuse in a MOS or dielectric breakdown fuse between two conductors.
[0003] There are many applications that require a memory can be programmed a few times, from two times to several hundred times, called MTP, Multiple-Time Programmable memory. This kind of device typically falls between one-time OTP and 10K times programmable memory, such as a flash memory. The process requirements for MTP are also different from OTP and flash memory.
[0004] Normally, in fabrication, MTP can allow adding one or two more masks, while OTP requires zero add-on mask and flash memory can allow adding at least 7-8 masks over the standard logic processes. An OTP memory can be used to implement an MTP memory. Such as a memory can be referred to as a MTP. By using N OTP cells as one MTP cell, each MTP cell can be programmed N times by programming into the different OTP cells each time in the MTP cell. Alternatively, N OTP memories can be used as one N-time programmable MTP by programming into different OTP memory each time.
[0005] There are many conventional solutions that exist to access OTP memory to emulate an MTP memory.
[0006] For example, one of the conventional solutions is proposed in US9824768B2 titled “Integrated OTP memory for providing MTP memory” discloses an integrated One-Time Programmable (OTP) memory to emulate an Multiple-Time Programmable (MTP) memory with a built-in program count tracking and block address mapping is disclosed. The integrated OTP memory has at least one non-volatile block register and count register to respectively store block sizes and program counts for different block/count configurations. The count register can be programmed before each round of programming occurs to indicate a new block for access. The integrated OTP memory also can generate a block address based on values from the count and block registers. By combining the block address with the lower bits of an input address, a final address can be generated and used to access different blocks (associated with different program counts) in the OTP memory to mimic an MTP memory.
[0007] Figure 1 shows a block diagram of a portion of a conventional MTP system. The MTP system includes a MTP memory built into an OTP memory array 100 having 4 blocks of 256 B (Bytes) each block denoted 101 through 104, respectively. The first time to program an OTP is to program into the block 0, 101. The second time is to program into the block 1, 102, and so on. In such OTP memory, one bit of data is stored in one memory cell, and the one memory cell is accessed during a read operation to read out the bit of data stored therein. There is a probability that data may not be programmed to the cells, resulting in failure to program the data. In such a situation, the OTP memory has failed. In a more problematic scenario, the data may not be properly programmed to the cells because the cell is “weak” or “slow”, meaning that a cell thought to have been programmed with one logic state could be read out to have the opposite logic state. This can cause malfunction of the system relying on the stored data.
[0008] In the case of a single OTP array, the manufacturer of the memory may encounter defects that make the device useless. This will reduce manufacturing yield, and increase costs. In the case of an MTP memory with OTP cells, the programming has to be carried over to the newer block with the same programming data. Therefore, there is a need to improve the reliability of OTP memories.
[0009] A control system is responsible to keep track of program counts by software or hardware and generating proper addresses to select the suitable blocks in the OTP memory array 100 for access.
[0010] Thus, there is a need for a system and method to improve the reliability of OTP memories.
SUMMARY OF THE INVENTION
[0011] This summary is provided to disclose a system and method for a reliable MTP using OTP memories. This summary is neither intended to identify essential features of the present invention nor is it intended for use in determining or limiting the scope of the present invention.
[0012] For example, various embodiments herein may include one or more systems and methods for a reliable MTP using OTP memories.
[0013] In an embodiment, the present invention describes an MTP (Multiple-Time Programmable) memory using an OTP (One-Time Programmable) memory array for functioning as an MTP memory. The method comprising storing, by an OTP memory, a single bit of input data. The method further includes storing, by at least a single bit of count register, a program count each time when starting a new count of programming the OTP memory and block size. The method further includes generating, by the OTP memory array, a block address bit based on count stored in the count register, and an input address to access different blocks of the OTP memory. The method further includes identifying, by the OTP memory array, bits of the input data failed while storing, and storing, by the OTP memory array, the bits of the failed input data into the previous block redundant OTP memory. The failed input data is stored a back-up data in the OTP memory.
[0014] In another embodiment, the present invention describes a system to function as an MTP (Multiple-Time Programmable memory. The system comprises a processor and an MTP memory operatively connected to the processor. The MTP memory further comprising at least a single bit of count register configured to store a program count and a block size. The MTP memory of the system further includes an OTP (One-Time Programmable) memory having a plurality of OTP blocks, wherein the OTP memory is configured to store a single bit of input data. The OTP memory further generates a block address bit based on the count stored in the count register, and an input address to access different blocks of the OTP memory. The OTP further identifies bits of the input data that failed while storing in the OTP memory, and stores the bits of the failed input data into previous block redundant OTP memory.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0015] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
[0016] Figure 1 illustrates a block diagram depicting a block diagram of a portion of a conventional MTP system, according to an embodiment of the present invention.
[0017] Figure 2 illustrates a schematic diagram depicting a count register associated with 256 B block of 4-time programmable, according to an exemplary implementation of the present invention.
[0018] Figure 3 illustrates a schematic block diagram depicting the finding of the latest block number, according to an embodiment of the present invention.
[0019] Figure 4 illustrates a schematic diagram depicting a block diagram of an MTP with an OTP memory array, registers, and control logic, having 4 blocks of 256 B memory, according to an embodiment of the present disclosure.
[0020] Figure 5 illustrates a schematic diagram of OTP with multiple bit cells which will be used for storing the redundant data, according to an exemplary implementation of the present invention.
[0021] Figure 6 illustrates a schematic diagram shows a block diagram of an SoC using an MTP memory, according to an exemplary implementation of the present invention.
[0022] Figure 7 illustrates a schematic diagram depicting a flow chart to start a new count of programming in an MTP memory, according to an exemplary implementation of the present invention.
[0023] Figure 8 illustrates a schematic diagram depicting a flow chart to read MTP memory, according to an exemplary implementation of the present invention.
[0024] Figure 9 illustrates an MTP (Multiple-Time Programmable) memory using an OTP (One-Time Programmable) memory array for functioning as an MTP memory, according to an exemplary implementation of the present invention.
[0025] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in a computer-readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION
[0026] The various embodiments of the present invention disclose a system and method for improving the reliability of OTP memories and using the OTP (One-Time Programmable) memories to emulate a MTP (Multiple-Time Programmable). This makes use of a built-in program counter and block address mapping is based on the count value. The count register can be programmed before each round of programming occurs to access a new block. The reliability of the values programmed in the new blocks for access due to defective or weakly programmable cells is compensated by making use of programming in the newer block of the MTP memory with the previous block also being valid so that a single bit gets stored in multi cell thereby providing redundancy. The novel aspect of the present invention is the use of the previously programmed blocks to ensure redundancy. Program reliability is ensured by programming the data one bit at a time and verifying all the programmed bits in a single-ended read mode. By updating the block count value the block address and the final address can be generated and accessed for the different blocks. The method for using a count register and the access to generate the final address based on the count register is also discussed.
[0027] In the following description, for purpose of explanation, specific details are outlined to provide an understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without these details. One skilled in the art will recognize that embodiments of the present disclosure, some of which are described below, may be incorporated into a number of systems.
[0028] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the present disclosure and are meant to avoid obscuring the present disclosure.
[0029] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0030] In an embodiment, the present invention discloses a method and system for improving the reliability of OTP memories and using the OTP memories to emulate an MTP. This makes use of a built-in program counter and block address mapping is based on the count value. The count register is programmed before each round of programming occurs to access a new block. The reliability of the values programmed in the new blocks for access due to defective or weakly programmable cells is compensated by making use of programming in the newer block of the MTP memory with the previous block also being valid so that a single bit gets stored in multi-cell thereby providing redundancy.
[0031] The system further uses the previously programmed blocks to ensure redundancy. Program reliability is ensured by programming the data one bit at a time and verifying all the programmed bits in a single-ended read mode. By updating the block count value the block address and the final address can be generated and accessed for the different blocks. The method for using a count register and the access to generate the final address based on the count register is also disclosed.
[0032] In an exemplary implementation, the present invention discloses a method to use a portion of OTP memory with different blocks for different program counts to operate like an MTP memory.
[0033] In another embodiment, the present invention discloses a system that uses automatic address generation to access different blocks in the OTP memory. A portion of OTP memory can be divided into many blocks associated with different program counts. There can also be circuitry to generate a block address based on program counts. The block address together with the lower bits in an input address can be used to generate a final address to access the OTP memory accordingly as the latest data that has been programmed.
[0034] In another embodiment, the present invention discloses a system that includes an MTP memory that uses an OTP memory array to function as an MTP memory having a plurality of OTP blocks, wherein the OTP blocks are of a fixed size. The system further includes an SoC, comprising a processor and an MTP memory. The MTP memory includes an OTP array having a plurality of OTP blocks. The system further includes a single bit of the count register programmed at least once to store the program count each time when starting a new count of programming the OTP array, wherein the block size of each OTP block is of a fixed size. The system further includes a control logic executing a programming operation.
[0035] In another exemplary implementation, the present invention discloses a method for programming one-time programmable (OTP) memory cells comprising programming input data and identifying bits of the input data which has failed to program by verifying the programmed data and reprogramming the failed bits. The method further includes identifying if at least one bit has failed the reprogramming by reading verifying the reprogrammed data.
[0036] In another exemplary implementation, the present invention discloses identifying includes impeding bits of the input data which passed programming from further programming by reading verifying the programmed data. The method further includes the input data and reprogrammed data are compared for identifying the failure of the reprogrammed data with input data. The method further includes programming a single bit of input data by selecting at least two memory cells. The redundancy of a single bit data stored in more than one bit cell takes care of failure due to a weak or slow programmed cell. The method also includes a read operation carried out by reading a single bit of data stored in at least two OTP memory cells.
[0037] In another exemplary implementation, the present invention discloses the block address is generated by adding the address bit requested with an offset of block size multiplied by the count number.
[0038] In another exemplary implementation, the present invention discloses identifying the failed input data includes comparing the stored input data with the stored failed input data as a back-up data in the OTP memory array.
[0039] In another exemplary implementation, the present invention discloses the single bit of the input data is stored by selecting at least two memory cells.
[0040] In another embodiment, an illustrative purpose as to exemplify the key conceptions of the present invention is disclosed. The OTP memory consists of a plurality of MTP memories. Programming the count register is performed by programming a bit in the count register each time starting a new count of programming. Converting the count register into a block address is achieved by adding all bits or by finding the first 0 in the location of bit stream. The count register is any stand alone non-volatile register or is built into the OTP memory array.
[0041] In another embodiment, the present invention discloses a count register programmed at least once to store the program count each time when starting a new count of programming the OTP memory array.
[0042] In another embodiment, the object of the present invention to mitigate the disadvantage of failure of an OTP memory is disclosed. The present invention also discloses the usage of an OTP memory array to emulate an MTP. The MTP uses a block count register to allow programming to blocks of OTP for an MTP. The programming and read access are dependent upon the latest block count of the block count register to access the latest block of the OTP array. The correct data access is taken care of by making use of redundant storage of data in the previous block with respect to the latest block of an OTP array.
[0043] Figure 1 illustrates a block diagram depicting a portion of a conventional MTP system, according to an embodiment of the present invention.
[0044] In Figure 1, a portion of a conventional MTP system (100) is disclosed. The MTP system (100) includes an MTP memory built into the OTP memory array (102) having 4 blocks of 256 B (Bytes) each block denoted through 104-110, respectively. The first time to program an OTP is to program into the block 0 (104). The second time is to program into block 1 (106), and so on. A control system is responsible to keep track of program counts by software or hardware and to generate proper addresses to select the suitable blocks in the OTP memory array (102) for access.
[0045] The OTP memory (102) has a 1 KB MTP memory that is configured as 4 blocks of 256 B OTP memory (104) through 110. Each count of programming will start from block (104) through the block (110) up to 4 times. This is scaled accordingly to bigger OTP arrays with fixed block size. For example, a 2KB MTP memory can be configured as 8 blocks of 256B OTP memory.
[0046] Figure 2 illustrates a schematic diagram depicting a count register associated with 256 B block of 4-time programmable, according to an exemplary implementation of the present invention.
[0047] In Figure 2, a count register (200) is associated with 256 B block of 4-time programmable OTP.
[0048] In Figure 2, the count registers are configured to store the program counts, i.e. count=1 and count=3, corresponding to the latest block addresses 0 and 2 respectively. The count register (200) is a non-volatile register, a stand-alone OTP register, or an OTP cells integrated into the OTP array (102). The entire MTP (100) is to be read to check if there are any defects before being used. Then, when a new program count starts, at least one bit in the count register (200) is programmed, from the lowest to highest bits, before any actual programming happens. The register can be non-volatile registers so that the configuration can be programmed only once before the MTP can be used for each new count of programming.
[0049] However, there can be some volatile registers to be read as the counterpart of the nonvolatile registers upon powering up or chip selecting, or triggering by a signal. The volatile registers can be set to any value so that each block in the MTP memory can be read arbitrarily. This feature allows checking if all blocks are all 0s before any programming and reading past programmed data for testability considerations.
[0050] Figure 3 illustrates a schematic block diagram (300) depicting the finding of the latest block number, according to an embodiment of the present invention.
[0051] In Figure 3, finding the latest block number is disclosed. The count register (200) is associated with the 256 B block of 4-time programmable filled with 1's. Since the count register (200) is filled with three 1's consequently in block (302), block (304), and block (306), the block count number becomes 2 (3-1). The access of the latest block with respect to programming or reading access is with respect to block number 2.
[0052] Figure 4 illustrates a schematic diagram depicting a block diagram of an MTP with an OTP memory array, registers, and control logic, having 4 blocks of 256 B memory, according to an embodiment of the present disclosure.
[0053] In Figure 4, the MTP (100) with the OTP memory array (102), registers (200), and control logic, having 4 blocks of 256 B memory (102), and a Block address generator (404) configured to generate address based on the count register (200) are disclosed. The count register (200) is programmed into the 0th bit before or after the first round of programming and the 1 bit before or after the second round of programming and so on. The program count is generated by adding all bits in the count register (200) together (assuming the programmed bits are 1s and un-programmed bits are 0s), or by finding the first 0 in the bit location in the count register, starting from the lowest bit.
[0054] For example, there are three programmed bits 300 so that the total number of 1's is 3. Another way to generate program count is to find the first 0 in the bit location starting from the bit position 0. Since the block address starts from 0, the program count 3 corresponds to the block address 3−1=2 (shown in Fig. 3). The block address is used as upper bits in a final address to generate access to the respective OTP block accordingly.
[0055] Firstly, the count register 200 is checked. If the count register 200 is all 0s, this indicates a blank MTP before any use. Reading the MTP will proceed to read blank data (i.e. all 0s) in the 1 KB OTP memory (102). Before the first count of programming starts, bit location 0 (306) in the count register (200) is programmed. The count register reads accordingly. The new count register has only one 1 to indicate the block address is 0 so that all programming occurs in the block 0 together with the lower bits in the input address to access any bits in the block 0. When reading the MTP after the first count of programming is finished, the count register is read as 1 to indicate a block address 0 so that reading bits within the block 0 and using the lower bits in the input address to read any bits within the block 0. In the second count of programming, the bit location 1 (304) in the count register (200) is programmed and the subsequent programs or read will use the block 1 for access with the block 0 used to provide inherent redundancy. This subsequently follows for the third level of programming with programming or read from block 2 and the redundancy provided by the block 1.
[0056] Figure 5 illustrates a schematic diagram of OTP with multiple bit cells which will be used for storing the redundant data, according to an exemplary implementation of the present invention.
[0057] In Figure. 5 the OTP with multiple bit cells is used for storing the redundant data. Here, for example, first-bit cell (504), second-bit cell (506), third-bit cell (508), and fourth-bit cell (510) are considered. The access of the data is done using word lines and bit lines selected using the controller. The value fetched from these bit cells is finally given as data by a sense amplifier (502).
[0058] A memory controller of the MTP system (100) is responsible for selecting the various word lines and bit lines for doing the necessary programming and read access. For example, two cells 504 and 508 connected to one bit line BL2, while the other two cells such as cells 506 and 510 connected the other bit line BL1. In particular, if the bit cell 504 has stored the value of '0' previously and if a value of '0' is required, there is no need for programming 508. The sense amplifier 502 gives a value with data '0'. If the cell 504 has stored a value of '1' and if there is a value of '0' required. Then the cell 506 will be programmed with the same voltage level as 504 which will make the sense amplifier 503 return a value of '0'. In case bit cell 504 has got a value of '0' stored in it and we require a value of '1', then the bit cells 504 and 508 will be programmed with a value of '1', so even in the case of weakly programming or slow charging of one of the cells, the other cell takes care of this which will make the sense amplifier (502) return a value of '1'. In case bit cell 504 has got a value of '1' stored in it and we require a value of '1', then the bit cell 508 will be programmed with a value of '1' which will again make the sense amplifier (502) return a value of '1'.
[0059] Figure 6 illustrates a schematic diagram shows a block diagram of an SoC using an MTP memory, according to an exemplary implementation of the present invention.
[0060] In Figure 6, a SOC architecture is disclosed. The SOC architecture includes an MTP memory (100), such as a plurality of OTP memory cell in at least one OTP memory array(102). The SoC further includes a processor (602) configured to communicate through a common bus interface i.e. interconnect (604) to various memory and peripheral devices such as I/O interfaces (606), serial interfaces (612), high-speed interfaces (614), and other memory (610). The other memory (610) is a conventional memory such as DRAM, SRAM, or flash that can interface to the processor (602) through a memory controller. The processor (602) generally is a microprocessor, a digital signal processor, or other programmable digital logic devices. Memory is constructed as an integrated circuit, which includes at least one memory array and at least one OTP memory (102) for building the MTP memory (100). The MTP memory (100) is configured to interface to the processor (602) through a memory controller that is used for a secure boot application process. In normal scenarios, if only a 256B OTP memory is present and there is a failure of programming the keys in the OTP array will lead to complete failure of the SoC during secure boot, which cannot be re-programmed again.
[0061] In case of the MTP, the SOC consisting of a 1KB OTP array, can be split up into four 256B MTP memory. Even with the failure of a single bit of block 1 of an OTP of 256B consisting of the key, block 0 will be used to provide the redundant data for the failed bit. This secure boot application will then use the keys without any failures from the OTP memory for booting. The memory controller using the redundancy programming logic can be implemented and integrated in the SoC.
[0062] Figure 7 illustrates a schematic diagram (700) depicting a flow chart to start a new count of programming in an MTP memory, according to an exemplary implementation of the present invention.
[0063] At step 702, the procedure starts when a user is ready to write data into a memory when the OTP memory is checked for all blanks and the program supply voltages are properly setup. At step 704, check whether the program count exceeds a limit. If yes, the programming can't be done so it is stopped 706. If not, program the count register (200) at step 708. In the next step 710, read the updated count register (200). At step 712, find the count number. At step 714, generate the final address bit by adding the address bit requested with the offset of block size multiplied by the count number. At step 716, program the data into the final address generated. At step 718, read verify to check if data have been programmed in the next step. At step, 720 program the data (as backup data) into the previous block redundant OTP memory to maintain the integrity of the programmed OTP memory in case of failures due to hardware. At step 722, check if all data are programmed. If not, at step 726, ready to program the next address, otherwise the programming stops 724.
[0064] Figure 8 illustrates a schematic diagram depicting a flow chart to read MTP memory, according to an exemplary implementation of the present invention.
[0065] In Figure. 8, a flow chart 800 depicting a method for reading data in an integrated MTP (100) is disclosed. At step 802, the procedure starts when a user is ready to read data from a memory. At step 804, read the count register (200) data. Then, at step 806, check if all bits in the count register are all zero. If yes, in the next step 808, read the OTP memory with the input address and check if more data is to be read. If not, at step 810, find the latest count number in the count register. In the next step 812, use the count number to generate the final block address. The final block address is generated by combining the block address with the lower bits in the input address. At step 814, read the MTP with the final address generated accordingly. At step 816, check if all data have been read. If not, at step 820, ready to read the next input address or otherwise stop reading data (step 818). The memory controller is responsible for selecting the various word lines and bit lines for doing the necessary programming and read access.
[0066] Figure 9 illustrates an MTP (Multiple-Time Programmable) memory using an OTP (One-Time Programmable) memory array for functioning as an MTP memory, according to an exemplary implementation of the present invention.
[0067] Referring now to Figure 9 which illustrates a flowchart (900) of the MTP (Multiple-Time Programmable) memory using the OTP (One-Time Programmable) memory array for functioning as the MTP memory, according to an exemplary implementation of the present invention. The flow chart (900) of Fig. 9 is explained below with reference to Fig. 7 as described above.
[0068] At step 902, storing, by an OTP memory, a single bit of input data.
[0069] At step 904, storing, by at least a single bit of count register, a program count each time when starting a new count of programming the OTP memory and block size.
[0070] At step 906, generating, by the OTP memory array, a block address bit based on count stored in the count register, and an input address to access different blocks of the OTP memory.
[0071] At step 908, identifying, by the OTP memory array, bits of the input data failed while storing, and
[0072] At step 910, storing, by the OTP memory array, the bits of the failed input data into previous block redundant OTP memory as a backup data.
[0073] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to a person skilled in the art, the invention should be construed to include everything within the scope of the invention.