DESC:TECHNICAL FIELD
[0001] The present disclosure relates generally to a communication system. The disclosure more particularly relates to a UART (Universal Asynchronous Receiver Transmitter) in the communication system.
BACKGROUND
[0002] Various interface technologies such as UART (Universal Asynchronous Receiver Transmitter), SPI, I2C, etc., have been developed to communicate between electronic devices over many years. The UART interface technology i.e., the UART is mostly used in the embedded systems for communicating with a microcontrollers/PC to implement functions such as monitoring, debugging, because of its simple structure and easy use. In UART the data is serially transmitted and received from one device to another.
[0003] In systems where multiple processors are utilized, there is a requirement for communication with each of these processors from an external PC or command centre for user interaction, configuring settings, and debugging. UART is commonly used for this purpose. However, when there are numerous processors in a system, accommodating physical UART lines for each one becomes a constraint, leading to increased cabling and space requirements within the system. Consequently, there is a need for a system that simplifies and provides a solution to this issue.
[0004] In this proposed system, a single UART terminal is connected to multiple UART terminals via an onboard switching circuit. Typically, in such systems, users must physically switch to each terminal for selection, often using jumpers, additional circuitry, or select signals, which required additional human intervention.
[0005] US patent no. 10,785,063 B2 dated September 22, 2020, proposes a method for variably changing a communication speed by a first device when a high-speed communication request within a range supported by the first device is input from a second device during low-speed communication of the first device with a third device in the UART communication and performing data communication. This disclosure is for selecting the baud rate automatically based on the incoming baud rate with a circuitry and switching to the detected baud rate. However, this disclosure is about switching the baud rate and not about switching between multiple UART terminals.
[0006] US patent publication no. 2016/0246570 A1 dated Aug 25 2016 discloses a line multiplexed UART interface that multiplexes a UART transmit and CTS functions on a transmit pin and multiplexes a UART receive and RTS functions on a receive pin. This method reduces the conventional need for an additional RTS pin and additional CTS pin. However, in this method, additional signal lines, RTS, and CTS are used for selection. These lines may not be available in all the UART interfaces.
[0007] US patent no. 4,325,147 dated April 13, 1982 proposes an asynchronous multiplex system allows full duplex communication between a plurality of terminals each provided with a universal, asynchronous receiver-transmitter (UART) which serially receives data information from a source thereof and is operative to produce a flag Signal indicating that all of the bits of a data word have been received for storage and are ready for transmission. In this multiple UART terminals are combined and their terminal identity is coded and packed to single terminal for transmission. Here the transmitted UART data has all the contents of all the terminals multiplexed in a sequential manner. Further upon receiving the data the circuit identifies the data with its terminal number by shift registers and de multiplexes the UART terminals. However, the above method includes sophisticated logic for storing, combining and packetizing the data and then de-multiplexing at the individual UART terminals. This method may be used for in multiple point to point communication, through single UART terminal, where multiplexing and de-multiplexing required at both ends. But it is not suitable for applications, where switching is to be done from a generic user interface like Hyper terminal of a PC.
[0008] US patent no. 7,650,449 B2 dated January 19, 2010, is about a UART interface communication circuit includes a plurality of communication devices, and each includes a UART interface, a selecting apparatus, a CPU, and a multiplexer (MUX). The communication devices connect with each other via the UART interfaces thereof. The selecting apparatus is connected to the CPU for defining one of the CPU as master and rest of the CPUs as slave. In this patent also there is a mux selection line is used and the CPU device has to select the required mux and this is working as master slave architecture.
[0009] US patent no. 9,183,168 B2 dated November 10, 2015, is also about switching of UART connection to the terminal by two different means, once is direct UART cable and other by USB cable. Here the circuit automatically detects the connected cable whether it is USB cable or UART cable and switching is done accordingly. This is about selection of UART or USB and not about switching between multiple UART terminals.
[0010] However, the above-mentioned conventional systems merely talk about UART communication and have limited functions and require addition inputs/command for operation, in particular for switching. Thus, there is a need for a system which can eliminate an additional select-line terminal on the PCB and for switching between multiple UART terminals from a single UART terminal.
SUMMARY
[0011] This summary is provided to introduce concepts of the invention related to a system and method for switching between plurality of UART terminals, as disclosed herein. This summary is neither intended to identify essential features of the invention as per the present invention nor is it intended for use in determining or limiting the scope of the invention as per the present invention.
[0012] In accordance with the present invention, a system for switching between plurality of UART terminals is disclosed. The system comprises: a multiplexer communicably coupled to a user terminal and a plurality of UART terminals; and a special sequence logic module connected to a RX line of the user terminal and a select-line of the multiplexer, wherein the special sequence logic module comprises: a decoder module configured to decode 8-bit data received from the user terminal; a shit register connected to the decoder module, configured to store the decoded data; a comparator module connected to the shift register, configured to compare a first set of data stored at the shift register with a predefined data, and generate a logic signal; and a terminal select logic module connected to the comparator and the shift register, configured to: determine a UART terminal from the plurality of UART terminals, based on the logic signal received from the comparator and a second set of data stored at the shift register; determine whether a UART terminal switching is valid based on the determined UART terminal and currently connected UART terminal, and generate the select-line data for the multiplexer to switch to the determined UART terminal, when the UART terminal switching is valid.
[0013] In an embodiment, the comparator generates a logic signal 1, when the first set of data stored at the shift register matches with the predefined data.
[0014] In an embodiment, the comparator generates a logic signal 0, when the first set of data stored at the shift register does not match with the predefined data.
[0015] In an embodiment, the terminal selection logic module considers the second set of data as the UART terminal number, when the logic signal is 1.
[0016] In an embodiment, the UART terminal switching is valid, when the determined UART terminal and currently connected UART terminal is not same.
[0017] In an embodiment, the user terminal data is a special sequence key stored in a register, wherein the register is of 8-bit or 16-bit.
[0018] In an embodiment, the shift register is a 16-bit shift register configured to store 16-bit of decoded data; wherein the first 8-bit data stored at the 16-bit shift register is the first set of data and the last 8-bit data stored at the 16-bit shift register is the second set of data.
[0019] In an embodiment, the user terminal is UART terminal.
[0020] In an embodiment, the user terminal and the plurality of UART terminals are configured at a constant baud rate.
[0021] In an embodiment, the comparator is 8-bit or 16-bit.
[0022] In another aspect of the present invention, a method for switching between plurality of UART terminals is disclosed. The method comprising: decoding, by a decoder module, 8-bit data received from a user terminal; storing, by a shift register, the decoded data; comparing, by a comparator module, a first set of data stored at the shift register with a predefined data, and generating a logic signal; determining, by a terminal select logic module, a UART terminal from the plurality of UART terminals, based on the logic signal generated by the comparator and a second set of data stored at the shift register; determining, by the terminal select logic module, whether a UART terminal switching is valid based on the determined UART terminal and currently connected UART terminal, and generating, by the terminal select logic module, a select-line data for a multiplexer to switch to the determined UART terminal, when the UART terminal switching is valid; and connecting, by the multiplexer module, the user terminal with the determined UART terminal based on the select-line data.
[0023] In an embodiment, generating the logic signal comprises: generating, by the comparator, a logic signal 1, when the first set of data stored at the shift register matches with the predefined data; generating, by the comparator, a logic signal 0, when the first set of data stored at the shift register does not match with the predefined data.
[0024] In an embodiment, determining the UART terminal from the plurality of terminals comprises: considering, by the terminal selection logic module, the second set of data as the UART terminal, when the logic signal is 1; wherein n being a terminal number.
[0025] In an embodiment, determining whether the UART terminal switching is valid comprises: the UART terminal switching is valid when the determined UART terminal and currently connected UART terminal is not same.
[0026] In an embodiment, the predefined data is a special sequence key stored in a register and the register is 8-bit or 16-bit.
[0027] In an embodiment, the shift register is a 16-bit shift register configured to store 16-bit of decoded data; wherein the first 8-bit data stored at the 16-bit shift register is the first set of data and the last 8-bit data stored at the 16-bit shift register is the second set of data.
[0028] In an embodiment, wherein the user terminal is UART terminal; wherein the user terminal and the plurality of UART terminals are configured at a constant baud rate.
[0029] In an embodiment, the comparator is 8-bit or 16-bit.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0030] The detailed description is described with reference to the accompanying figures.
[0031] Figure 1 illustrates a system block diagram, according to an exemplary implementation of the present disclosure.
[0032] Figure 2 illustrates an internal blocks of a special sequence logic module, according to an exemplary implementation of the present disclosure.
[0033] Figure 3 illustrates a flow chart for identification, according to an exemplary implementation of the present disclosure.
[0034] Figure 4 illustrates a circuit diagram, according to an exemplary implementation of the present disclosure.
[0035] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION
[0036] The present disclosure describes a system and method for automatic switching between multiple UARTs from a single UART terminal.
[0037] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without these details. One skilled in the art will recognize that embodiments of the present disclosure, some of which are described below, may be incorporated into a number of systems.
[0038] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the presently disclosure and are meant to avoid obscuring of the presently disclosure.
[0039] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0040] In the present disclosure and the embodiments, at least one of plural options encompasses all conceivable combinations of the options. At least one of plural options may be one of the options, some of the options, or all of the options. For example, at least one of A, B, or C indicates only A, only B, only C, A and B, A and C, B and C, or A, B, and C.
[0041] The terminology used in the present disclosure is only for the purpose of explaining a particular embodiment, and such terminology shall not be considered to limit the scope of the present disclosure. As used in the present disclosure, the forms “a,” “an,” and “the” may be intended to include the plural forms as well, unless the context clearly suggests otherwise. The terms “comprises,” “comprising,” “including,” and “having” are open ended transitional phrases and therefore specify the presence of stated elements, modules, units and/or components but do not forbid the presence or addition of one or more other elements, components, and/or groups thereof.
[0042] The terms first, second, third, etc., should not be construed to limit the scope of the present disclosure as the aforementioned terms may be only used to distinguish one element, component, region, layer, or section from another component, or section. Terms such as first, second, third etc., when used herein do not imply a specific sequence or order unless clearly suggested by the present disclosure.
[0043] In systems where multiple processor units or microprocessors are involved, the debugging or configuration is controlled through UART terminals of the processors/microcontrollers. The UART include a transmitter line (TX) to transmit data and a receiver line (RX) to receive data. In UART communication, two UARTs can directly communicate with each other. The transmitting UART receive a data from a controlling device for example a CPU and transmit the data serially to the receiver UART. To communicate between two UARTs, the baud rate of the UARTs should be same and the speed of data transfer is dependent on the baud rate.
[0044] In such systems with multiple processors, there is often a physical constraint on a board or a PCB for number of UART terminals i.e., Transmitter and Receiver lines (Tx and Rx) for each of the UART terms. The present disclosure discloses a solution to communication between a user UART terminal and a plurality of UART terminals using one set of Tx and Rx lines and thereby eliminating the additional physical lines for each of the UART terminals.
[0045] In an aspect of the present invention, a multi-processor system is a single board. The board may include a plurality of CPUs/processors, each of the processors has separate UART terminals to communication with an external device, a multiplexer communicably coupled to each of the UART terminal and a user UART terminal and the multiplexer is used for switching between the each of the UART terminals on the board, to connect one of the UART terminals with the user UART terminal.
[0046] The user UART terminal can be provided outside the system and the configuration or debug of each CPUs/processor on the board can be done through switching between the processor’s UART terminals. For this purpose, conventionally, multiplexers were used for switching between the terminals and to switch at a particular terminal an additional select line data was required. The need of additional data to switch or jump at a particular terminal by the multiplexer is provided by the user using physical select line or by additional circuit with and additional interface to the user for connecting the user terminal and the multiplexer. Thus, accommodating physical UART lines for each one the processors and physical select line for the multiplexer becomes a constraint, leading to increased cabling and space requirements on the board and/or within the system. Consequently, there is a need for a system that simplifies and provides a solution to this issue. Thus, the present disclosure discloses a solution to communication between a user UART terminal and a plurality of UART terminals using one set of Tx and Rx lines. This eliminates the need for extra physical lines i.e., physical select line for switching between the UART terminals.
[0047] FIG. 1 illustrates a block diagram of a system (100) for switching between plurality of UART terminals (101) from a user UART terminal (102). The system (100) includes a plurality of UART terminals (1011,…,n) communicably coupled to a multiplexer (103) to receive data from a user UART terminal (102). Each of the UART terminals (101) corresponds to a processor (not shown) for configuration or debugging of the processor. The system may be a multi-processor system on a single board.
[0048] The transmitter line (Tx) and receiver line (Rx) of each of the UART terminals (101) are connected to the user UART terminal (102) via the multiplexer (103). The multiplexer (103) acts as a switching device to connect one of the UART terminals (101) with the user UART terminal (102) for configuration and debugging, wherein the multiplexer (103) connects the transmitter (Tx) line of UART terminal (101) with the receiver (Rx) line of the user UART terminal (102) and receiver (Rx) line of the UART terminal (101) with the transmitter (Tx) line of the user UART terminal (102) based on a terminal select line data. Further, each of the UART terminals (101) have an identification number “#” i.e., 1, 2, 3, 4, 5, etc., which refers to UART terminal 1, UART terminal 2, UART terminal 3, UART terminal 4, etc. these identification numbers help the user to select and communicate with any one of the terminals (1011,…,n) as per his requirements.
[0049] The system (100) further includes a special sequence detect logic (104) which is connected to the Rx line of the user UART terminal to analyze an input data from the user UART terminal (102) for detecting a switching request, determine a terminal number and generate the terminal select line data for the multiplexer. The switching request is a special sequence key sent from the user UART terminal (102), when a user wants to communicate with any one of UART terminals (1011,…,n). The special sequence key is a combination of special key + terminal number i.e., Alt + “terminal number”. For the sake of illustration, if user wants to communicate/switch to the UART terminal 3, the user will send “Alt + 3”. Upon detecting such a special sequence key, the special sequence detect logic (104) will determine the UART terminal number and will generate the select line data for the multiplexer (103) to switch at a particular terminal. Taking the above example, upon detecting a special sequence key “Alt + 3”, the special sequence detect logic (104) determines that the user wants to communicate with the terminal number 3 and accordingly the special sequence logic module (104) will generate a select line data for the multiplexer to switch at the terminal number 3, to connect the user UART terminal (102) with the UART terminal (1013) for communication. The special sequence detect logic (104) will analyze the input data (hereafter referred as user data) in real-time for detection of the special sequence key. The special sequence detect logic (104) is also known as special sequence logic module (104).
[0050] FIG. 2 illustrates the special sequence logic module (104) which includes a UART decoder module (202) coupled to the Rx line of the user UART terminal (102) to receive and decode the user data. The decoder module (202) continuously receives the user data in bytes, wherein the data is 8-bit data. The decoder module (202) has preconfigured settings such as baud rate, parity bit, number of stop bits, etc. to decode the user data. Further, the decoder module (202) identifies a start bit and stop bit and decodes the user data and stores the user data in a 16-bit shift register (203). The 16-bit shift register (203) can store 2 bytes of data at a time i.e., 2 packets of 8-bit data. In an embodiment, the shift register (203) can be of 16-bit or 32-bit or 64-bit, etc. and similarly it can store more packets of 8-bit user data.
[0051] The special sequence detect logic (104) further includes a comparator (204) which is configured to receive the user data i.e., 8-bit data (also referred as first byte) from the 16-bit shift register (203) and compare the user data with a predefined sequence data stored at an 8-bit sequence register (205). If the user data matches with the predefined sequence, the comparator generates a logic signal typically denoted as “1” or “Yes”. If the user data does match with the predefined sequence, the comparator generates a logic signal typically denoted as “0” or “No”. The 8-bit sequence register (205) is preconfigured with an 8-bit special sequence key, which corresponds to “Alt” key of a keyboard. The 8-bit sequence register can be 16-bit, 32-bit, etc., but not limited to 8-bit.
[0052] The special sequence logic module (104) also includes a terminal select logic module (206) communicably coupled to the comparator (204) to receive the logic signals and the 16-bit shift register (203) to receive the 2nd byte data (as referred as next byte), which is the user data. If the terminal select logic module (206) receives the logic signal “1” then the terminal select logic module (206) considers the 2nd byte data stored at the 16-bit shift register (203) as a terminal number and generate the select line data for the multiplexer (103) to the determined terminal number. If the terminal select logic module (206) receives the logic signal “0” then the terminal select logic module (206) ignores the consideration of the 2nd byte data and does not generate the select line data i.e., if the terminal select logic module (206) receives a logic signal “0”, then it does not change the present state of the select line data. The terminal number is based on next byte received at the 16-bit shift register which is in pipeline. The next byte or 2nd byte is nothing, but the user data sent from the user terminal (102). As the terminal number is based on the user data which is 8-bit data. Thus, there can be up to 256 combinations i.e., the system can switch between 2 to 256 terminals.
[0053] The terminal sequence logic module (206) is further configured to validate and verifies the determined UART terminal number i.e., if the value is not a valid terminal number i.e., out of the number of available terminals or the same terminal number, which is currently connected then there will be no change in terminal selection. If the terminal selected is valid and is different from the current terminal the multiplexer (103) will switch to the requested UART terminal (101n) and both the Tx and Rx lines will be redirected to the newly determined UART terminal (101), and existing terminal will be disconnected from the user terminal (102).
[0054] In accordance with the present disclosure, the UART terminal (101) transmits and receives data from the user terminal (102) in parallel and is configured at a constant baud rate. The UART terminals (101) transmit and receive data connected without any delay and no latency is introduced to the data lines. The switching time for switching between the plurality of UART terminals (101) can be calculated based on the baud rate and switching circuit operating clock. In an example, for a baud rate of 115200 the bit time is: 8.6 µs. If one start and one stop bit setting is used, then one character transmission time could be 8.6 µs. Similarly for 10 bits the time required for transmission will be 86 µs. Considering one special character and one terminal number is used to select the channel then two-character times is required before switching to another terminal, which is: 172 µs. If the switching circuit works with 1MHz clock, then switching time is: 1 µs. So total switching time to switch between the plurality of terminals (101) for the above case would be 173 µs.
[0055] FIG.3 illustrates a flow chart of an identification process for switching between the plurality of UART terminals (101). At step 301, the incoming data which is the user 8-bit data is parallel tapped and received at the special sequence logic module (104). At step 302, the special sequence logic module (104) checks or determines the user data for a special sequence key. If the special sequence logic module (104) determines the specific sequence key is matched with the user data then move to step 303, otherwise move to step 301. At step 303, the terminal sequence logic module (206) determines the terminal number (101n) by considering next byte i.e., user data received at the 16-bit shift register (203) and validates if the terminal change is valid based on the present state of select line data i.e., if the present state of the select line data generated by the terminal select logic module (206) is not same as the requested UART terminal (101n), then move to step 304. If the terminal change is not valid i.e., the present state of the select line data generated by the terminal select logic module (206) is same as the requested UART terminal (101n), then move to step 301. At step 304, the terminal select logic module (206) generates the select line data for the multiplexer based on determined terminal number, to switch the connection from the presently connected UART terminal (101n) with the determined UART terminal, thereby connecting the user UART terminal (102) with one of the requested UART terminals (101n). The terminal select logic module (206) always validates the determined UART terminal number and verifies i.e., if the value is not a valid terminal number i.e., out of the number of available terminals or the same terminal number, which is currently connected then there will be no change in terminal selection. If the terminal selected is valid and is different from the current terminal the multiplexer (103) will switch to the requested UART terminal (101) and both the Tx and Rx lines will be redirected to the newly determined UART terminal (101), and existing terminal will be disconnected from the user terminal (102).
[0056] In an embodiment, FIG. 4 illustrates an application circuit diagram, where the CPU/Microprocessor terminals (401) are connected to a field programmable gate array device with TXD, RXD and ground line at the same voltage logic levels i.e., LVCMOS. The programmable logic device (402) is programmed with the same logic as disclosed above for switching between the plurality of UART terminals. The combined single UART line is connected to the external RS232 port (404) via an EIA-232 level translator (403) which will convert the voltage levels to the RS232 compliant port connection.
[0057] In exemplary embodiment, the present disclosure provides a system (100) for switching between plurality of UART terminals (1011,..n) comprising: a multiplexer (103) communicably coupled to a user terminal (102) and a plurality of UART terminals (1011,…n); and a special sequence logic module (104) connected to a RX line of the user terminal (102) and a select-line of the multiplexer, wherein the special sequence logic module (104) comprises: a decoder module (202) configured to decode 8-bit data received from the user terminal (102); a shit register (203) connected to the decoder module (202), configured to store the decoded data; a comparator module (204) connected to the shift register (203), configured to compare a first set of data stored at the shift register (203) with a predefined data, and generate a logic signal; and a terminal select logic module (206) connected to the comparator (204) and the shift register (203), configured to: determine a UART terminal (101n) from the plurality of UART terminals (101-1,…n), based on the logic signal received from the comparator (204) and a second set of data stored at the shift register (203); determine whether a UART terminal switching is valid based on the determined UART terminal (101n) and currently connected UART terminal (101n), and generate the select-line data for the multiplexer (103) to switch to the determined UART terminal (101n), when the UART terminal switching is valid.
[0058] The comparator generates a logic signal 1, when the first set of data stored at the shift register (203) matches with the predefined data; the comparator generates a logic signal 0, when the first set of data stored at the shift register (203) does not matches with the predefined data.
[0059] The terminal selection logic module (206) considers the second set of data as the UART terminal (101n), when the logic signal is 1; wherein n being a terminal number.
[0060] The UART terminal switching is valid, when the determined UART terminal (101n) and currently connected UART terminal (101) is not same.
[0061] The predefined data is a special sequence key stored in a register (205), wherein the register (205) is of 8-bit or 16-bit.
[0062] The shift register is a 16-bit shift register configured to store 16-bit of decoded data; wherein the first 8-bit data stored at the 16-bit shift register is the first set of data and the last 8-bit data stored at the 16-bit shift register is the second set of data.
[0063] The user terminal (102) is UART terminal; wherein the user terminal (102) and the plurality of UART terminals (1011,…n) are configured at a constant baud rate.
[0064] The system as claimed in any one of claims 1 to 7, wherein the comparator is of 8-bit or 16-bit.
[0065] In yet another exemplary embodiment, the present disclosure provides a method for switching between plurality of UART terminals (1011,…n) comprising: decoding, by a decoder module (202), 8-bit data received from a user terminal (102); storing, by a shift register (203), the decoded data; comparing, by a comparator module (204), a first set of data stored at the shift register with a predefined data, and generating a logic signal; determining, by a terminal select logic module (206), a UART terminal (101n) from the plurality of UART terminals (1011,…n), based on the logic signal generated by the comparator (204) and a second set of data stored at the shift register (203); determining, by the terminal select logic module (206), whether a UART terminal switching is valid based on the determined UART terminal (101n) and currently connected UART terminal (101n), and generating, by the terminal select logic module (206), a select-line data for a multiplexer to switch to the determined UART terminal (101), when the UART terminal switching is valid; and connecting, by the multiplexer module (103), the user terminal (102) with the determined UART terminal (101) based on the select-line data.
[0066] The method further comprises generating the logic signal comprises: generating, by the comparator (204), a logic signal 1, when the first set of data stored at the shift register (203) matches with the predefined data; generating, by the comparator (204), a logic signal 0, when the first set of data stored at the shift register (203) does not match with the predefined data.
[0067] The method further comprises determining the UART terminal (101n) from the plurality of terminals (1011,…n) comprises: considering, by the terminal selection logic module (206), the second set of data as the UART terminal (101n), when the logic signal is 1; wherein n being a terminal number.
[0068] The method further comprises determining whether the UART terminal switching is valid comprises: the UART terminal switching is valid when the determined UART terminal (101n) and currently connected UART terminal (101n) is not same.
[0069] The method further comprises that the predefined data is a special sequence key stored in a register (205) and the register (205) is 8-bit or 16-bit.
[0070] The method further comprises the shift register is a 16-bit shift register configured to store 16-bit of decoded data; wherein the first 8-bit data stored at the 16-bit shift register is the first set of data and the last 8-bit data stored at the 16-bit shift register is the second set of data.
[0071] The method further comprises that the user terminal (102) is UART terminal; wherein the user terminal (102) and the plurality of UART terminals (1011,…n) are configured at a constant baud rate. Wherein the comparator is 8-bit or 16-bit.
[0072] Thus, the present disclosure eliminates the additional physical select lines for the multiplexer, which are required for switching between the plurality of UART terminals to connect the user UART terminal to one of the UART terminals (101). The present disclosure provides the following advantages: Switching between multiple UART lines without using any external selection logic lines from user terminal. Using special sequence data from the user terminal for switching between the terminals. Terminal switching logic works on a faster clock speed with minimal latency. Receive terminal is scanned for terminal switch request in parallel without adding any latency on the receive terminal line. In an exemplary embodiment, the logic disclosed is for 4 terminals with 8-bit special key. The special key is customizable and number of channels can be expanded for scalability. Advantages of this approach multiple UART terminals are reduced to single UART terminal. This reduces costs for extra cabling and extra space occupied in the systems for multiple UART terminals.
[0073] The above disclosed system and method for automatic switching between multiple UARTs from a single UART terminal solves the need of a user to physically switch to each terminal for selection, using jumpers, additional circuitry or select signals. Thereby, the present disclosure provides an automatic switching circuit based on input data received from the user terminal along with specification sequence and switches to the desired terminal, without any addition signals.
[0074] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:
1. A system (100) for switching between plurality of UART terminals (1011,..n) comprising:
a multiplexer (103) communicably coupled to a user terminal (102) and a plurality of UART terminals (1011,…n); and
a special sequence logic module (104) connected to a RX line of the user terminal (102) and a select-line of the multiplexer, wherein the special sequence logic module (104) comprises:
a decoder module (202) configured to decode 8-bit data received from the user terminal (102);
a shit register (203) connected to the decoder module (202), configured to store the decoded data;
a comparator module (204) connected to the shift register (203), configured to compare a first set of data stored at the shift register (203) with a predefined data, and generate a logic signal; and
a terminal select logic module (206) connected to the comparator (204) and the shift register (203), configured to:
determine a UART terminal (101n) from the plurality of UART terminals (101¬1,…n), based on the logic signal received from the comparator (204) and a second set of data stored at the shift register (203);
determine whether a UART terminal switching is valid based on the determined UART terminal (101n) and currently connected UART terminal (101n), and
generate the select-line data for the multiplexer (103) to switch to the determined UART terminal (101n), when the UART terminal switching is valid.
2. The system as claimed in claim 1, wherein:
the comparator generates a logic signal 1, when the first set of data stored at the shift register (203) matches with the predefined data;
the comparator generates a logic signal 0, when the first set of data stored at the shift register (203) does not matches with the predefined data.
3. The system as claimed in any one of claims 1 or 2, wherein the terminal selection logic module (206) considers the second set of data as the UART terminal (101n), when the logic signal is 1; wherein n being a terminal number.
4. The system as claimed in any one of claims 1 to 3, wherein the UART terminal switching is valid, when the determined UART terminal (101n) and currently connected UART terminal (101) is not same.
5. The system as claimed in any one of claims 1 to 2, wherein the predefined data is a special sequence key stored in a register (205), wherein the register (205) is of 8-bit or 16-bit.
6. The system as claimed in any one of claims 1 to 5, wherein the shift register is a 16-bit shift register configured to store 16-bit of decoded data; wherein the first 8-bit data stored at the 16-bit shift register is the first set of data and the last 8-bit data stored at the 16-bit shift register is the second set of data.
7. The system as claimed in any one of claims 1 to 6, wherein the user terminal (102) is UART terminal;
wherein the user terminal (102) and the plurality of UART terminals (1011,…n) are configured at a constant baud rate.
8. The system as claimed in any one of claims 1 to 7, wherein the comparator is of 8-bit or 16-bit.
9. A method for switching between plurality of UART terminals (1011,…n) comprising:
decoding, by a decoder module (202), 8-bit data received from a user terminal (102);
storing, by a shift register (203), the decoded data;
comparing, by a comparator module (204), a first set of data stored at the shift register with a predefined data, and generating a logic signal;
determining, by a terminal select logic module (206), a UART terminal (101n) from the plurality of UART terminals (1011,…n), based on the logic signal generated by the comparator (204) and a second set of data stored at the shift register (203);
determining, by the terminal select logic module (206), whether a UART terminal switching is valid based on the determined UART terminal (101n) and currently connected UART terminal (101n), and
generating, by the terminal select logic module (206), a select-line data for a multiplexer to switch to the determined UART terminal (101), when the UART terminal switching is valid; and
connecting, by the multiplexer module (103), the user terminal (102) with the determined UART terminal (101) based on the select-line data.
10. The method as claimed in claim 9, wherein generating the logic signal comprises:
generating, by the comparator (204), a logic signal 1, when the first set of data stored at the shift register (203) matches with the predefined data;
generating, by the comparator (204), a logic signal 0, when the first set of data stored at the shift register (203) does not match with the predefined data.
11. The method as claimed in any one of claims 9 or 10, wherein determining the UART terminal (101n) from the plurality of terminals (1011,…n) comprises:
considering, by the terminal selection logic module (206), the second set of data as the UART terminal (101n), when the logic signal is 1; wherein n being a terminal number.
12. The method as claimed in any one of claims 9 to 11, wherein determining whether the UART terminal switching is valid comprises:
the UART terminal switching is valid when the determined UART terminal (101n) and currently connected UART terminal (101n) is not same.
13. The method as claimed in any one of claims 9 to 12, wherein the predefined data is a special sequence key stored in a register (205) and the register (205) is 8-bit or 16-bit.
14. The method as claimed in any one of claims 9 to 13, wherein the shift register is a 16-bit shift register configured to store 16-bit of decoded data;
wherein the first 8-bit data stored at the 16-bit shift register is the first set of data and the last 8-bit data stored at the 16-bit shift register is the second set of data.
15. The method as claimed in any one of claims 9 to 14, wherein the user terminal (102) is UART terminal;
wherein the user terminal (102) and the plurality of UART terminals (1011,…n) are configured at a constant baud rate.
16. The method as claimed in any one of claims 9 to 15, wherein the comparator is 8-bit or 16-bit.