Description:RELATED APPLICATION The present application claims priority to U.S. Non-Provisional Patent Application No. 17/645,785 filed on 23 December 2021 and titled “System and method for calibrating a time-interleaved digital-to-analog converter”, the entire disclosure of which is hereby incorporated by reference. Background An efficient technique to compensate for the impairments of an analog component (such as a time-interleaved analog-to-digital converter (ADC)) is to use a digital equalizer. To train the digital equalizer, a bandlimited calibration signal needs to be generated and fed to the analog system under test and the output needs to be sampled by an ADC. A time-interleaved ADC could be viewed as an analog system with linear and nonlinear impairments followed by an ideal ADC. Generating a bandlimited calibration signal using a digital-to-analog converter (DAC) has an advantage of flexibility. For instance, it is possible to generate calibration signals of different amplitudes and bandwidths with a DAC. The problem with using a DAC is that it generates images at multiples of the DAC sampling rate. If these images are not removed, then when the ADC samples the calibration signal, the response of the system to be corrected at those images will fall on top of the response of the system at the desired frequencies introducing an error in the calibration process. If the maximum frequency (fmax) of the input analog signal to an ADC is close to fadc/2 (fadc being a sampling frequency of the ADC), a very sharp anti-alias filter is needed at the output of the calibration DAC. Accurate high-order on-chip LC-filters are hard to implement, take up considerable silicon area, and suffer from significant losses, especially in on-chip implementations. Moreover, if ADC operation (and calibration) at different sampling rates (fadc) is desired, multiple filters may be needed with RF multiplexing function. This option would require even more silicon area, as well as a difficult implementation for the RF multiplexer. Alternatively, a single tunable LC-filter may be used, but it would be only possible within a narrow frequency range. Brief description of the Figures Some examples of apparatuses and/or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which FIG. 1 shows an example system for analog-to-digital conversion including calibration circuitry; FIG. 2 shows an example time-interleaved ADC; FIG. 3 shows an example time-interleaved DAC including two sub-DACs; FIG. 4 is a flow diagram of an example process for calibrating a time-interleaved DAC; FIG. 5 illustrates a user device in which the examples disclosed herein may be implemented; FIG. 6 illustrates a base station or infrastructure equipment radio head in which the examples disclosed herein may be implemented; and FIG. 7 shows an example of generating lower-rate clocks at different phases based on a sampling clock and an inverted sampling clock. Detailed Description Various examples will now be described more fully with reference to the accompanying drawings in which some examples are illustrated. In the figures, the thicknesses of lines, layers and/or regions may be exaggerated for clarity. Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Further examples may cover all modifications, equivalents, and alternatives falling within the scope of the disclosure. Like numbers refer to like or similar elements throughout the description of the figures, which may be implemented identically or in modified form when compared to one another while providing for the same or a similar functionality. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an “or”, this is to be understood to disclose all possible combinations, i.e. only A, only B as well as A and B. An alternative wording for the same combinations is “at least one of A and B”. The same applies for combinations of more than 2 elements. The terminology used herein for the purpose of describing particular examples is not intended to be limiting for further examples. Whenever a singular form such as “a,” “an” and “the” is used and using only a single element is neither explicitly or implicitly defined as being mandatory, further examples may also use plural elements to implement the same functionality. Likewise, when a functionality is subsequently described as being implemented using multiple elements, further examples may implement the same functionality using a single element or processing entity. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used, specify the presence of the stated features, integers, steps, operations, processes, acts, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components and/or any group thereof. Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning of the art to which the examples belong. FIG. 1 shows an example system 100 for analog-to-digital conversion including calibration circuitry 101. The calibration circuitry 101 is provided for calibration of an ADC 140 in this example. Alternatively, the system under calibration may be any system other than the ADC 140. Hereafter, the examples will be explained with reference to a case that the calibration circuitry 101 is used for calibration of the ADC 140. However, it should be noted that the calibration circuitry 101 may be used for calibration of any system (that may be referred to as a main system). The ADC 140 (a main ADC) converts the analog input signal 102 to a digital signal. The ADC 140 may be a time-interleaved ADC (TI-ADC) or a different type of ADC. Time interleaving of ADCs is a way to increase the overall system sampling rate by using several ADCs (sub-ADCs) in parallel. FIG. 2 shows an example TI-ADC 200. The TI-ADC 200 includes a plurality of sub-ADCs 210 (M sub-ADCs) coupled in parallel. Each sub-ADC 210 operates at sampling frequency (fs/M) and the overall sampling frequency of the TI-ADC 200 is fs. Each sub-ADC 210 samples the analog input signal at different time instances and the outputs of the sub-ADCs 210 are multiplexed by a multiplexer 220. An ADC 140 is a non-linear device that can incur some linear and/or non-linear distortions on the outputs of the ADC 140. To compensate for the impairments of the ADC 140 (more generally, any linear or non-linear system), a digital equalizer 170 (e.g., a non-linear equalizer (NLEQ)) may be used. The digital equalizer 170 processes an output of the ADC 140 to remove/reduce a linear and/or non-linear distortion incurred by the ADC 140. The digital equalizer 170 may be a digital non-linear filter, e.g., a polynomial or Volterra filter, or a linear filter, e.g., a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter. To train the digital equalizer 170, a bandlimited calibration signal 104 (e.g., a periodic signal) is generated by a calibration DAC 120 and fed to the ADC 140. The calibration signal generator 110 generates digital calibration data, and the calibration DAC 120 converts the digital calibration data to an analog calibration signal 104. The analog calibration signal 104 may be filtered by the anti-alias filter 130 and then injected into the ADC 140 and to the observation ADC 150. Generating a bandlimited signal (i.e., a calibration signal) using a DAC has an advantage of flexibility. For instance, calibration signals of different amplitudes and bandwidths can be generated with a DAC. However, the problem with using a DAC that operates at the same rate as the ADC 140 in generating the bandlimited calibration signal is that the DAC generates images at multiples of the DAC sampling rate. If the images are not removed, then when the ADC samples the calibration signal, the response of the system to be corrected at those images will fall on top of the response of the system at the desired frequencies introducing an error in the calibration process. In examples, a time-interleaved DAC (TI-DAC) is used as the calibration DAC 120 to generate the analog calibration signal 104. A TI-DAC includes two or more sub-DACs and the delayed (time-interleaved) output signals of the two or more sub-DACs are summed such that a higher overall sampling rate is achieved. FIG. 3 shows an example time-interleaved DAC 120 including two sub-DACs 122, 124. The calibration signal generator 110 generates and supplies digital calibration data to the sub-DACs 122, 124, and each sub-DAC 122, 124 generates a corresponding output at a different time instant and the outputs of the sub-DACs 122, 124 are summed by a combiner 126. The summed output is then filtered by an alti-aliasing filter 130. Each sub-DAC 122, 124 may operate at a sampling rate F_s (the sampling rate of the main ADC 140). In examples, one sub-DAC 122 (e.g., DAC 0) may be clocked by the ADC sampling clock at F_s and the other sub-DAC 124 (e.g., DAC 1) may be clocked by the inverted ADC sampling clock at F_s. The clock going to one sub-DAC is the inverse of the clock going to the other sub-DAC. By using the 2x time-interleaved DAC 120, the image frequencies of the time-interleaved DAC 120 are at multiples of twice the non-interleaved DAC rate and hence are easier to remove by filtering. The analog calibration signal 104 may be attenuated by the attenuator 132 and sampled and quantized by the observation ADC 150. The observation ADC 150 converts (samples) the analog calibration signal to a digital domain. The reference estimation circuitry 160 generates a reference signal from the sampled calibration signals for adaptive equalization of the ADC 140. The NLEQ coefficient estimation circuitry 162 is configured to generate coefficients for the digital equalizer 170 based on the reference signal (i.e., the reference data recovered via the observation ADC 150 and the reference estimation circuitry 160, or alternatively the digital reference data) and the output of the ADC 140. Any conventional digital adaptation algorithm may be used for the NLEQ coefficient estimation, e.g., a least mean square (LMS), recursive least square (RLS), etc. The digital equalizer 170 processes the output of the ADC 140 based on the coefficients received from the NLEQ coefficient estimation circuitry 162. With a time-interleaved DAC 120 (TI-DAC) used to generate the analog calibration signal 104, there is a mismatch problem between the sub-DACs 122, 124. In examples, the mismatch between the sub-DACs 122, 124 may be estimated by the mismatch estimation block 196 based on the outputs of the observation ADC 150. The duty cycle estimation and correction may also be performed by the duty cycle correction block 194 and the duty cycle estimation block 192 to correct impairments due to clock skew of the observation ADC 150, which will be explained in detail below. The observation ADC 150 may capture the analog calibration signal 104 (e.g., a periodic signal) at an effective rate of 2F_s (Fs being the sampling frequency of the ADC 140, or an operating frequency of a main system, in general). The observation ADC 150 may be a low-rate ADC (e.g., additional sub-ADC of a TI-ADC operating at F_s) operating at F_c=F_s/M, where M is the interleaving factor of the TI-ADC. To generate the samples with a resolution of T_s/2 (i.e., the effective rate of 2Fs), the observation ADC 150 may be clocked by the ADC sampling clock (ϕ_s) and the inverted ADC sampling clock ((ϕ_s ) ̅), and 2M lower-rate clocks (〖F_c=F〗_s/M) at different phases may be generated by using the system clock and the inverted system clock to effectively sample the analog calibration signal at all of its phases at 2Fs. FIG. 7 shows an example of generating 2M lower-rate clocks 712-726 at different phases in case of M=4. The observation ADC 150 may be clocked by the system clock 702 (Fs) and the inverted system clock 704 (Fs), and generate 8 (i.e., = 2M) lower-rate clocks 712-726 (at F_s/4 in this example) at different phases for the effective combined sampling rate of 2Fs based on the system clock 702 and the inverted system clock 704. Each of the lower-rate clocks 712-726 has a different phase. The observation ADC 150 samples the analog calibration signal 104 using the 8 lower-rate clocks 712-726 (one at a time and cycling through all the lower-rate clocks 712-726) and combine the samples generated for different phases to effectively sample the analog calibration signal 104 at 2Fs. In this case, if the ADC sampling clock does not have a 50% duty cycle, the duty cycle skew may occur. The duty cycle skew and the impairments due to the duty cycle skew needs to be estimated and corrected by the duty cycle estimation block 192 and the duty cycle correction block 194. For this purpose, a filtered clock signal 108 at the rate of F_s K/M may be fed into the observation ADC 150, which will be explained in detail below. The TI-DAC mismatch estimate block 196 estimates the mismatch correction factor and sends it to the calibration signal generator 110. The calibration signal generator then applies the correction factor to the calibration data in a digital domain. The process for TI-DAC mismatch correction and observation ADC clock duty cycle skew estimation and correction are explained below. The train of pulses is periodic, and it can be represented as a Fourier series as follows: ∑_(n=-∞)^∞▒δ(t-nT_s ) =1/T_s ∑_(n=-∞)^∞▒e^(j 2π/T_s nt) . Equation (1) The outputs of the first sub-DAC 122 (DAC 0 in FIG. 3) and the second sub-DAC 124 (DAC 1 in FIG. 3) may be written as follows: s_0 (t)=p_0 (t)*((d_0+s(t)) ∑_(n=-∞)^∞▒δ(t-nT_s ) ), and Equation (2) s_1 (t)=p_1 (t)*((d_1+s(t-T_skew ))∑_(n=-∞)^∞▒δ(t-nT_s-T_s/2-T_skew ) ). Equation (3) where p_0 (t) and p_1 (t) are the pulse shapes of DAC 0 and DAC 1, respectively. The anti-alias filter impulse response is assumed to be included in p_0 (t) and p_1 (t). d_0 and d_1 are the DC offsets for DAC 0 and DAC 1, respectively, and s_0 (t) and s_1 (t) are the desired output waveforms of DAC 0 and DAC 1, respectively. T_skew is the clock skew between the clocks to DAC 0 and DAC 1. Ts is the sampling period of DAC 0 and DAC 1. The outputs of the DAC 0 and DAC 1 in the frequency domain may be written as: S_0 (f)=1/T_s P_0 (f) ∑_(n=-∞)^∞▒(d_0 δ(f-nF_s )+S(f-nF_s )) , Equation (4) S_1 (f)=1/T_s P_1 (f) e^(-j2πfT_skew ) ∑_(n=-∞)^∞▒〖e^(-jπn) (d_1 δ(f-nF_s )+S(f-nF_s )) 〗. Equation (5) The clock skew T_skew could be combined with the frequency response of P_1 (f). The outputs of the two sub-DACs (DAC 0 and DAC 1) are added as follows: S_dac (f)=S_0 (f)+S_1 (f)=1/T_s ∑_(n=-∞)^∞▒(P_0 (f)+(-1)^n P_1 (f) e^(-j2πfT_skew ) )S(f-nF_s ) +1/T_s ∑_(n=-∞)^∞▒(d_0 P_0 (f)+(-1)^n d_1 P_1 (f) e^(-j2πfT_skew ) )δ(f-nF_s ) . Equation (6) The first step in TI-DAC calibration is to correct the frequency response mismatch between the two sub-DACs 122, 124. Example solution for the correction of the mismatch is described below. However, it should be noted that the solution described below is just one example and other solutions may be utilized to implement the calibration procedure. Since the calibration signal (a reference signal) is generally periodic, its spectrum is discrete, and it is sufficient to consider how to calibrate the TI-DAC 120 for one frequency. This procedure may then be repeated for all frequencies occupied by the calibration signal. Consider a sinewave used as the calibration signal as follows: s(t)=A_s sin⁡(2πf_c t+ϕ_s ), Equation (7) S(f)=A_s/2j (δ(f-f_c ) e^(jϕ_s )-δ(f+f_c ) e^(-jϕ_s ) ). Equation (8) The output of the TI-DAC 120 for a sinewave input is written as follows: S_dac (f)=1/T_s A_s/2j ∑_(n=-∞)^∞▒[(P_0 (nF_s+f_c )+(-1)^n P_1 (nF_s+f_c ) e^(-j2π(nF_s+f_c ) T_skew ) )δ(f-f_c-nF_s ) e^(jϕ_s )-(P_0 (nF_s-f_c )+(-1)^n P_1 (nF_s-f_c ) e^(-j2π(nF_s-f_c ) T_skew ) )δ(f+f_c-nF_s ) e^(-jϕ_s ) ] +1/T_s ∑_(n=-∞)^∞▒(d_0 P_0 (nF_s )+(-1)^n d_1 P_1 (nF_s ) e^(-j2πfT_skew ) )δ(f-nF_s ) . Equation (9) It is assumed that the TI-DAC anti-aliasing filters 130 remove components above F_s. The TI-DAC anti-alias filter output is sampled by the observation ADC 150 effectively sampling at 2F_s, so that the spectrum can be evaluated at positive frequencies in the range 0