Description:FIELD OF INVENTION
[0001] The present subject matter generally relates to converter circuits, more particularly relates to a system and method for converting alternating current (AC) to direct current (DC) with power factor correction.
BACKGROUND
[0002] A conventional electric vehicle (EV) EV battery charger includes a boost-type Power Factor Correction (PFC) circuit for shaping the input current, followed by an isolated DC-DC converter for voltage regulation. Some of the popular topologies commonly used for these chargers, include a conventional boost type PFC or a totem-pole PFC followed by a DC-DC converter such as a Phase-shifted full-bridge, a resonant LLC, or a dual active bridge (DAB) type converter.
[0003] Usually, in a boost-type power factor correction (PFC) circuit, a PFC stage is hard-switched, and a DC-DC stage is soft-switched. Soft switching the PFC stage may open up interesting possibilities. One such possibility may include a DAB based soft-switched single-stage AC-DC converter for battery charging applications. In such converters, a grid voltage is initially folded and then applied to a DAB converter. Further, a wide variation of voltage on the primary (due to folding operation) and secondary (due to battery load) sides may impact a zero-voltage switching of the DAB converter. As a result, analysis, design and practical implementation of such converters become quite complicated.
[0004] A current fed type isolated boost PFC converter is another possibility where the PFC stage is soft-switched. In such converters, a diode bridge is typically used on a secondary side of a transformer to rectify high-frequency transformer voltage. When an uncontrolled diode bridge is employed on the secondary side of the transformer, an output voltage becomes tightly coupled to a clamp capacitor voltage through the turns ratio of the transformer. This tight coupling of voltages limits the ability of the converter to vary the output voltage over a wide range, consequently restricting the range over which the output power can be varied, which may not be attractive. Although the PFC converter is employed for battery charging, such PFC converter lacks capability to allow the wide variation of voltages at the output stage. The minimum output voltage is constrained to avoid overmodulation of the converter. While this PFC converter provides soft switching and active clamping for improved efficiency, its limited output voltage range restricts its applicability in situations where flexibility in the output voltage is a critical requirement. Therefore, there is a demand for a novel converter to address voltage variation issues.
[0005] Hence, there is a need for an improved system and method for converting alternating current (AC) to direct current (DC) with power factor correction and soft-switching in order to address the aforementioned issues.
SUMMARY
[0006] In accordance with an embodiment of the present disclosure, a system for converting Alternating Current (AC) to Direct Current (DC) is disclosed. The system may include: a converter. The converter includes a primary stage and a secondary stage.
[0007] In accordance with an embodiment, each stage includes a plurality of switches, wherein the converter is configured to convert Alternating Current (AC) to Direct Current (DC) with power factor correction (PFC) and allow regulation of a range of DC output voltages and powers.
[0008] In accordance with an embodiment, the primary stage is galvanically isolated from the secondary stage using a high-frequency transformer.
[0009] In accordance with an embodiment, the system includes a plurality of voltage sensors configured to measure a plurality of voltage levels at a plurality of nodes associated with the converter.
[0010] In accordance with an embodiment, the system includes a plurality of current sensors configured to measure a plurality of current levels through plurality of circuit elements associated with the converter.
[0011] In accordance with an embodiment, the system includes a controller unit, communicatively coupled to the converter. The controller unit is configured to receive the measured plurality of voltage levels from the plurality of voltage sensors and the measured plurality of current levels from the plurality of current sensor, and generate one of a desired reference voltage level and a desired reference current level to allow regulation of a range of DC output voltages and currents at a converter output port. Further, the controller unit is configured to determine one or more control parameters corresponding to the primary stage, and the secondary stage. The control parameters include at least one of a duty ratio of the primary stage, a duty ratio of the secondary stage, and a control phase shift between a primary voltage associated with the primary stage, and a secondary voltage associated with the secondary stage, a switching frequency, a dead time of the primary stage, and a dead time of the secondary stage; modulate the determined one or more control parameters corresponding to the primary stage, and the secondary stage.
[0012] In accordance with an embodiment, the controller unit is configured to generate a plurality of control signals for the plurality of switches based on the modulated one or more control parameters.
[0013] In accordance with an embodiment, the controller unit is configured to control the plurality of switches in the primary stage and the secondary stage based on the generated plurality of control signals, by using a modulation scheme and a switching pattern, for correcting Power Factor (PF) of the converter. The switching pattern is configured to enable soft switching of the plurality of switches.
[0014] In accordance with an embodiment, the system includes a plurality of drive circuits configured to apply the generated plurality of control signals at the plurality of switches based on the modulation scheme and the switching pattern.
[0015] In accordance with another embodiment, a method for converting alternating Current (AC) to Direct Current (DC) is disclosed. The method includes receiving, by a controller unit, a plurality of voltage levels and a plurality of current levels measured from a converter, wherein the converter includes a primary stage, and a secondary stage, wherein each stage comprises a plurality of switches, and wherein the primary stage is galvanically isolated from the secondary stage using a high-frequency transformer.
[0016] In accordance with an embodiment, a method for converting alternating Current (AC) to Direct Current (DC) includes generating, by the controller unit, one of a desired reference voltage level and a desired reference current level to allow regulation of a range of DC output voltages and currents at a converter output port.
[0017] In accordance with an embodiment, a method for converting alternating Current (AC) to Direct Current (DC) includes determining, by the controller unit, one or more control parameters corresponding to the primary stage, and the secondary stage.
[0018] In accordance with an embodiment, the control parameters include at least one of a duty ratio of the primary stage, a duty ratio of the secondary stage, and a control phase shift between a primary voltage associated with the primary stage, and a secondary voltage associated with the secondary stage, a switching frequency, a dead time of the primary stage, and a dead time of the secondary stage.
[0019] In accordance with an embodiment, a method for converting alternating Current (AC) to Direct Current (DC) includes modulating, by the controller unit, the determined one or more control parameters corresponding to the primary stage, and the secondary stage.
[0020] In accordance with an embodiment, the method further includes generating, by the controller unit, a plurality of control signals for the plurality of switches based on the modulated one or more control parameters.
[0021] In accordance with an embodiment, the method further includes controlling, by the controller unit through the plurality of drive circuits, the plurality of switches in the primary stage and the secondary stage based on the generated plurality of control signals, by using a modulation scheme and a switching pattern, for correcting a Power Factor (PF) of the converter, wherein the switching pattern is configured to enable soft switching of the plurality of switches.
[0022] To further clarify the advantages and features of the present disclosure, a more particular description of the disclosure will follow by reference to specific embodiments thereof, which are illustrated in the appended figures. It is to be appreciated that these figures depict only typical embodiments of the disclosure and are therefore not to be considered limiting in scope. The disclosure will be described and explained with additional specificity and detail with the appended figures.
BRIEF DESCRIPTION OF DRAWINGS
[0023] The disclosure will be described and explained with additional specificity and detail with the accompanying figures in which:
[0024] FIG. 1A is an exemplary circuit diagram illustrating a current-fed dual active bridge alternating current (AC) to direct current (DC) boost power factor correction (PFC) converter with an active clamp and a secondary full bridge configuration, in accordance with an embodiment of the present disclosure;
[0025] FIG. 1B is an exemplary circuit diagram illustrating a current-fed dual a bridge alternating current (AC) to direct current (DC) boost power factor correction (PFC) converter with an active clamp and a secondary half-bridge configuration, in accordance with an embodiment of the present disclosure;
[0026] FIG. 1C is an exemplary circuit diagram illustrating a current-fed dual active bridge alternating current (AC) to direct current (DC) boost power factor correction (PFC) converter with an active clamp and a diode bridge based front-end configuration, in accordance with an embodiment of the present disclosure;
[0027] FIG. 2A is an exemplary graphical representation depicting a primary voltage, a secondary voltage and primary current waveforms in accordance with an embodiment of the present disclosure;
[0028] FIG. 2B is another exemplary graphical representation depicting a primary voltage, a secondary voltage, and primary current waveforms over two switching cycles, in accordance with another embodiment of the present disclosure;
[0029] FIG. 2C is another exemplary graphical representation depicting a clamp capacitor voltage, a grid voltage, and grid current waveforms, in accordance with an embodiment of the present disclosure;
[0030] FIG. 2D is another exemplary graphical representation depicting an output capacitor voltage and output current waveforms over two-lines, in accordance with an embodiment of the present disclosure;
[0031] FIG. 3 is a diagram of an exemplary controller unit, in accordance with an embodiment of the present disclosure;
[0032] FIG. 4 is a circuit diagram of an exemplary single-phase module shown in FIG. 5A-FIG. 5D for an electric vehicle (EV) charging application, in accordance with an embodiment of the present disclosure;
[0033] FIG. 5A is an exemplary block diagram of a three-phase STAR configuration with a single output for fast charging, in accordance with an embodiment of the present disclosure;
[0034] FIG. 5B is an exemplary block diagram of a three-phase STAR configuration with multiple outputs for normal charging, in accordance with an embodiment of the present disclosure;
[0035] FIG. 5C is an exemplary block diagram of a three-phase DELTA configuration with a single output for fast charging, in accordance with an embodiment of the present disclosure;
[0036] FIG. 5D is an exemplary block diagram of a three-phase DELTA configuration with multiple outputs for normal charging, in accordance with an embodiment of the present disclosure;
[0037] FIG. 6 is an exemplary overall architecture diagram depicting an exemplary system for converting an alternating current (AC) to a direct current (DC) with power factor correction, in accordance with an embodiment of the present disclosure; and
[0038] FIG. 7 is a flow diagram illustrating an exemplary method for converting Alternating Current (AC) to Direct Current (DC) is disclosed, in accordance with embodiment of the present disclosure.
[0039] Further, those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and may not have necessarily been drawn to scale. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the figures by conventional symbols, and the figures may show only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the figures with details that will be readily apparent to those skilled in the art having the benefit of the description herein.
DETAILED DESCRIPTION OF THE DISCLOSURE
[0040] For the purpose of promoting an understanding of the principles of the disclosure, reference will now be made to the embodiment illustrated in the figures and specific language will be used to describe them. It will nevertheless be understood that no limitation of the scope of the disclosure is thereby intended. Such alterations and further modifications in the illustrated system, and such further applications of the principles of the disclosure as would normally occur to those skilled in the art are to be construed as being within the scope of the present disclosure. It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the disclosure and are not intended to be restrictive thereof.
[0041] In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
[0042] The terms "comprise", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that one or more devices or sub-systems or elements or structures or components preceded by "comprises... a" does not, without more constraints, preclude the existence of other devices, sub-systems, additional sub-modules. Appearances of the phrase "in an embodiment", "in another embodiment" and similar language throughout this specification may, but not necessarily do, all refer to the same embodiment.
[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. The system, methods, and examples provided herein are only illustrative and not intended to be limiting.
[0044] Accordingly, the term “module” or “subsystem” should be understood to encompass a tangible entity, be that an entity that is physically constructed permanently configured (hardwired) or temporarily configured (programmed) to operate in a certain manner and/or to perform certain operations described herein.
[0045] Embodiments of the present disclosure provides a system and method for converting Alternating Current (AC) to Direct Current (DC) with power factor correction.
[0046] Referring now to the drawings, and more particularly to FIG. 1A through FIG. 7, where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments and these embodiments are described in the context of the following exemplary system and/or method.
[0047] FIG. 1A is an exemplary circuit diagram illustrating a current-fed dual active bridge alternating current (AC)-direct current (DC) boost power factor correction (PFC) converter 100 with an active clamp and a secondary full bridge configuration, in accordance with an embodiment of the present disclosure. According to FIG. 1A, a current-fed dual active bridge alternating current-direct current AC-DC boost power factor correction (PFC) converter 100 (also referred herein as converter 100) is disclosed. In an exemplary embodiment, the converter 100 may include a primary stage 104a and a secondary stage 104b. The primary stage 104a may be configured to correct a power factor (PF) in the secondary full bridge configuration. The converter 100 may be configured to convert Alternating Current (AC) to Direct Current (DC) with power factor correction (PFC) and allow regulation of a range of DC output voltages and powers. The primary stage 104a may be galvanically isolated from the secondary stage 104b. In an exemplary embodiment, the primary stage 104a may include a line-frequency H-bridge 102, a clamp circuit 116, and a high-frequency-H-bridge 103. In an embodiment, the line-frequency H-bridge 102 may include a first set of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d which may be electrically interfaced with an AC supply voltage vg. The first set of switches Sa 106a, Sb 106b, Sc 106c, and Sd 106d may be configured to operate in a range of line frequencies for synchronous rectification to limit conduction losses. The range of line frequency may include, but not limited to, a frequency range between 45–65 Hz.
[0048] Further, the primary stage 104a may include a primary inductor 114 connected in series between the first set of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d (hereinafter referred to as the first switches S 106) and a clamp circuit 116. The first switches S 106 may be configured to enable bidirectional power flow by selecting polarity of load current, io through a closed loop strategy. The closed loop strategy may include a closed loop controller that determines and manages the direction of power flow in the circuit. This strategy may include a feedback and control mechanisms to make real-time decisions about the polarity of the load current (i.e., the direction in which current flows through the load). For power flow from a load side to a grid side, voltage from a secondary side 130b of the high-frequency transformer 120 may lead the primary side voltage. Consequently, a polarity of a control phase shift angle may be adjusted shown in FIG. 3. The closed loop controller may be configured to generate the phase shift angle. The phase shift angle may include an angular measurement that quantifies the time delay or phase difference between two waveforms. The phase shift angle may be typically measured in degrees or radians and indicate how much one waveform lags or leads the other in time. The clamp circuit 116 may include a controlled auxiliary switch Saux 112 connected in series with a clamp capacitor 113 The clamp circuit 116 is electrically connected across a high-frequency H-bridge 103, and the clamp circuit 116 is configured to clamp a voltage across each of a second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d (hereinafter referred to as the second switches S 108) within the high-frequency H-bridge 103 of the primary stage 104a. In an exemplary embodiment, the high-frequency H-bridge 103 may include the second set of controlled switches S 108 electrically connected across the clamp circuit 116. The second switches S 108 may be configured to operate in a range of frequency higher than the range of line frequency (for example 10 kHz – 1 MHz). The second switches S 108 of the high-frequency H-bridge 103 in the primary stage 104a are modulated in synchronization with the controlled auxiliary switch Saux 112 for power factor correction.
[0049] The converter 100 may include a high-frequency transformer 120 electrically coupled to the primary stage 104a and the secondary stage 104b. The high-frequency transformer 120 may be configured to provide a galvanic isolation. The secondary stage 104b may include a third set of controlled switches S5 110a, S6 110b, S7 110c, S8 110d (hereinafter referred to as the third switches S 110) and a capacitor 122 electrically interfaced with a secondary winding of the high-frequency transformer 120. The switches S 106, S 108, Saux 112, S 110, may include, but not limited to, silicon metal-oxide-semiconductor field-effect transistor (Si MOSFET), Silicon based insulated-gate bipolar transistor (Si IGBT), silicon carbide (SiC) MOSFET, gallium nitride (GaN) high-electron-mobility transistor (HEMT), and the like.
[0050] The third switches S 110 may be configured to control an output current or a DC output voltage. The voltage of the clamp capacitor 113 may be maintained above a threshold level, and a current waveform of the primary inductor 114 may be modulated to track a desired pattern for correcting the power factor. The threshold level of the clamp capacitor voltage 113 is higher than the peak value of the grid voltage, vg. The threshold level may be higher than 1.414 times the rms value of the grid voltage. The rms value of the grid voltage may vary from 85V-265V for universal applications. In an embodiment of the present disclosure, the converter 100 may be configured for correcting the power factor in a single-phase module (shown in FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D) configuration. In an embodiment of the present disclosure, the converter 100 may be configured for correcting the power factor in a multi-phase module shown in FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D) configuration. For modulating the current waveform of the primary inductor 114, the primary stage 104a may be configured to switch the second switches S108 in synchronization with the controlled auxiliary switch Saux 112 using a modulation technique. The modulation technique may include, but not limited to, a pulse width modulation technique, and the like. The pulse width modulation technique may include applying a plurality of voltage vectors across the primary inductor 114. The voltage vectors may include combinations or patterns of voltage applied across the primary inductor 114. The primary stage 104a may be configured to modify a time interval associated with the plurality of voltage vectors. The time interval of the voltage vectors may refer to the voltage duration or timing of voltage patterns applied across the primary inductor 114. The time interval of the voltage vectors may be varied sinusoidally over a 10-millisecond period to obtain a rectified sinusoid waveform. The primary stage 104a may be configured to modulate the current waveform of the primary inductor 114 to track the desired pattern (such as for example, a sine wave pattern) based on the modified time interval and vary a pulse width of the primary voltage v11’ associated with the primary stage 104a. A converter input port 118 may be configured to actively manipulate grid current values, ig, so that the grid current values ig closely resemble a sinusoidal waveform and are phase-aligned with the grid voltage, vg.
[0051] The clamp circuit 116 may be configured to create a pathway for the current in the primary inductor 114 when one of the second switches S 108 in the high-frequency H-bridge 103 are turning OFF. The clamping operation is essential for clamping the voltage across each of the second switches S 108 within the high-frequency H-bridge 103 of the primary stage 104a. The controlled auxiliary switch Saux 112 and the second switches S 108 in the primary stage 104a may be configured to allow voltage states to be controllably applied across nodes 1-1’ of the high-frequency H-bridge 103. The voltage states may include, but not limited to, a positive voltage, a negative voltage, and a zero voltage.
[0052] In an embodiment of the present disclosure, a secondary side diode bridge (not shown) may be replaced with the third switches S 110. The third switches S 110 may be configured to allow voltage states. The voltages states may be applied across the secondary side 130b of the high-frequency transformer 120 in a precisely controlled manner. The voltage states may include, but not limited to, a positive voltage, a negative voltage, and a zero voltage. When an uncontrolled diode bridge (not shown) is used on the secondary side, an output voltage (vo) is tightly linked to the clamp capacitor voltage (vaux) through a duty ratio (n:1) of the high-frequency transformer 120. This linkage imposes a lower limit on both vaux and (vo) to prevent overmodulation. However, through the incorporation of the third switches S 110 on the secondary side 130b of the high-frequency transformer 120, the output voltage (vo) may be decoupled from the clamp capacitor voltage (vaux). This decoupling enables a broad spectrum of adjustments in the output voltage (vo) for a specific power level, and, inversely, extensive modulation of the output power for a given output voltage (vo). This level of flexibility in voltage and power control may be unattainable when employing the secondary diode bridge (not shown).
[0053] In an embodiment of the present disclosure, the controlled auxiliary switch Saux 112, the second switches S 108 of the high-frequency H-bridge 103 in the primary stage 104a and the third switches S 110 of the secondary stage 104b may be configured to operate in a soft switching mode. Each of controlled auxiliary switch Saux 112, the second switches S 108 and the third switches S 110 may be configured to be softly activated using a switching pattern.
[0054] FIG. 1B is an exemplary circuit diagram illustrating a current-fed dual active bridge type alternating current (AC) to direct current (DC) boost power factor correction (PFC) converter with an active clamp and a secondary half-bridge configuration, in accordance with an embodiment of the present disclosure. The secondary stage 104b of the converter 100 may include a half-bridge configuration. The half-bridge configuration may include the third switches S5 110a, S6 110b, and one or more capacitors 124a, 124b in the secondary half-bridge configuration as shown in FIG. 1B. The third switches S5 110a, S6 110b, and the one or more capacitors 124a, 124b may be configured to allow square wave voltages. The square wave voltages may be applied across the secondary side 130b of the high-frequency transformer 120.
[0055] The converter 100 may include two inductors 114, 126 such as a primary inductor L 114 and a leakage inductor Llk 126. When any of the switching patterns listed in Table is employed, it may result in an interruption in the current flow through at least one of these inductors 114, 126. This interruption may result in a voltage overshoot occurring across the second switches S 108, due to rate of change of current, expressed as Ldi/dt. The controlled auxiliary switch Saux 112 may be positioned in a specific orientation to ensure a pathway for a flow of inductor current within the converter 100. For example, if a power MOSFET is used to realize Saux 112, a source terminal of 112 may be connected to the inductor 114, and a drain terminal may be connected to the clamp capacitor 113. Hence, the controlled auxiliary switch Saux 112 and the clamp capacitor 113, serve as the active clamp circuit 116. The positions of the auxiliary switch Saux 112 and the clamp capacitor 113 may be interchanged to realize the clamp circuit 116 without compromising its functionality. The controlled auxiliary switch Saux 112 and the clamp capacitor 113, clamps the voltage across the second switches S 108 to vaux during turn OFF (prohibiting voltage overshoots). The controlled auxiliary switch Saux 112 may be not employed on the secondary stage 104b since the secondary stage 104b is voltage fed, which prevents any voltage overshoots across the third switches S110.
[0056] In an exemplary embodiment, the switches auxiliary switch Saux 112, S 108, S 110 may be configured to be softly activated when the voltage across the auxiliary switch Saux 112, switches S 108, S 110 is zero while they are gated ON. The current may be directed through a body diode of the switch Saux 112 or S1 108aor S2 108b or S3 108c or S4 108d or S5 110a or S6 110b or S7 110c or S8 110d under consideration by appropriately modulating the remaining switches. For modulation technique, the below table lists the combination of switches and voltage generated for primary side switches:
Table 1. Modulation techniques and switching patterns for the primary side switches
Modulation Scheme 1
Saux S1 S2 S3 S4 v11’ vL
ON ON OFF OFF ON vaux (+ve) |vg|-vaux
ON OFF ON ON OFF -vaux
(-ve) |vg|-vaux
OFF ON ON ON ON Zero |vg|
Modulation Scheme 2
Saux S1 S2 S3 S4 v11’
ON ON OFF OFF ON vaux (+ve) |vg|-vaux
ON OFF ON ON OFF -vaux
(-ve) |vg|-vaux
OFF ON ON OFF OFF Zero |vg|
OFF OFF OFF ON ON Zero |vg|

TABLE. 1
[0057] For modulation technique, the below table lists the combination of switches and voltage generated for secondary side 130b switches in full bridge configuration and half-bridge configuration shown in FIG. 1A and FIG. 1B:

Table.2. Modulation technique for secondary side bridge
Full Bridge Configuration
S5 S6 S7 S8 v22’
ON OFF OFF ON vo
ON OFF ON OFF Zero
OFF ON OFF ON Zero
OFF ON ON OFF -vo

Half-Bridge Configuration
S5 S6 v22’
ON OFF vo
OFF ON -vo
TABLE. 2
[0058] The controlled auxiliary switch Saux 112, the second switches S 108 of the high-frequency H-bridge 103 in the primary stage 104a and the third switches S 110 of the secondary stage 104b may be configured to operate in a soft switching mode. Each of controlled auxiliary switch Saux 112, the second switches S 108 and the third switches S 110 may be configured to be softly activated using the switching pattern as shown in Table. 1 and 2.
[0059] FIG. 1C is an exemplary circuit diagram illustrating a current-fed dual active bridge alternating current (AC) to direct current (DC) boost power factor correction (PFC) converter with an active clamp and a diode bridge based front-end configuration, in accordance with an embodiment of the present disclosure. In the diode bridge based front-end configuration, the primary stage 104a of the converter 100 may include one or more diodes 128a, 128b, 128c, 128d, auxiliary switch Saux 112, the second switches S 108. The diodes 128a, 128b, 128c, 128d in the primary stage 104a may provide a one-way path for the electrical current. The diodes 128a, 128b, 128c, 128d may be configured to allow power to flow in a single direction and prevent reverse flow. The diodes 128a, 128b, 128c, 128d, as represented in the circuit diagram FIG. 1C, may be particularly suited for low-cost and low-power applications with unidirectional power flow requirements.
[0060] FIG. 2A is an exemplary graphical representation 200a depicting a primary voltage, a secondary voltage, and primary current waveforms, transformer voltage and current waveforms, in accordance with an embodiment of the present disclosure. The voltage and current waveforms 200a may include a primary voltage waveform 206a, a transformer primary current waveform 206b, and a secondary voltage waveform reflected to a primary side 206c. The pulse width of the primary voltage v11’ may change over a line cycle as the switches Saux 112 and S108 are activated and deactivated for PFC operation. The transformer primary current waveform 206b represents the current ip 204 flowing through the primary side 130a of the high-frequency transformer 120. The transformer primary current waveform 206b shows how current ip changes during the operation of the high-frequency transformer 120. The secondary voltage waveform 206c represents the voltage v22’ across the secondary side 130b of the high-frequency transformer 120.
[0061] FIG. 2B is another exemplary graphical representation 200b depicting a primary voltage, a secondary voltage, primary current waveforms over two switching cycles, in accordance with an embodiment of the present disclosure. The voltage and current waveforms 200b include a primary voltage waveform 208a, a primary current waveform 208b, and a secondary voltage waveform 208c reflected to primary side. The voltage and current waveforms 200a, 200b may include the high-frequency switching waveforms of the voltages and currents.
[0062] FIG. 2C is another exemplary graphical representation 200c depicting a clamp capacitor voltage, a grid voltage and grid current waveforms, in accordance with an embodiment of the present disclosure. The waveforms 200c include a grid voltage waveform 210a, a grid current waveform 210b, and an clamp capacitor voltage waveform 210c. In this representation, the voltage values across the clamp capacitor, vaux (for example, the clamp capacitor 113), may be carefully regulated to maintain a steady voltage 400 V. Additionally, the grid current values, ig, may be actively manipulated to assume the grid current waveform 210b that closely resembles a sinusoidal waveform, and it is phase-aligned with the grid voltage, vg shown in the grid voltage waveform 310a. This phase alignment helps optimize the power factor of the PFC converter 100.
[0063] FIG. 2D is another exemplary graphical representation 200d depicting output capacitor voltage and output current waveforms over two-line cycles, in accordance with an embodiment of the present disclosure. The output capacitor voltage and output current waveforms 200d may include an output capacitor voltage waveform 212a, an output current waveform 212b, and a control phase shift waveform 212c. Within this visual depiction, the output capacitor voltage waveform 212a may include an output voltage values, vo, the output current waveform 212b may include output current values io, and the control phase shift waveform 212c may include phase shift values, ?. The output voltage values, vo, may be carefully regulated to a steady voltage 60 V. Furthermore, the control phase shift waveform 212c may include a phase shift angle, denoted as ?, which is approximately 14 degrees. This phase shift angle may be generated by a controller unit shown in FIG. 3.
[0064] FIG. 3 is a diagram of an exemplary controller unit 300, in accordance with an embodiment of the present disclosure. The controller unit 300 may be communicatively coupled to the converter 100 shown in FIG. 6. The controller unit 300 may include voltage and current control loops 301, an optimization module 302, a pulse width modulator 304 hosted on a micro-controller unit MCU. The voltage and current control loops 301 may include a second-order generalized-integrator (SOGI) filter 306, a voltage controller 308, a current controller 310, a load voltage controller 312, and a load current controller 314. The SOGI filter 306, the voltage controller 308, the current controller 310, the load voltage controller 312, and the load current controller 314 may be configured to determine control parameters corresponding to the primary stage 104a, and the secondary stage 104b. The control parameters may include, but not limited to, a duty ratio of the primary stage dpri, a duty ratio of the secondary stage dsec, a control phase shift between a primary voltage v11’ associated with the primary stage 104a, a secondary voltage v22’ associated with the secondary stage, a switching frequency fsw, a dead time of the primary stage 104a Tdpri, and a dead time of the secondary stage, and the like. The power flow may be controlled by varying the phase shift between a primary bridge voltage waveform and a secondary bridge voltage waveform, varying the duty ratio dsec of the secondary bridge voltage waveform (applicable when using the secondary full bridge), or varying switching frequency of the converter 100 shown in FIG. 3. The switching frequency fsw may be dynamically varied through the implementation of the optimization module 302. The optimization module 302 may be configured to send commands to the pulse width modulator 304 for generating appropriate switching pulses. The switching frequency fsw may be varied by modifying specific registers within the microcontroller unit (MCU). The pulse width modulator 304 may be configured to generate a carrier waveform. The carrier waveform may be used for pulse width modulation based on a switching pattern.
[0065] The optimization module 302 may be configured to modulate determined control parameters corresponding to the primary stage 104a, and the secondary stage 104b and generate control signals for switches Sa, Sb, Sc, Sd, Saux, S1, S2, S3, S4, S5, S6, S7, S8. Gate pulses are brief electrical signals or voltage waveforms used to control the switching of switches Sa, Sb, Sc, Sd, Saux, S1, S2, S3, S4, S5, S6, S7, S8. These pulses determine when these switches Sa, Sb, Sc, Sd, Saux, S1, S2, S3, S4, S5, S6, S7, S8 turn ON or OFF. The first set of switches Sa, Sb, Sc, Sd enable synchronous rectification based on grid voltage vg. The optimization module 302 and a switching pattern may be configured to control the switches Saux, S1, S2, S3, S4, S5,S6, S7, S8 in the primary stage 104a and the secondary stage 104b based on the generated control signals for correcting Power Factor (PF) of the converter 100. The controller unit 300 may be configured to generate one of a desired reference voltage level and a desired reference current level to allow regulation of a range of DC output voltages and currents at a converter output port.
[0066] FIG. 4 is a circuit diagram 400 of an exemplary single-phase module 510a, 510b, 510c shown in FIG. 5A – FIG. 5D for an electric vehicle charging application, in accordance with an embodiment of the present disclosure. The single-phase module configuration 400 may include the converter 100. The converter 100 may include a first AC terminal 402, a second AC terminal 404, a DC positive terminal 406, and a DC negative terminal 408. The converter 100 is a pivotal part of the configuration and is responsible for converting and regulating the electric power. The converter 100 may be connected as follows: the first AC terminal 402 may be connected to the line of a single phase alternating current (AC) power source. The second AC terminal 404 may be connected to the neutral of the single-phase AC power source. The positive DC terminal 406 may be connected to the positive terminal of a battery load and the negative DC terminal 408 may be connected to the negative terminal of the battery load.
[0067] FIG. 5A is an exemplary block diagram 500a of a three-phase star configuration with a single output for fast charging, in accordance with an embodiment of the present disclosure. The three-phase star configuration 500a may include a plurality of single phase modules 510a, 510b, 510c (for example, single phase modules 1, 2, 3). In this configuration the plurality of converters 510a, 510b, 510c may be connected to a multi-phase AC supply through respective input ports 502a, 502b, 502c, 502d, 502e, 502f. The output ports 506a, 506b, 506c, 506d, 506e, 506f of the plurality of modules 510a, 510b, 510c may be paralleled and connected to a single load circuit 508. The load circuit 508 may include, but not limited to, a battery load to store or utilize the electrical power as needed.
[0068] FIG. 5B is an exemplary block diagram 500b of a three-phase star configuration with multiple output ports for normal charging, in accordance with an embodiment of the present disclosure. The three-phase star configuration 500b may include a plurality of single phase modules 510a, 510b, 510c. In this configuration the plurality of converters 510a, 510b, 510c may be connected to a multi-phase AC supply through respective input ports 502a, 502b, 502c, 502d, 502e, 502f in a star configuration. The plurality of modules may be connected to a plurality of load circuits 508a, 508b, 508c through respective output ports 506a, 506b, 506c, 506d, 506e, 506f.
[0069] FIG. 5C is an exemplary block diagram 500c of three-phase DELTA configuration with a single output for fast charging, in accordance with an embodiment of the present disclosure. Each of the plurality of converters modules 510a, 510b, 510c may be connected to a single load circuit 508 via respective plurality of converter output ports 506a, 506b, 506c, 506d, 506e, 506f, where each of the output ports are paralleled. In this configuration the plurality of converters 510a, 510b, 510c may be connected to a multi-phase AC supply through respective input ports 502a, 502b, 502c, 502d, 502e, 502f in a DELTA configuration.
[0070] FIG. 5D is an exemplary block diagram 500d of three-phase DELTA configuration with multiple outputs for normal charging, in accordance with an embodiment of the present disclosure. In this multi-phase module configuration 500d, the plurality of converters 510a, 510b, 510c may connect with the plurality of phases of a multi-phase AC supply voltage in a DELTA configuration. The plurality of modules may be connected to a plurality of load circuits 508a, 508b, 508c through respective output ports 506a, 506b, 506c, 506d, 506e, 506f.
[0072] In the single-phase module 510a or 510b or 510c, power factor correction involves actively manipulating the current iL, that flows through the primary inductor L 114. This manipulation may be performed to shape the inductor current, iL, into a rectified sinusoidal waveform which is phase-aligned with the rectified grid voltage |vg|. As a result of this clever shaping, the grid current ig, may include the sinusoidal waveform that perfectly synchronizes with the grid voltage, vg. This synchronization of the current and voltage waveforms enables effective correction of the power factor in the single-phase module 510a or 510b or 510c.
[0073] In a three-phase module, as illustrated in Fig. 5A-FIG. 5D, the approach to power factor correction involves shaping the current of each individual single-phase module 510a, 510b, 510c. The power factor correction techniques may be applied to each of the single-phase module 510a, 510b, 510c. The current waveforms may align with respective grid voltages enables the effective correction of the power factor in the entire three-phase module 510a, 510b, 510c.
[0074] FIG. 6 is an overall architecture diagram 600 depicting a system for converting alternating current (AC) to direct current (DC) with power factor correction, in accordance with an embodiment of the present disclosure. The system 600 may include the converter 100, the controller unit 300, a plurality of voltage sensors 602, a plurality of current sensors 604, analog to digital converters 606, and a gate drive circuitry 608. The plurality of voltage sensors 602 may be configured to measure a plurality of voltage levels at a plurality of nodes associated with the converter 100. The plurality of current sensors 604 may be configured to measure a plurality of current levels through plurality of circuit elements associated with the converter 100. The controller unit 300 may be communicatively coupled to the converter 100. The controller unit 300 may be configured to receive the measured plurality of voltage levels from the plurality of voltage sensors 602 and the measured plurality of current levels from the plurality of current sensors 604. The controller unit 300 may be configured to generate one of a desired reference voltage level and a desired reference current level to allow regulation of a range of DC output voltages and currents at a converter output port. The controller unit 300 may be configured to determine one or more control parameters corresponding to the primary stage 104a, and the secondary stage 104b. The control parameters may include, but not limited to, a duty ratio of the primary stage 104a, a duty ratio of the secondary stage dsec, and a control phase shift between a primary voltage v11’ associated with the primary stage 104a, and a secondary voltage associated with the secondary stage 104b, a switching frequency fsw, a dead time of the primary stage Tpri 104a, and a dead time of the secondary stage 104b, and the like. The controller unit 300 may be configured to modulate the determined one or more control parameters corresponding to the primary stage 104a, and the secondary stage 104b. The controller unit 300 may be configured to generate a plurality of control signals for the plurality of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d based on the modulated one or more control parameters. The controller unit 300 may be configured to control the plurality of switches in the primary stage 104a and the secondary stage 104b based on the generated plurality of control signals, by using a modulation scheme and the switching pattern, for correcting Power Factor (PF) of the converter 100, the switching pattern is configured to enable soft switching of the plurality of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d. Finally, the plurality of drive circuits (gate drive circuitry) 608 may be configured to apply the generated plurality of control signals at the plurality of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d based on the modulation scheme and the switching pattern.
[0075] According to exemplary embodiment of the present disclosure, various voltage ranges are available based on the specific application requirements. In an embodiment of the present disclosure, a first option may include voltage ranges between 40 to 120 V and is suitable for charging electric two-wheelers and three-wheelers. These types of vehicles typically have lower voltage battery systems. In another embodiment of the present disclosure, a second option may include voltage range is set between 250 to 500 V. This range is ideal for charging four-wheelers, particularly those equipped with a 400 V nominal battery pack. Many modern electric cars may fall within this category. In another embodiment of the present disclosure, a third option may include the voltage range expands to 600 to 1000 V, catering to four-wheelers with a higher 800 V nominal battery pack. Electric vehicles with higher voltage systems, such as some luxury and performance cars, fall into this category. These options may represent distinct voltage ranges tailored to meet the charging needs of different types of electric vehicles. The choice of option depends on the specific application and the voltage characteristics of the electric vehicle battery.
[0076] FIG. 7 is a flow diagram 700 illustrating an exemplary method for converting Alternating Current (AC) to Direct Current (DC) is disclosed, in accordance with embodiment of the present disclosure. At step 702, a plurality of voltage levels and a plurality of current levels measured from a converter 100 are received by a controller unit 300. In an embodiment of the present disclosure, the converter 100 may include a primary stage 104a and a secondary stage 104b. Each stage may include a plurality of switches, and the primary stage 104a is galvanically isolated from the secondary stage 104b using a high-frequency transformer 120.
[0077] At step 704, one of a desired reference voltage level and a desired reference current level is generated by the controller unit 300 to allow regulation of a range of DC output voltages and currents at a converter output port.

[0078] At step 706, one or more control parameters corresponding to the primary stage 104a, and the secondary stage 104b is determined via the controller unit 300. In an embodiment of the present disclosure, the one or more control parameters include a duty ratio of the primary stage 104a, dpri, a duty ratio of the secondary stage 104b, dsec, and a control phase shift between a primary voltage v11’ associated with the primary stage 104a, and a secondary voltage associated with the secondary stage 104b, a switching frequency, a dead time of the primary stage 104a, and a dead time of the secondary stage 104b. In an embodiment of the present disclosure, the one or more control parameters corresponding to the primary stage 104a, and the secondary stage 104b may include measuring an AC supply voltage, a clamp capacitor voltage, and an inductor current corresponding to the primary stage 104a and an output voltage, and an output current corresponding to the secondary stage 104b, generating a voltage set point for the clamp capacitor voltage and a reference current pattern as a function of the AC supply voltage, generating a voltage setpoint for the DC output voltage at a converter output port, and determining a duty ratio of the primary stage dpri 104a, a duty ratio of the secondary stage dsec 104b, a phase shift between the primary voltage v11’ associated with the primary stage 104a, and the secondary voltage associated with the secondary stage 104b, a switching frequency, a dead time of the primary stage 104a, and a dead time of the secondary stage 104b.
[0079] According to an exemplary embodiment of the present disclosure, a clamp capacitor voltage of a clamp capacitor 113 is maintained above a threshold level. A current waveform of a primary inductor 114 is modulated to track a desired pattern for correcting a power factor. In an embodiment of the present disclosure, a second switches S1 108a, S2 108b, S3 108c, S4 108d of the high-frequency H-bridge 103 of the primary stage 104a is switched in synchronization with a controlled auxiliary switch Saux 112 to apply a plurality of voltage vectors across the primary inductor 114. In an embodiment of the present disclosure, a time interval associated with the plurality of voltage vectors is modified and an induction current waveform is modulated to track the desired pattern based on the modified time interval.
[0080] At step 708, determined one or more control parameters corresponding to the primary stage 104a, and the secondary stage 104b is modulated by the controlled unit 300.
[0081] At step 710, a plurality of control signals is generated by the controller unit 300 for the plurality of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d based on the modulated one or more control parameters.
[0082] At step 712, the plurality of switches Sa 106a, Sb 106b, Sc 106c, Sd 106d, Saux 112, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, in the primary stage 104a and the secondary stage 104b is controlled by the controller unit 300 through the plurality of drive circuits 608 based on generated plurality of control signals. In an embodiment of the present disclosure, the plurality of switches S1 108a, S2 108b, S3 108c, S4 108d, Saux 112 is controlled by using a modulation scheme and a switching pattern, for correcting a power factor (PF) of the converter 100. The switching pattern is configured to enable soft switching of the plurality of switches. The modulation scheme and the switching pattern are determined for the converter 100. The second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d of the high-frequency H-bridge 103 in the primary stage 104a are modulated in synchronization with the controlled auxiliary switch Saux 112 for power factor correction. The voltage across each of the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d is clamped within the high-frequency H-bridge 103 of the primary stage 104a. The third set of controlled switches S5 110a, S6 110b, S7 110c, S8 110d is modulated in the secondary stage 104b based on the determined modulation scheme and the switching pattern, for regulating a range of DC output voltage and currents. In an embodiment of the present disclosure, the controlled auxiliary switch Saux 112, the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d of the high-frequency H-bridge 103 of the primary stage 104a and the third set of controlled switches S5 110a, S6 110b, S7 110c, S8 110d of the secondary stage 104b are modulated to allow one of a positive voltage, a negative voltage, and a zero voltage to be controllably applied across the nodes 1-1’ of the high-frequency H-bridge 103 and secondary winding of the high-frequency transformer 120. The high-frequency transformer 120 is configured to provide galvanic isolation between the primary stage 104a and the secondary stage 104b.
[0083] In an embodiment of the present disclosure, the controlled auxiliary switch Saux 112, the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d of the high-frequency H-bridge 103 of the primary stage 104a, and the third set of controlled switches S5 110a, S6 110b, S7 110c, S8 110d of the secondary stage 104b are operated in a soft switching mode. Each of the controlled auxiliary switch Saux 112, the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d and the third set of controlled switches S5 110a, S6 110b, S7 110c, S8 110d are configured to be softly activated using the switching pattern. In an embodiment of the present disclosure, the voltage across each of the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d is clamped within the high-frequency H-bridge 103 of the primary stage 104a may include, creating a path for the inductor current when at least one of the second set of controlled switches S1 108a, S2 108b, S3 108c, S4 108d in the high-frequency H-bridge 103 of the primary stage 104a are turning OFF.
[0084] Various embodiments of the system 100 and method for converting Alternating Current (AC) to Direct Current (DC) as described above provides effective power factor correction, enhancing the efficiency of AC to DC conversion. The system 100 allows regulation of a wide range of DC output voltages and powers, making it adaptable for various applications. The system 100 employs a high-frequency transformer 120 to obtain galvanic isolation between a primary stage 104a and a secondary stage 104b, enhancing safety and performance. Voltage and current sensors 602, 604, coupled with a controller unit 300, enable precise monitoring and control of the conversion process. Further, the system 100 determines control parameters for both primary and secondary stages, including duty ratios, phase shift, switching frequency, and dead times, to optimize performance. A modulation scheme and switching pattern is employed to enable soft switching of the switches, reducing switching losses and improving efficiency. Furthermore, the system 100 modulates voltage vectors across the inductor 114, to modulate the current through inductor 114 to track a desired pattern for power factor correction, ensuring an efficient conversion process. The system 100 is suitable for single-phase and multi-phase module configurations, making it adaptable for different electrical systems. A clamp circuit 116 helps prevent voltage overshoots across the switches S 108. In addition, auxiliary switch Saux 112, S108 and S 110 allow control over positive, negative and zero voltage applied across nodes 1-1’ of primary H-bridge 103 and transformer secondary winding 120. The system 100 utilizes soft-switching schemes to reduce switching losses and enhance system efficiency.
[0085] The embodiments herein can comprise hardware and software elements. The embodiments that are implemented in software include but are not limited to, firmware, resident software, microcode, etc. The functions performed by various modules described herein may be implemented in other modules or combinations of other modules. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can comprise, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
[0086] The illustrated steps are set out to explain the exemplary embodiments shown, and it should be anticipated that ongoing technological development will change the manner in which particular functions are performed. These examples are presented herein for purposes of illustration, and not limitation. Further, the boundaries of the functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternative boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Alternatives (including equivalents, extensions, variations, deviations, etc., of those described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternatives fall within the scope and spirit of the disclosed embodiments. Also, the words “comprising,” “having,” “containing,” and “including,” and other similar forms are intended to be equivalent in meaning and be open-ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items or meant to be limited to only the listed item or items. It must also be noted that as used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise.
[0087] Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the embodiments of the present invention are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.
, Claims:We claim:
1. A system for converting Alternating Current (AC) to Direct Current (DC), the system comprising:
a converter (100), comprising a primary stage (104a) and a secondary stage (104b), wherein each stage (104a, 104b) comprises a plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, Saux 112), wherein the converter (100) is configured to convert Alternating Current (AC) to Direct Current (DC) with power factor correction (PFC) and allow regulation of a range of DC output voltages and powers and wherein the primary stage (104a) is galvanically isolated from the secondary stage (104b) using a high-frequency transformer (120);
a plurality of voltage sensors (602) configured to measure a plurality of voltage levels at a plurality of nodes associated with the converter (100);
a plurality of current sensors (604) configured to measure a plurality of current levels through plurality of circuit elements associated with the converter (100); and
a controller unit (300), communicatively coupled to the converter (100), wherein the controller unit is (300) configured to:
receive the measured plurality of voltage levels from the plurality of voltage sensors (602) and the measured plurality of current levels from the plurality of current sensors (604);
generate one of a desired reference voltage level and a desired reference current level to allow regulation of a range of DC output voltages and currents at a converter output port;
determine one or more control parameters corresponding to the primary stage (104a), and the secondary stage (104b), wherein the control parameters comprise at least one of a duty ratio of the primary stage (104a), a duty ratio of the secondary stage (104b), and a control phase shift between a primary voltage (v11’) associated with the primary stage (104a), and a secondary voltage (v22’) associated with the secondary stage (104b), a switching frequency, a dead time of the primary stage (104a), and a dead time of the secondary stage (104b);
modulate the determined one or more control parameters corresponding to the primary stage (104a), and the secondary stage (104b);
generate a plurality of control signals for the plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, Saux 112) based on the modulated one or more control parameters; and
control the plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, Saux 112) in the primary stage (104a) and the secondary stage (104b) based on the generated plurality of control signals, by using a modulation scheme and a switching pattern, for correcting Power Factor (PF) of the converter (100), wherein the switching pattern is configured to enable soft switching of the plurality of switches (S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, Saux 112); and
a plurality of drive circuits (608) configured to apply the generated plurality of control signals at the plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, Saux 112), based on the modulation scheme and the switching pattern.

2. The system as claimed in claim 1, wherein the converter (100) comprises:
the primary stage (104a), configured to correct the Power Factor (PF), comprising:
a line-frequency H-bridge (102) comprising:
a first set of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d), electrically interfaced with an AC supply voltage, wherein the first set of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d) are configured to operate in a range of line frequency; and
a primary inductor (114) connected in series between the first set of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d) and a clamp circuit (116);
the clamp circuit (116) comprising:
a controlled auxiliary switch Saux (112) connected in series with a clamp capacitor (113), wherein the clamp circuit (116) is electrically connected across a high-frequency H-bridge (103), and wherein the clamp circuit (116) is configured to clamp a voltage across each of a second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) within the high-frequency H-bridge (103) of the primary stage (104a); and
the high-frequency H-bridge (103) comprising:
the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) electrically connected across the clamp circuit (112), wherein the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) are configured to operate in a range of frequency higher than the range of line frequency;
the high-frequency transformer (120) electrically coupled to the primary stage (104a) and the secondary stage (104b), wherein the high-frequency transformer (120) is configured to provide a galvanic isolation; and
the secondary stage (104b) comprising:
a third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d) electrically interfaced with a secondary winding of the high-frequency transformer (112), and a plurality of capacitors (122, 124a, 124b), wherein the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d) are configured to control at least one of an output current and a DC output voltage.

3. The system as claimed in claim 2, wherein the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) are modulated in synchronization with the controlled auxiliary switch Saux (112) for the PF correction.

4. The system as claimed in claim 2, wherein the voltage of the clamp capacitor (113) is maintained above a threshold level and wherein the current waveform of the primary inductor (114) is modulated to track a desired pattern for correcting the PF.

5. The system as claimed in claim 4, wherein for modulating the current waveform of the primary inductor (114) to track the desired pattern, the primary stage (104a) is configured to:
switch the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) in synchronization with the controlled auxiliary switch Saux (112) using a pulse width modulation technique to apply a plurality of voltage vectors across the primary inductor (114);
modify a time interval associated with the plurality of voltage vectors;
modulate the current waveform of the primary inductor (114) to track the desired pattern based on the modified time interval; and
vary a pulse width of the primary voltage (v11’) associated with the primary stage (104a).

6. The system as claimed in claim 2, wherein for clamping the voltage across each of the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) within the high-frequency H-bridge (103) of the primary stage (104a), the clamp circuit (116) is configured to create a path for the current in the primary inductor (114) when at least one of the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) in the high-frequency H-bridge (103) are turning OFF.

7. The system as claimed in claim 2, wherein the controlled auxiliary switch Saux (112) and the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) in the primary stage (104a) allow one of a positive voltage, a negative voltage, and a zero voltage to be controllably applied across nodes 1-1’ of the high-frequency H-bridge (103).

8. The system as claimed in claim 2, wherein the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d) of the secondary stage (104b) allow one of a positive voltage, a negative voltage, and a zero voltage to be controllably applied across the corresponding secondary winding of the high-frequency transformer (120).

9. The system as claimed in claim 2, wherein the controlled auxiliary switch Saux (112), the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) in the primary stage (104a) and the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d) of the secondary stage (104b) are configured to operate in a soft switching mode, wherein each of controlled auxiliary switch Saux (112), the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) and the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d) are configured to be softly activated using a switching pattern.

10. The system as claimed in claim 2, wherein the range of line frequency is between (45 – 65 Hz).

11. The system as claimed in claim 2, wherein the converter (100) is configured for correcting the power factor in a single-phase module (504a, 504b, 504c) configuration.

12. The system as claimed in claim 2, wherein the converter is configured for correcting the power factor in a multi-phase module (504a, 504b, 504c) configuration.

13. The system as claimed in claim 12, wherein in the multi-phase module (504a, 504b, 504c) configuration, a plurality of converters (502a, 502b, 502c) are connected to plurality of phases of a multi-phase AC supply voltage, and at least one of a single load circuit (508) via a plurality of converter output ports (506a, 506b, 506c, 506d, 506e, 506f) and a plurality of load circuits (508a, 508b, 508c) at the plurality of converter output ports (506a, 506b, 506c, 506d, 506e, 506f) using at least one of a star configuration and a delta configuration at a converter input (118).

14. The system as claimed in claim 13, wherein each of the converter output ports (506a, 506b, 506c, 506d, 506e, 506f) are paralleled with each other.

15. The system as claimed in claim 13, wherein each of the plurality of converters (502a, 502b, 502c) are connected to plurality of load circuits via respective plurality of converter output ports (506a, 506b, 506c, 506d, 506e, 506f).

16. A method for converting Alternating Current (AC) to Direct Current (DC), the method comprising:
receiving, by a controller unit (300), a plurality of voltage levels and a plurality of current levels measured from a converter (100), wherein the converter (100) comprises a primary stage (104a), and a secondary stage (104b), wherein each stage (104a, 104b) comprises a plurality of switches, and wherein the primary stage (104a) is galvanically isolated from the secondary stage (104b) using a high-frequency transformer (120);
generating, by the controller unit (300), one of a desired reference voltage level and a desired reference current level to allow regulation of a range of DC output voltages and currents at a converter output port;
determining, by the controller unit (300), one or more control parameters corresponding to the primary stage (104a), and the secondary stage (104b), wherein the control parameters comprise at least one of a duty ratio of the primary stage (104a), a duty ratio of the secondary stage (104b), and a control phase shift between a primary voltage (v11’) associated with the primary stage (104a), and a secondary voltage associated with the secondary stage (104b), a switching frequency, a dead time of the primary stage (104a), and a dead time of the secondary stage (104b);
modulating, by the controller unit (300), the determined one or more control parameters corresponding to the primary stage (104a), and the secondary stage (104b);
generating, by the controller unit (300), a plurality of control signals for the plurality of switches based on the modulated one or more control parameters; and
controlling, by the controller unit (300) through the plurality of drive circuits, the plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, Saux 112) in the primary stage (104a) and the secondary stage (104b) based on the generated plurality of control signals, by using a modulation scheme and a switching pattern, for correcting a Power Factor (PF) of the converter, wherein the switching pattern is configured to enable soft switching of the plurality of switches (S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, Saux 112).

17. The method as claimed in claim 16, wherein determining the one or more control parameters corresponding to the primary stage (104a), and the secondary stage (104b) comprises:
measuring an AC supply voltage, a clamp capacitor voltage, and an inductor current corresponding to the primary stage (104a) and an output voltage, and an output current corresponding to the secondary stage (104b);
generating a voltage set point for the clamp capacitor voltage and a reference current pattern as a function of the AC supply voltage;
generating a voltage setpoint for the DC output voltage at a converter output port (506a, 506b, 506c, 506d, 506e, 506f); and
determining a duty ratio of the primary stage (104a), a duty ratio of the secondary stage (104b), a phase shift between the primary voltage (v11’) associated with the primary stage (104a), and the secondary voltage associated with the secondary stage (104b), a switching frequency, a dead time of the primary stage (104a), and a dead time of the secondary stage (104b).

18. The method as claimed in claim 16, wherein controlling the plurality of switches (Sa 106a, Sb 106b, Sc 106c, Sd 106d, S1 108a, S2 108b, S3 108c, S4 108d, S5 110a, S6 110b, S7 110c, S8 110d, Saux 112) in the primary stage (104a) and the secondary stage (104b) with the generated plurality of control signals by using the modulation scheme and the switching pattern for correcting the power factor of the converter (100) comprises:
determining the modulation scheme and the switching pattern for the converter (100);
modulating the second set of controlled switches based on the determined modulation scheme and the switching pattern, wherein the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) in the primary stage (104a) are modulated in synchronization with the controlled auxiliary switch Saux (112) for power factor correction;
clamping the voltage across each of the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) within the high-frequency H-bridge (103) of the primary stage (104a);
modulating the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d) in the secondary stage (104b) based on the determined modulation scheme and the switching pattern, for regulating a range of DC output voltage and currents;
modulating the controlled auxiliary switch (Saux 112), the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) of the primary stage (104a), and the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d) of the secondary stage (104b) to allow one of a positive voltage, a negative voltage, and a zero voltage to be controllably applied across nodes 1-1’ of the high-frequency H-bridge (103) and secondary winding of the high-frequency transformer (120), wherein the high-frequency transformer (120) is configured to provide galvanic isolation between the primary stage (104a) and the secondary stage (104b);
operating the controlled auxiliary switch (Saux 112), the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) of the primary stage (104a), and the third set of controlled switches (S5 110a, S6 11-b, S7 110c, S8 110d)of the secondary stage (104b) in a soft switching mode, wherein each of the controlled auxiliary switch (Saux 112), the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) and the third set of controlled switches (S5 110a, S6 110b, S7 110c, S8 110d) are configured to be softly activated using the switching pattern.

19. The method as claimed in claim 18, wherein clamping the voltage across each of the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) within the high-frequency H-bridge (103) of the primary stage (104a) comprises:
creating a path for the inductor current when at least one of the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) in the high-frequency H-bridge (103) of the primary stage (104a) are turning OFF.

20. The method as claimed in claim 16, further comprising:
maintaining a clamp capacitor voltage of the clamp capacitor (113) above a threshold level and modulating a current waveform of a primary inductor (114) to track a desired pattern for correcting the PF;
switching the second set of controlled switches (S1 108a, S2 108b, S3 108c, S4 108d) of the high-frequency H-bridge (103) of the primary stage (104a) in synchronization with the controlled auxiliary switch Saux (112) to apply a plurality of voltage vectors across the primary inductor (114);
modifying a time interval associated with the plurality of voltage vectors; and
modulating the inductor current waveform to track the desired pattern based on the modified time interval.
Dated this 28th day of November 2023

Sanath M V
Patent Agent (IN/PA- 5004)
Agent for the Applicant