Claims:1. A system for drift adjustment in a timer, the system comprising:
a first computing element comprising a first timer configured to run at a first pre-defined frequency;
a second computing element comprising a second timer configured to run at a second pre-defined frequency;
a scheduling device in communication with the first computing element and the second computing element, the scheduling device comprising one or more processors, wherein the one or more processors operatively coupled with memory, the memory storing instructions executable by the one or more processors to:
receive a set of first data packets pertaining to a request raised from the first computing element;
transmit the received set of first data packets to the second computing element, wherein the second timer gets actuated in response to receipt of the transmitted set of first data packets;
obtain a set of second data packets pertaining to completion of a pre-defined count at the second timer, wherein the obtained set of second data packets are transmitted to the first computing element; and
wherein based on the set of second data packets, the first computing element carries out an adjustment in any drift occurred in timing of the first timer.
2. The system as claimed in claim 1, wherein in response to receipt of the transmitted set of second data packets, the first computing element generates a set of third data packets pertaining to an acknowledgment of the receipt of the transmitted set of second data packets.
3. The system as claimed in claim 1, wherein the first timer and the second timer are started simultaneously.
4. The system as claimed in claim 2, wherein the first timer is reset based on the receipt of the set of second data packets, and after resetting the first timer, the processing element acknowledges programmable logic element, embedded in the second computing element, through third set of packets.
5. The system as claimed in claim 1, wherein the scheduling device acquires a timestamp each time a set of first data packets are received from the first computing element and when any of the first timer and the second timer completes its count.
6. The system as claimed in claim 1, wherein the second pre-defined frequency is configured to be an integral multiple of the first pre-defined frequency.
7. The system as claimed in claim 1, wherein the first computing element comprises any of HR (High Resolution) timer and HPET (High Precision Event Timer) timer.
8. The system as claimed in claim 1, wherein the system comprises a communicating interface operatively coupled with the scheduling device, the first computing element, and the second computing element, and configured to communicatively couple the scheduling device with the first computing element and the second computing element.
9. The system as claimed in claim 1, wherein the communicating interface is equipped with a custom communication protocol that is implemented using any or a combination of LPC (low pin count), GPIO (general purpose input output) module, serial UART (universal asynchronous receiver-transmitter) interface, PCIe (peripheral component interconnect express), and Ethernet.
10. A method for drift adjustment in a timer, the method comprising:
receiving, at a scheduling device, a set of first data packets pertaining to a request raised from a first computing element comprising a first timer configured to run at a first pre-defined frequency;
transmitting, at the scheduling device, the received set of first data packets to a second computing element comprising a second timer configured to run at a second pre-defined frequency, wherein the second timer gets actuated in response to receipt of the transmitted set of first data packets;
obtaining, at the scheduling unit, a set of second data packets pertaining to completion of a pre-defined count at the second timer, wherein the obtained set of second data packets are being transmitted to the first computing element; and
wherein based on the set of second data packets, an adjustment in any drift occurred in timing of the first timer is being carried out by the first computing element.
, Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to the manipulation of timers. In particular, the present disclosure relates to a system and method for drift adjustment in a timer in a non-real time operating environment.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Time critical applications used in embedded systems, predominantly work with bare metal software where no operating system is employed. As the complexity of the embedded system increases with multi core processors, multiple interfaces and multiple applications, it becomes necessary and prudent to use an operating system. Operating system is associated with a scheduler, which schedules various tasks that are to be executed. In time critical applications, real time operating systems are used to control the timing of such applications.
[0004] Real time operating systems are very expensive. Also, individual drivers for various peripherals are to be procured separately for the real time operating systems like VxWorks, Lynx etc. Hence, non-real time operating systems are used in most of the embedded systems.
[0005] Non real time operating systems use software timers or processing element’s internal hardware-timers for time critical applications. Applications generally run on user pace and the timers can be controlled from the kernel space. The time critical applications running on user space, initiate/configure the timer and wait for the timer expiry intimation. Though the internal timers of the processing element generate the timer expiry intimation accurately, and the same may be returned to the timer application running in the user space with a delay due to operating system overheads such as scheduler and process priority overheads. Subsequently, the initiation of next timer cycle gets delayed. After few milliseconds, the drift in timing due to the accumulated accuracy errors over a period of time exceeds the acceptable limits for critical applications. It is mandatory to adjust timing interval based on timing data from a substantially accurate source.
[0006] There is, therefore, a requirement in the art for to provide an efficient and economically feasible solution to mitigate above-mentioned problems, and for enabling adjustment in any drift occurred in the timer.

OBJECTS OF THE PRESENT DISCLOSURE
[0007] A general object of the present disclosure is to provide a smart, economically feasible, and efficient system and method for enabling adjustment in any drift occurred in a timer.
[0008] Another object of the present disclosure is to provide a system and method for adjusting drift in the timing in a non-real time operating system environment using HPET and HRT internal timers of x86 processing elements in coherence with the hardware timers on programmable logic element in a non-real time operating systems.
[0009] Another object of the present disclosure is to provide a system and method for high resolution time out generation in the kernel space.
[0010] Another object of the present disclosure is to provide a system and method to adjust the accumulated timing drift errors due to context switching from the kernel space to user space scheduling delay at random time intervals.
[0011] Another object of the present disclosure is to provide a system and method equipped with custom protocol to manage interrupt chain between processing element and programmable logic element for timing initiation and request closure.

SUMMARY
[0012] Aspects of the present disclosure relates, in general, to the manipulation of timers. In particular, the present disclosure relates to a system and method for drift adjustment in a timer in a non-real time operating environment.
[0013] An aspect of the present disclosure pertains to an efficient and cost-effective system for drift adjustment in a timer, the system comprising: a first computing element comprising a first timer configured to run at a first pre-defined frequency; a second computing element comprising a second timer configured to run at a second pre-defined frequency; a scheduling device in communication with the first computing element and the second computing element, the scheduling device comprising one or more processors, wherein the one or more processors operatively coupled with memory, the memory storing instructions executable by the one or more processors to: receive a set of first data packets pertaining to a request raised from the first computing element; transmit the received set of first data packets to the second computing element, wherein the second timer gets actuated in response to receipt of the transmitted set of first data packets; obtain a set of second data packets pertaining to completion of a pre-defined count at the second timer, wherein the obtained set of second data packets are transmitted to the first computing element; and wherein based on the set of second data packets, the first computing element carries out an adjustment in any drift occurred in timing of the first timer.
[0014] In an aspect, in response to receipt of the transmitted set of second data packets, the first computing element generates a set of third data packets pertaining to an acknowledgment of the receipt of the transmitted set of second data packets.
[0015] In an aspect, the first timer and the second timer are started simultaneously.
[0016] In an aspect, the first timer is reset based on the receipt of the set of second data packets, after resetting the first timer, processing element acknowledges programmable logic element through third set of packets.
[0017] In an aspect, the scheduling device acquires a timestamp each time a set of first data packets are received from the first computing element and when any of the first timer and the second timer completes its count.
[0018] In an aspect, the second pre-defined frequency is configured to be an integral multiple of the first pre-defined frequency.
[0019] In an aspect, the first computing element comprises any of HR (High Resolution) timer and HPET (High Precision Event Timer) timer.
[0020] In an aspect, the second computing element comprises programmable logic element.
[0021] In an aspect, the system comprises a communicating interface operatively coupled with the scheduling device, the first computing element, and the second computing element, and configured to communicatively couple the scheduling device with the first computing element and the second computing element.
[0022] In an aspect, the communicating interface may be equipped with a custom communication protocol that is implemented using any or a combination of LPC (low pin count), GPIO (general purpose input output) module, serial UART (universal asynchronous receiver-transmitter) interface, PCIe (peripheral component interconnect express), and Ethernet.
[0023] Another aspect of the present disclosure pertains to a method for drift adjustment in a timer, the method comprising: receiving, at a scheduling device, a set of first data packets pertaining to a request raised from a first computing element comprising a first timer configured to run at a first pre-defined frequency; transmitting, at the scheduling device, the received set of first data packets to a second computing element comprising a second timer configured to run at a second pre-defined frequency, wherein the second timer gets actuated in response to receipt of the transmitted set of first data packets; obtaining, at the scheduling unit, a set of second data packets pertaining to completion of a pre-defined count at the second timer, wherein the obtained set of second data packets are being transmitted to the first computing element; and wherein based on the set of second data packets, an adjustment in any drift occurred in timing of the first timer is being carried out by the first computing element.
[0024] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.
[0025] Within the scope of this application it is expressly envisaged that the various aspects, embodiments, examples and alternatives set out in the preceding paragraphs, in the claims and/or in the following description and drawings, and in particular the individual features thereof, may be taken independently or in any combination. Features described in connection with one embodiment are applicable to all embodiments, unless such features are incompatible.

BRIEF DESCRIPTION OF DRAWINGS
[0026] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.
[0027] FIG. 1 illustrates an exemplary schematic network architecture of the proposed system, to elaborate upon its working in accordance with an embodiment of the present disclosure.
[0028] FIG. 2 illustrates a flow diagram depicting internal application timer running in processing element, in accordance with an embodiment of the present disclosure.
[0029] FIG. 3 illustrates a flow diagram depicting working of external timer in programmable logic element, in accordance with an embodiment of the present disclosure.
[0030] FIG. 4 illustrates a schematic diagram depicting relationship between external timer in programmable logic element and processing element application timer, in accordance with an embodiment of the present disclosure.
[0031] FIG. 5 illustrates a graphical representation depicting extended timing drift due to multiple interrupts.
[0032] FIG. 6 illustrates a graphical representation depicting compensated time drifts and multiple interrupts.
[0033] FIG. 7 illustrates a flow diagram of the proposed method, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0034] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0035] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability.
[0036] Embodiments of the present disclosure relates, in general, to the manipulation of timers. In particular, the present disclosure relates to a system and method for drift adjustment in a timer in a non-real time operating environment.
[0037] According to an embodiment, the present disclosure pertains to an efficient and cost-effective system for drift adjustment in a timer, the system comprising: a first computing element comprising a first timer configured to run at a first pre-defined frequency; a second computing element comprising a second timer configured to run at a second pre-defined frequency; a scheduling device in communication with the first computing element and the second computing element, the scheduling device comprising one or more processors, wherein the one or more processors operatively coupled with memory, the memory storing instructions executable by the one or more processors to: receive a set of first data packets pertaining to a request raised from the first computing element; transmit the received set of first data packets to the second computing element, wherein the second timer gets actuated in response to receipt of the transmitted set of first data packets; obtain a set of second data packets pertaining to completion of a pre-defined count at the second timer, wherein the obtained set of second data packets are transmitted to the first computing element; and wherein based on the set of second data packets, the first computing element carries out an adjustment in any drift occurred in timing of the first timer.
[0038] In an embodiment, in response to receipt of the transmitted set of second data packets, the first computing element generates a set of third data packets pertaining to an acknowledgment of the receipt of the transmitted set of second data packets.
[0039] In an embodiment, the first timer and the second timer are started simultaneously.
[0040] In an embodiment, the first timer is reset based on the receipt of the set of second data packets , after resetting the first timer, processing element acknowledges programmable logic element through third set of data packets..
[0041] In an embodiment, the scheduling device acquires a timestamp each time a set of first data packets are received from the first computing element and when any of the first timer and the second timer completes its count.
[0042] In an embodiment, the second pre-defined frequency is configured to be an integral multiple of the first pre-defined frequency.
[0043] In an embodiment, the first computing element comprises any of HR (High Resolution) timer and HPET (High Precision Event Timer) timer.
[0044] In an embodiment, the second computing element comprises programmable logic element.
[0045] In an embodiment, the system comprises a communicating interface operatively coupled with the scheduling device, the first computing element, and the second computing element, and configured to communicatively couple the scheduling device with the first computing element and the second computing element, wherein the communicating interface is implemented using any or a combination of LPC ( Low Pin Count), GPIO (general purpose input output) module, serial UART (universal asynchronous receiver-transmitter) interface, PCIe (peripheral component interconnect express), and Ethernet.
[0046] In an embodiment, the communicating interface can be equipped with a custom communication protocol that is implemented using any or a combination of LPC (low pin count), GPIO (general purpose input output) module, serial UART (universal asynchronous receiver-transmitter) interface, PCIe (peripheral component interconnect express), and Ethernet.
[0047] According to another embodiment, the present disclosure pertains to a method for drift adjustment in a timer, the method comprising: receiving, at a scheduling device, a set of first data packets pertaining to a request raised from a first computing element comprising a first timer configured to run at a first pre-defined frequency; transmitting, at the scheduling device, the received set of first data packets to a second computing element comprising a second timer configured to run at a second pre-defined frequency, wherein the second timer gets actuated in response to receipt of the transmitted set of first data packets; obtaining, at the scheduling unit, a set of second data packets pertaining to completion of a pre-defined count at the second timer, wherein the obtained set of second data packets are being transmitted to the first computing element; and wherein based on the set of second data packets, an adjustment in any drift occurred in timing of the first timer is being carried out by the first computing element.
[0048] FIG. 1 illustrates an exemplary schematic network architecture of the proposed system, to elaborate upon its working in accordance with an embodiment of the present disclosure.
[0049] According to an embodiment, the proposed system 100 (interchangeably referred to as system 100, herein) includes a first computing element 102 (interchangeably referred to as computing element 102, and processing element 102, herein) that can further include a first timer 104 (interchangeably referred to as timer 104, herein) configured to run at a first pre-defined frequency.
[0050] In an embodiment, the system 100 includes a second computing element 110 (interchangeably referred to as computing element 110 and Programmable logical element, herein), which in turn can include a second timer 112 (interchangeably referred to as timer 112, herein) configured to run at a second pre-defined frequency.
[0051] In other embodiment, the system 100 includes a scheduling device 106 in communication with the first computing element 102 and the second computing element 110. In another embodiment, the system 100 includes a communicating interface 108 operatively coupled with the scheduling device 106, the first computing element 102, and the second computing element 110, where the communicating interface 108 can be configured to communicatively couple the scheduling device 110 with the first computing element 102 and the second computing element 110.
[0052] In an embodiment, the communicating interface 108 can be equipped with a custom communication protocol that is implemented using any or a combination of LPC (low pin count), GPIO (general purpose input output) module, serial UART (universal asynchronous receiver-transmitter) interface, PCIe (peripheral component interconnect express), and Ethernet.

[0053] In an embodiment, the first computing element 102 can raise a request related to scheduling of a timer while running one or more applications or tools, where a set of first data packets, pertaining to the request raised, can be generated at the first computing element 102. The generated set of first data packets can be transmitted and further can be received by the scheduling device 106.
[0054] In one embodiment, the scheduling device 106 can transmit the received set of first data packets to the second computing element 110, and the second timer 112 can get actuated in response to receipt of the transmitted set of first data packets. In other embodiment, the scheduling device 106 can acquire a timestamp each time a set of first data packets are received from the first computing element 102.
[0055] In an embodiment, the second computing element 110 can generate a set of second data packets pertaining to completion of a pre-defined count at the second timer, where the generated set of second data packets can be obtained by the scheduling device 106, which can further transmit the obtained set of second data packets to the first computing element 102. Further, based on the set of second data packets, the first computing element 102 can carry out an adjustment in any drift occurred in timing of the first timer 104.
[0056] In one embodiment, in response to receipt of the transmitted set of second data packets, the first computing element 102 can generate a set of third data packets pertaining to an acknowledgment of the receipt of the transmitted set of second data packets. In other embodiment, the first timer 102 can be reset based on the receipt of the set of second data packets and, after resetting the first timer, processing element acknowledges programmable logic element through third set of packets.. In other embodiment, the first timer 104 and the second timer 112 can be started simultaneously.
[0057] FIG. 2 illustrates a flow diagram depicting internal application timer running in processing element, in accordance with an embodiment of the present disclosure.
[0058] In an embodiment, the processing element 102 can be equipped with an internal timer 104 (also referred to as processing element timer 104, herein), which can be either hardware or software based. In one embodiment, at block 202, the timer 104 is initiated as one or more tools or applications are started. At block 204, it is checked that whether the timer has expired, i.e. whether the timer has completed a pre-defined first count. In case, the timer is found to be expired, then at block 206, the processing element 102 is interrupted. However, in case, the timer is found not to be expired, at block 208, the expiration of the timer is awaited then after a specific duration, it is again checked at the block 204 whether the timer has expired.
[0059] FIG. 3 illustrates a flow diagram depicting working of external timer in programmable logic element, in accordance with an embodiment of the present disclosure.
[0060] In an embodiment, the processing element 102 can be coupled, at block 302, with an external timer 112, which can be either hardware or software based, through the communication interface, and further the timer can be initiated as one or more tools or applications are started. At block 304, it is checked that whether the timer has expired, i.e. whether the timer has completed a pre-defined count. In case, the timer is found not to be expired, at block 312, the expiration of the timer is awaited, and after a specific duration, it is again checked at the block 304 whether the timer has expired.
[0061] However, in case, the timer is found to be expired, then at block 306, the processing element 102 is interrupted. Further, at block 308, an acknowledgement is transmitted from the processing element 102 to the second computing element 110 (interchangeably referred to as programmable logical element 110, herein), and correspondingly, at block 310, timing of the processing element 102 can be adjusted. Again, at the block 312, the expiration of the timer is awaited.
[0062] FIG. 4 illustrates a schematic diagram depicting relationship between external timer in programmable logic element and processing element application timer, in accordance with an embodiment of the present disclosure.
[0063] In an embodiment, the processing element’s timer 104 can be initiated while starting the applications. In an exemplary embodiment, the processing element’s timer 100 can run in the order of 400 micro-seconds in view of the non-real time environment. The application on the processing element may wait for timer completion to resume further processing operations. On completion of the specified timing from the processing element’s timer 104, the application can resume for subsequent processing operations. Moreover, timing information passed by the processing element’s timer 104 can be captured before the request and after the timer completion as a system time stamp. In an implementation, the timing information from the processing element’s timer 104 can be processed in application at an arbitrary time for further events. Each timing data returned from the processing element’s timer 104 may induce an error due to the inhibit operating system overheads. Hence, the timing data exhibited by the processing element’s timer 104 in each cycle can be arbitrary and can carry a delta erroneous in timing information.
[0064] In an embodiment, the processing element’s timer can be periodically used for processes in applications. The erroneous timing data captured in each cycle shall be carried forward for each processing cycle in application causing a drift in the timer which further affects the timing of different processes executed in application. This drift behaviour of processing element’s timer when utilized in application space of non-real time OS affects the schedules of various time-critical processes.
[0065] In an illustrative embodiment, graphical representation, as illustrated in FIG. 5, depicts extended timing drift due to multiple interrupts corresponding to the processing element’s timer drift log –

TimeStamp Ref of Interrupt Interrupt Time Achieved (usec) Timing Deviation of Interrupt for 400usecs (usec) Timing Drift (usec)
2569 357 -43 -43
3220 369 -31 -74
8954 368 -32 -106
29072 364 -36 -142
33954 365 -35 -177
57552 358 -42 -219
58954 367 -33 -252
72152 357 -43 -295
78032 357 -43 -338
78404 367 -33 -371
83954 367 -33 -404
93392 358 -42 -446
98512 358 -42 -488
103632 359 -41 -529
108954 367 -33 -562
113872 358 -42 -604
117552 360 -40 -644
118992 361 -39 -683
124112 358 -42 -725
129232 357 -43 -768

[0066] In an embodiment, the external periodic timer 112 in the programmable logic element 110 with an integral multiple of required processing element’s frequency/ timing can be configured to compensate for the drift and update the application timing information. A periodic timer can be set by the processing element in the programmable logic element before starting the time critical applications. The periodic timer set by the processing element to the programmable logic element can be a higher order integer multiple of the processing element timer. In an exemplary embodiment,, it can be in order of 250
[0067] In one embodiment, this periodic timing data communicated from the processing element to the programmable logic element and computed on the programmable logic element for interrupting the processing element, which is herein referred as the programmable logic element timer. Therefore, the programmable logic element starts ticking the external timer. The Programmable logic element timer can interrupt the processing element through Ethernet or UART interfaces after expiry of every programmable logic element timer period.
[0068] As illustrated in FIG. 3, the processing element can get periodic interrupts from the programmable logic element in every 100 ms (milliseconds). This interrupt received by the processing element can be interpreted in to application space for correction of timestamping in further processing of the processing element timer. Further, the processing element can compensate the drift of the application’s timer in next cycle.
[0069] In an embodiment, the processing element can acknowledge the interrupts to the programmable logic element to ensure the processing element timer drift is compensated. Based on the interrupt from the programmable logic element, the processing element can adjust its internal application timer periodically, thereby the processing element may control the timer drift in critical applications.
[0070] HPET timer and HR Timers can be tested with power pc based bench marking system running real-time operating system (RTOS) and the results may be compared with power pc hardware timers.
[0071] In one embodiment, the time stamping can be done between the consecutive packets received from Intel processor board via Ethernet on power pc.
[0072] In an experimentation method, HPET and HR timers can run on Intel processor and schedule the packets after expiration of timer interval period of, for example, 100 micro seconds or more to power pc running with lynx real-time operating system (RTOS) via Ethernet UDP protocol.
[0073] In an illustrative embodiment, while tested the system with HPET timer and high resolution (HR) timers for system performance with 400 micro seconds timer interrupts. HR timer performance is found to be better than HPET timer performance. In an embodiment, the experiment can be conducted for longer duration for verifying any time drift or accumulation of time in timer interrupts generation. The accumulated drift observed in HR and HPET hardware timers can affect the threads scheduling over a period of time. Hence, a methodology to compensate this drift using an accurate external timer implemented on the programmable logic element is devised.
[0074] In an embodiment, the timer can be implemented exclusively on external programmable logic element device and further interrupt response can be given to the processing element using serial communication interface.
[0075] In an implementation, the test can be carried out through following steps– (1) Transmit packets from requesting timer to external logging device, (2) Receive the packet on external logging device and save the timestamp, (3) Transmit timer request to the programmable logic element, (4) Receive the timer request from the processing element in programmable logic element, (5) Initialization and running timer component count as per the requested timing in the programmable logic element, (6) Transmit timer completion response from the programmable logic element to the processing element after timer count completion, (7) Receive the timer completion response at the processing element from the programmable logic element, (8) Transmit timer acknowledgement to the programmable logic element from the processing element, (9) Receive the timer acknowledgement from the processing element in the programmable logic element, and (10) Timer request at Programmable logic element is cleared. This is to ensure that timer completion response is received at the processing element.
[0076] In this test, the programmable logic element can run the timer for a scaled value of the hardware timer on the processing element. Typically, 100 msecs (milli seconds) timer is implemented on Programmable logic element for compensation timing on the processing element. This is a scale factor of 250 in reference to the processing element timing of 400usecs. When the timer on the programmable logic element is interrupted, the accumulated timing on the processing element is reset and threads are scheduled as per the new timing on the processing element.
[0077] In an illustrative embodiment, as in FIG. 6, a graphical representation depicts compensated time drifts and multiple interrupts as per an excerpt of application timer compensation log –

TimeStamp Ref of Interrupt Interrupt Time Achieved (usec) Timing Deviation of Interrupt for 400usecs (usec) Compensated Timing Drift (usec)
1922552 369 -31 -9744
1941712 358 -42 -9786
1972432 358 -42 -9828
1972994 358 -42 -9870
1977552 350 -50 -9920
1982672 358 -42 -9962
1987792 358 -42 -10004
1992912 358 -42 -10046
1968 358 -42 -42
4072 358 -42 -84
11636 358 -42 -126
20279 357 -43 -169
29530 358 -42 -211
33588 359 -41 -252
44680 358 -42 -294
47619 358 -42 -336
55288 369 -31 -367

[0078] FIG. 7 illustrates a flow diagram of the proposed method, in accordance with an embodiment of the present disclosure.
[0079] In an embodiment, the method 700 includes, at block 702, receiving, at a scheduling device, a set of first data packets pertaining to a request raised from a first computing element comprising a first timer configured to run at a first pre-defined frequency.
[0080] In an embodiment, the method 700 includes, at block 704, transmitting, at the scheduling device, the received set of first data packets to a second computing element comprising a second timer configured to run at a second pre-defined frequency, wherein the second timer gets actuated in response to receipt of the transmitted set of first data packets.
[0081] In an embodiment, the method 700 includes, at block 706, obtaining, at the scheduling unit, a set of second data packets pertaining to completion of a pre-defined count at the second timer, wherein the obtained set of second data packets are being transmitted to the first computing element.
[0082] In an embodiment, the method 700 includes, at block 708, an adjustment in any drift occurred in timing of the first timer is being carried out by the first computing element based on the set of second data packets.
[0083] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive patent matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “includes” and “including” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refer to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[0084] The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practised with modification within the spirit and scope of the appended claims.
[0085] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0086] The present disclosure provides a smart, economically feasible, and efficient system and method for enabling adjustment in any drift occurred in a timer.
[0087] The present disclosure provides a system and method for adjusting drift in the timing in a non-real time operating system environment using HPET and HRT internal timers of x86 processing elements in coherence with the hardware timers on programmable logic element in a non-real time operating systems.
[0088] The present disclosure provides a system and method for high resolution time out generation in the kernel space.
[0089] The present disclosure provides a system and method to adjust the accumulated timing drift errors due to context switching from the kernel space to user space scheduling delay at random time intervals.
[0090] The present disclosure provides a system and method equipped with custom protocol to manage interrupt chain between processing element and programmable logic element for timing initiation and request closure.