CLIAMS:WE CLAIM
1. A method for dynamically adjusting a low power clock frequency of a host device, the method comprising:
dynamically determining an initial frequency of a low power clock of the host device at which a low power link between the host device and a peripheral device is operational;
computing a low power clock frequency range of the host device based on the initial frequency of the low power clock;
assessing the low power link in the low power clock frequency range; and
adjusting the low power clock frequency to a typical frequency of the low power clock frequency range based on the assessment.
2. The method of claim 1, further comprising detecting a coupling of the peripheral device to the host device.
3. The method of claim 1, further comprising setting a control-data read clock of the host device to the low power clock of the host device.
4. The method of claim 1, wherein dynamically determining the initial frequency of the low power clock comprises:
sweeping a plurality of frequencies of the low power clock of the host device;
assessing the low power link at each of the plurality of frequencies; and
determining the initial frequency of the low power clock based on the assessment.
5. The method of claim 4, wherein sweeping comprises setting, at a first instance, the low power clock frequency to a pre-determined frequency and iteratively setting, at a subsequent instance, the low power clock frequency to an updated frequency.
6. The method of claim 4, wherein assessing the low power link at each of the plurality of frequencies comprises:
initiating a write command from the host device to write data on at least one register of the peripheral device;
initiating a read command by the host device to read data from the at least one register of the peripheral device; and
comparing the read data with the write data for a data parity.
7. The method of claim 4, wherein determining the initial frequency of the low power clock comprises determining a frequency from the plurality of frequencies at which a data parity occurred while assessing.
8. The method of claim 1, wherein computing the low power clock frequency range comprises determining a maximum, a minimum, and a typical low power clock frequencies based on the initial frequency of the low power clock and one or more predetermined ratios.
9. The method of claim 1, wherein assessing the low power link in the low power clock frequency range comprises assessing the low power link for each of a set of frequencies selected from within the low power clock frequency range by:
initiating a write command from the host device to write data on at least one register of the peripheral device;
initiating a read command by the host device to read data from the at least one register of the peripheral device; and
comparing the read data with the write data for a data parity.
10. The method of claim 1, wherein adjusting comprises adjusting the low power clock frequency to the typical frequency of the low power clock frequency range for which a data parity occurred throughout the low power clock frequency range while assessing.
11. The method of claim 1, further comprising resetting a control-data read clock of the host device to a receive low power clock of the host device.
12. A system, comprising:
a circuitry for dynamically adjusting a low power clock frequency of a host device by performing operations comprising:
dynamically determining an initial frequency of a low power clock of the host device at which a low power link between the host device and a peripheral device is operational;
computing a low power clock frequency range of the host device based on the initial frequency of the low power clock;
assessing the low power link in the low power clock frequency range; and
adjusting the low power clock frequency to a typical frequency of the low power clock frequency range based on the assessment.
13. The system of claim 12, wherein the operations further comprise detecting a coupling of the peripheral device to the host device.
14. The system of claim 12, wherein dynamically determining the initial frequency of the low power clock comprises:
sweeping a plurality of frequencies of the low power clock of the host device;
assessing the low power link at each of the plurality of frequencies; and
determining the initial frequency of the low power clock based on the assessment.
15. The system of claim 14, wherein sweeping comprises setting, at a first instance, the low power clock frequency to a pre-determined frequency and iteratively setting, at a subsequent instance, the low power clock frequency to an updated frequency.
16. The system of claim 14, wherein assessing the low power link at each of the plurality of frequencies comprises:
initiating a write command from the host device to write data on at least one register of the peripheral device;
initiating a read command by the host device to read data from the at least one register of the peripheral device; and
comparing the read data with the write data for a data parity.
17. The system of claim 14, wherein determining the initial frequency of the low power clock comprises determining a frequency from the plurality of frequencies at which a data parity occurred while assessing.
18. The system of claim 14, wherein computing the low power clock frequency range comprises determining a maximum, a minimum, and a typical low power clock frequencies based on the initial frequency of the low power clock and one or more predetermined ratios.
19. The system of claim 12, wherein assessing the low power link in the low power clock frequency range comprises assessing the low power link for each of a set of frequencies selected from within the low power clock frequency range by:
initiating a write command from the host device to write data on at least one register of the peripheral device;
initiating a read command by the host device to read data from the at least one register of the peripheral device; and
comparing the read data with the write data for a data parity.
20. The system of claim 12, wherein adjusting comprises adjusting the low power clock frequency to the typical frequency of the low power clock frequency range for which a data parity occurred throughout the low power clock frequency range while assessing.
21. The system of claim 12, wherein the system comprises a mobile device, the circuitry comprises a mobile industry processor interface (MIPI) circuitry; the host device comprises a MIPI host device, and the peripheral device comprises a MIPI peripheral device.
22. A non-transitory computer-readable medium storing processor-executable instructions for:
dynamically determining an initial frequency of a low power clock of the host device at which a low power link between the host device and a peripheral device is operational;
computing a low power clock frequency range of the host device based on the initial frequency of the low power clock;
assessing the low power link in the low power clock frequency range; and
adjusting the low power clock frequency to a typical frequency of the low power clock frequency range based on the assessment.

Dated this 24th day of March, 2015
Shwetha A Chimalgi
Of K&S Partners
Agent for the Applicant

,TagSPECI:TECHNICAL FIELD
This disclosure relates generally to a host-peripheral interface, and more particularly to system and method for dynamically adjusting a low power clock frequency of a host device upon detecting coupling of a peripheral device to the host device.