Claims:WE CLAIM:
1. A method for dynamically switching a high-speed clock of a host device, the method comprising:
determining a status of the host device and a peripheral device coupled to the host device with respect to a transmission and a reception of high-speed data respectively; and
switching the high-speed clock between the host device and the peripheral device based on the status.

2. The method of claim 1, wherein determining the status further comprises sending a notification on high-speed clock initiation from the host device to the peripheral device.

3. The method of claim 2, wherein determining the status further comprises receiving an indication from the peripheral device on a readiness to receive the high-speed data in response to the notification on high-speed clock initiation.

4. The method of claim 3, wherein switching the high-speed clock further comprises enabling the high-speed clock in response to the indication on the readiness to receive the high-speed data.

5. The method of claim 4, further comprising transferring the high-speed data from the host device to the peripheral device upon enabling the high-speed clock.

6. The method of claim 1, wherein determining the status further comprises receiving an indication from the peripheral device on a completion of transmission of the high-speed data.

7. The method of claim 6, wherein switching the high-speed clock further comprises disabling the high-speed clock in response to the indication on the completion of transmission of the high-speed data.

8. The method of claim 6, wherein receiving the indication on the completion of transmission of the high-speed data further comprises:
detecting an end of the high-speed data being transferred from the host device to the peripheral device; and
switching a plurality of data lanes to a low-power mode upon detecting the end of the high-speed data.

9. A system, comprising:
a circuitry for dynamically switching a high-speed clock of a host device by performing operations comprising:
determining a status of the host device and a peripheral device coupled to the host device with respect to a transmission and a reception of high-speed data respectively; and
switching the high-speed clock between the host device and the peripheral device based on the status.

10. The system of claim 9, wherein determining the status further comprises sending a notification on high-speed clock initiation from the host device to the peripheral device.

11. The system of claim 10, wherein determining the status further comprises receiving an indication from the peripheral device on a readiness to receive the high-speed data in response to the notification on high-speed clock initiation.

12. The system of claim 11, wherein switching the high-speed clock further comprises enabling the high-speed clock in response to the indication on the readiness to receive the high-speed data.

13. The system of claim 12, wherein the operations further comprise transferring the high-speed data from the host device to the peripheral device upon enabling the high-speed clock.

14. The system of claim 9, wherein determining the status further comprises receiving an indication from the peripheral device on a completion of transmission of the high-speed data.

15. The system of claim 14, wherein switching the high-speed clock further comprises disabling the high-speed clock in response to the indication on the completion of transmission of the high-speed data.

16. The system of claim 14, wherein receiving the indication on the completion of transmission of the high-speed data further comprises:
detecting an end of the high-speed data being transferred from the host device to the peripheral device; and
switching a plurality of data lanes to a low-power mode upon detecting the end of the high-speed data.

Dated this 30th day of October, 2015
Swetha S.N
Of K&S Partners
Agent for the Applicant

, Description:TECHNICAL FIELD
This disclosure relates generally to a host-peripheral interface, and more particularly to system and method for dynamically switching a high-speed clock of a host device.