Claims:1. A system for enabling high speed communication return path for a plurality of signals, wherein each signal of the plurality of signals has its own return path, and wherein at least one signal of the plurality of signals takes the return path of the shield (DGND) to enable lowest inductance.
2. The system of claim 1, wherein the signal is a power signal or a communication signal.
3. The system of claim 1, wherein the system comprises a first CPU and a second CPU that are operatively coupled with each other using RS485 protocol through a RS485 transceiver and a RS485 connector.
4. The system of claim 3, wherein theat least one signal interfaces between an internal circuit and the RS485 transceiver.
5. The system of claim 3, wherein output signal and input signal between the first CPU and the second CPU are communicated between the respective CPU and the RS485 transceiver, and wherein such output signal and input signal have their own return path (DGND).
6. The system of claim 3, wherein signals between the RS485 transceiver and the RS485 connector have their own return path (RS_ISO_GND 218).
7. The system of claim 1, wherein the system comprises a first CPU and a second CPU that are operatively coupled with each other using Ethernet protocol through an Ethernet switch and an Ethernet connector, wherein the each signal between the first CPU and the second CPU has its own return path.
, Description:TECHNICAL FIELD
The present disclosure relates generally to the field of high speed communication. In particular it pertains to a system and method for a high speed communication return path.

BACKGROUND
Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
ISO3086T is an isolated differential line transceiver with integrated oscillator outputs that provide primary voltage for an isolation transformer. The device is a full-duplex differential line transceiver for RS485 and RS422 applications that can easily be configured for half-duplex operation by connecting pin 11 to pin 14, and pin 12 to pin 13. Any cabled I/O can be subjected to electrical noise transients from various sources. These noise transients can cause damage to the transceiver and/or near-by sensitive circuitry if they are of sufficient magnitude and duration. These isolated devices can significantly increase protection and reduce the risk of damage to expensive control circuits.
The ISO3086T PIN descriptions are as follows:
PIN Name PIN No I/O DESCRIPTION
D1 1 O Transformer Driver Terminal 1, Open Drain Output.
D2 2 O Transformer Driver Terminal 2, Open Drain Output.
GND1 3 – Logic-side Ground.
VCC1 4 – Logic-side Power Supply.
R 5 O Receiver Output.
(RE) ¯ 6 I Receiver Enable Input. This pin has complementary logic.
DE 7 I Driver Enable Input.
D 8 I Driver Input.
GND2 9, 15 – Bus-side Ground. Both pins are internally connected.
NC 10 – No Connect. This pin is not connected to any internal circuitry.
Y 11 O Non-inverting Driver Output.
Z 12 O Inverting Driver Output.
B 13 I Inverting Receiver Input.
A 14 I Non-inverting Receiver Input.
VCC2 16 – Bus-side Power Supply.

A U.S. Patent No. 629,051,481 describes “Low-inductance low-resistance electrical connector” that explains a low-inductance, low-resistance electrical connector for delivering power from a power supply to an IC module comprises a ground contact, a processor power contact and a cache power contact stamped from pure copper sheets and separated from each other by thin insulation film. Plastic members are provided with spring arms to engage with and thus provide sufficient normal force for contact arms of the corresponding contacts to engage with corresponding contact pads of the IC module thereby ensuring a reliable electrical connection. Whereas, the low-inductance, low-resistance electrical connector has been used for making a connection between a speed, module and its power supply.
Communication between two devices like a computer system, externally connected to another computer system or devices by means of high data rate cables or Ethernet cables usually fails or gets interrupted due to physical disturbances. The interruption causes loss of communication between the two systems or devices and also causes the resetting of IC’s.
Therefore, there is a requirement in the art for a methodology that can minimize risk of occurrence of such communication failure.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about”. Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all Markush groups used in the appended claims.

OBJECTS OF THE INVENTION
Ag eneral object of the present disclosure is to provide a system and method for a high-speed communication return path.

SUMMARY
Aspects of the present disclosure relate to a system and method for a high speed communication return path. In an aspect, every signal should have its own return path, be it a power signal or a communication signal. Defining proper return of the signal depends on the frequency at which the signal is working. Low frequency can take the return path of low resistances, whereas high frequency signals can take return path shaving low inductance path. As far as the whole system is concerned, it should have a common ground.
In an aspect, when using the same return path in earlier systems, the systems were susceptible to communication failure as well as resetting of the CPU. A well thought circuit design with a well-designated return path can take care of unwanted communication failures and CPU resetting.
In an aspect, a high speed communication return path of a signal can take the return path of the shield (i.e., Chassis Ground) instead of the PCB (DGND), which can be the lowest inductance path through which communication loss can be minimized to a large extent.
In an aspect, the return path of an external communication port can be its low inductance path, i.e., the shield/ enclosure ground.
Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
FIG. 1 illustrates an exemplary block diagram of RS485 communication in accordance with embodiments of the present disclosure.
FIG. 2 illustrates an exemplary RS485 communicationcircuit diagramin accordance with embodiments of the present disclosure.
FIG. 3 illustrates an exemplary block diagram of Ethernet communication in accordance with embodiments of the present disclosure.
FIG. 4 illustrates an exemplary Ethernet communicationcircuit diagramin accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION
The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
Various terms as used herein. To the extent a term used in a claim is not defined, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
Aspects of the present disclosure relate to a system and method for a high speed communication return path. In an aspect, every signal should have its own return path, be it a power signal or a communication signal. Defining proper return of the signal depends on the frequency at which the signal is working. Low frequency can take the return path of low resistances, whereas high frequency signals can take return paths having low inductance path. As far as the whole system is concerned, it should have a common ground.
In an aspect, when using the same return path in earlier systems, the systems were susceptible to communication failure as well as resetting of the CPU. A well thought circuit design with a well-designated return path can take care of unwanted communication failures and CPU resetting.
In an aspect, a high speed communication return path of a signal can take the return path of the shield (i.e., Chassis Ground) instead of the PCB (DGND), which can be the lowest inductance path through which communication loss can be minimized to a large extent.
In an aspect, the return path of an external communication port can be its low inductance path, i.e., the shield/ enclosure ground.
FIG. 1 illustrates an exemplary block diagram 100 of RS485 communication in accordance with embodiments of the present disclosure. In an embodiment, the central processing unit (CPU) 102 can be configured to communicate with another CPU or any other system following RS485 protocol through a RS485 transceiver 104 and a RS485 connector 106. Each and every communication signals can have their own return paths (as discussed in FIG. 2).
FIG. 2 illustrates an exemplaryRS485 communicationcircuit diagram 200 in accordance with embodiments of the present disclosure. In an embodiment, the ISO3086TDW 214 circuit can be an isolated RS485 transceiver that can communicate with external RS485 bus interface to internal circuit. Each and every signal can have its own return path (Ground).Signals that can be interfaced between internal circuit and transceiver use the return path of DGND, whereas the RS485 external bus can take the return path of its shield ground, which can act as low resistance/ inductance path to transmit and receive signals. In an embodiment, this circuit design can ensure that any noise or fault generated at the external communication cannot impact the communication, i.e., communication failure as well as internal circuit failure/ resetting can be avoided altogether.
As shown in FIG. 2, the receiver output signal MCU_RS485_RXD2 206, the receiver enable input signal MCU_RS485_RE 202, the driver enable input signal MCU_RS485_DE 208, and the driver input signal MCU_RS485_TXD2204 can be communicated between the CPU 102 and the RS485 transceiver 104.In an embodiment, the signals mentioned above can have their own return path, viz., DGND 212 and can have a power supply, viz., C3V3 210.
In an embodiment, the signals TX- 220,TX+ 222,RX- 224, and RX+ 226 can be communicated between the RS485 transceiver and the RS485 connector. In an embodiment, the signals mentioned above can have their own return path, viz., RS_ISO_GND218 and can have a power supply, viz., ISO_RS_5V 216.
In an embodiment, since these signals, before and after the RS485 transceiver, have their own voltage references, they should have their return path too so that any unwanted noise or external disturbance which can occur from RS485 connector cannot affect the CPU. In an embodiment, when using the same return path in earlier systems, the systems were susceptible to communication failure as well as resetting of the CPU. A well thought circuit design with a well designated return path, as discussed in FIG. 2, can take care of unwanted communication failures and CPU resetting.
In an embodiment, RS_ISO_GND 218 can be the shield/ enclosure ground, i.e., the low inductance path (return path).
FIG. 3 illustrates an exemplary block diagram 300 of Ethernet communication in accordance with embodiments of the present disclosure. In an embodiment, the CPU 302 can be configured to communicate with another CPU or any other system following Ethernet protocol through an Ethernet switch304 and an Ethernet connector RJ45+ Internal Magnetics 306. Every communication signals can have their own return paths (as discussed in FIG. 4).
FIG. 4 illustrates an exemplary Ethernet communicationcircuit diagram 400 in accordance with embodiments of the present disclosure. In an embodiment, the Ethernet communication circuit can get isolated from the internal circuit with the internal magnetics present at RJ45 circuit. Each every signal has its own return path (Ground).Signals which can be interfaced between internal circuit and transceiver uses the return path of DGND, where as the Ethernet external bus takes the return path of its shield ground which can act as low resistance/ inductance path to transmit and receive signals. In an embodiment, this circuit design can ensure that any noise or fault generated at external communication cannot impact the communication, i.e., communication failure as well as internal circuit failure/ resetting can be avoided altogether.
In an embodiment, the signals TXM2 402, TXP2 404, RXM2 406 and RXP2 408 can be communicated between the CPU 302 and Ethernet switch 304. In an embodiment, the signals mentioned above can have their own return path, viz., DGND 412 and can have a power supply, viz., 3V3A 410.
In an embodiment, RJ45 can have internal magnetics. It can take the return path as shield of connector so that any unwanted noise or external disturbance which can occur from Ethernet connector cannot affect CPU of the system. In an embodiment, when using the same return path in earlier systems, the systems were susceptible to communication failure as well as resetting of the CPU. A well thought circuit design with a well designated return path, as discussed in FIG. 4, can take care of unwanted communication failures and CPU resetting.
In an embodiment, PGND can be the shield/ enclosure ground, i.e., the low inductance path (return path).
While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
The present disclosure provides a system and method for a high-speed communication return path.